CN114864663A - Silicon carbide Schottky diode and manufacturing method thereof - Google Patents
Silicon carbide Schottky diode and manufacturing method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 172
- 238000002161 passivation Methods 0.000 claims description 92
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 20
- 229910052760 oxygen Inorganic materials 0.000 claims description 20
- 239000001301 oxygen Substances 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 2
- 239000012790 adhesive layer Substances 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000007774 longterm Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 239000011368 organic material Substances 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66007—Multistep manufacturing processes
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- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Abstract
A silicon carbide Schottky diode and a method for manufacturing the same. Relates to the field of semiconductors. The silicon carbide substrate comprises an epitaxial layer arranged on the front surface of the silicon carbide substrate and an ohmic contact electrode arranged on the back surface of the silicon carbide substrate; a lower metal layer is arranged on the ohmic contact electrode; further comprising: the P-type doped region extends downwards from the top of the epitaxial layer; the first field oxide is arranged on the top of the epitaxial layer; the second field oxide is arranged at the top of the epitaxial layer and positioned on the side part of the first field oxide, and a front metal contact electrode is arranged above the P-type doped region and connected with the side part of the first field oxide; an upper metal layer disposed above the front metal contact electrode; the invention reduces the influence of external charges or electric fields on the surface of the device, and can effectively protect the long-term stability and reliability of the voltage resistance of the device.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a silicon carbide Schottky diode and a manufacturing method thereof.
Background
The silicon carbide is used as a third-generation semiconductor material, the critical breakdown field strength of the silicon carbide is 10 times that of a Si material, the forbidden bandwidth and the heat conductivity of the silicon carbide are 3 times that of the Si material, and the concentration of an intrinsic carrier is only one tenth of that of the Si material, so that the silicon carbide becomes an ideal material for manufacturing high-voltage, high-power, high-frequency and high-temperature resistant devices.
Silicon carbide power devices generally include device types such as JBS, MPS, MOSFET, JFET, IGBT, etc., and after the devices are manufactured, CP test (chipprobe) is performed in the industry to calibrate the defective products of the chips. It is known that the reliability of power semiconductors is one of the important characteristics of products, and the operational capability under high humidity environment is a key index for testing the reliability of devices
However, for a high-voltage-withstanding silicon carbide device, the reverse avalanche voltage is usually above 1400V, and in the CP test process, air ionization between the front electrode of the wafer and the scribe line may occur, which may cause an Arcing (Arcing) phenomenon, and damage the wafer and the test equipment, so that the extremely high avalanche voltage may bring a certain difficulty to the wafer test link. In addition, according to the market demand, a product with higher reliability must be developed to have higher market competitiveness, and particularly, the operation capability of the device in an HV-H3TRB (High-voltage High-temperature High-humidity reversible bias) environment is tested, so that the design and processing of the device are higher in complexity and higher in difficulty.
Disclosure of Invention
Aiming at the problems, the invention provides the silicon carbide Schottky diode which can avoid the sparking phenomenon in the CP test process and greatly enhance the robustness of the device under H3TRB and the manufacturing method thereof.
The technical scheme of the invention is as follows: a silicon carbide Schottky diode comprises an epitaxial layer arranged on the front surface of a silicon carbide substrate and an ohmic contact electrode arranged on the back surface of the silicon carbide substrate; a lower metal layer is arranged on the ohmic contact electrode; further comprising:
the P-type doped region extends downwards from the top of the epitaxial layer;
the first field oxide is arranged on the top of the epitaxial layer;
a second field oxide arranged on the top of the epitaxial layer and positioned at the side part of the first field oxide,
the front metal contact electrode is arranged above the P-type doped region, and the side part of the front metal contact electrode is connected with the first field oxide;
an upper metal layer disposed above the front metal contact electrode;
the passivation layer is arranged above the metal layer and the first field oxide; and
the PI glue is positioned at the top of the device and extends downwards to the epitaxial layer through the passivation layer; and a distance is reserved between the PI glue and the side part of the device to form a scribing channel.
Specifically, the passivation layer includes:
the first passivation layer is arranged above the upper metal layer and the first field oxide;
and the second passivation layer is arranged above the second field oxide.
Specifically, the passivation layer I and the passivation layer II sequentially consist of a semi-insulating polycrystalline silicon layer and a silicon nitride layer from bottom to top.
Specifically, the second field oxide layer and the passivation layer are matched with the scribing channel area.
Specifically, the first field oxide and the second field oxide and the first passivation layer and the second passivation layer are respectively arranged at intervals;
the passivation layer wraps the first field oxide layer;
and the second passivation layer is wrapped on the second field oxide.
A method for manufacturing a silicon carbide Schottky diode comprises the following steps:
s001, growing an epitaxial layer on the silicon carbide substrate;
s002, forming a P-type doped region in the epitaxial layer through ion implantation;
s003, depositing field oxygen I and field oxygen II on the front surface of the device;
s004, forming a metal contact electrode on the front surface of the device;
s005, depositing an upper metal layer above the metal contact electrode to be used as an electrode to be led out;
s006, manufacturing a first passivation layer and a passivation layer at the terminal positions of the device respectively;
s007, manufacturing a PI adhesive layer at the terminal position of the device;
s008, manufacturing an ohmic contact electrode on the back of the silicon carbide substrate;
and S009, depositing a lower metal layer on the ohmic contact electrode to finish the manufacture of the device.
Specifically, in step S002, a P-type doped region is formed by one-time ion implantation, the doped impurity is Al, the implantation temperature is 400-.
Specifically, step S003 is to form a layer of SiO2 by chemical vapor deposition in advance, and then to form field oxide one and field oxide two by etching.
Specifically, before the passivation layer one and the passivation layer two are fabricated in step S006, a SiPOS film and a silicon nitride film are sequentially deposited from bottom to top, and then a passivation layer one (8) and a passivation layer two (9) are formed by etching.
The invention has the beneficial effects that:
1. the second field oxide layer and the second passivation layer are covered under the scribing channel area, when reverse pressure is applied, especially when high voltage of more than 1000V is applied, the equipotential surface of the back electrode is on the surface of the scribing channel, but because the field oxide (SiO 2) and the d passivation layer (silicon nitride) exist in the scribing channel, the relative dielectric constant is high, the insulating property is good, and ionization formation does not occur between the upper metal layer of the wafer and the surface of the scribing channel, so the sparking phenomenon can be avoided.
2. The wafer is decomposed into a single chip in the cutting scribing channel area 13, and HV-H3TRB examination and verification are carried out on the device after sealing and testing are finished. The field oxygen has stronger hydroscopicity because its material characteristic, and silicon nitride and PI glue film in the passivation layer have fine water-proof effects, if passivation layer and PI glue film can not fine protection field oxygen, whole passivation layer and PI just can not fine isolated steam, because the device terminal constantly absorbs steam through field oxygen under high humid air spare, the field ring portion that leads to having steam is under high withstand voltage condition, the electric leakage is too big, the water electrolysis takes place easily, lead to the device to become invalid. And a gap interval is reserved between every two of the first field oxide and the second field oxide and the first passivation layer and the second passivation layer through subsection deposition in the edge area of the scribing channel. The peripheral silicon nitride layer of passivation structure of parcel formula can be fine protects field oxygen, and isolated steam passes through field oxygen and gets into the terminal, and the Pi glue at top also has outstanding waterproof performance simultaneously, further promotes the reliability of device under HV-H3 TRB.
3. The resistivity of SiPOS in the passivation layer is greatly lower than that of an organic insulating material, when the temperature is high, movable ions in the outer organic material are respectively transported to two electrodes under the action of an electric field, and because the semi-insulating layer has more current carriers, induced charges are generated in the semi-insulating layer, so that power lines of the charges in the organic material are stopped in the semi-insulating layer and cannot reach the surface of a tube core, the effects of shielding the charges and homogenizing the electric field are achieved to a certain extent, the influence of external charges or the electric field on the surface of a device is reduced, and the long-term stability and the reliability of the voltage resistance of the device can be effectively protected.
Drawings
Figure 1 is a schematic view of the structure of the present invention,
figure 2 is a schematic structural diagram of the epitaxial layer grown in step S001,
figure 3 is a schematic structural view of the p-type doped region after the ion implantation of step S002,
FIG. 4 is a schematic structural diagram of the first field oxide and the second field oxide deposited in step S003,
fig. 5 is a schematic structural view of forming a front metal contact electrode in step S004,
figure 6 is a schematic diagram of the structure of step S005 for depositing the thickening metal,
FIG. 7 is a schematic structural diagram of fabricating a first passivation layer and a second passivation layer in step S006,
FIG. 8 is a schematic diagram of the PI cement structure prepared in step S007,
fig. 9 is a schematic structural view of the ohmic contact electrode formed in step S008,
FIG. 10 is a schematic structural diagram of the step S009 of depositing a thickening metal;
FIG. 11 is a photograph of an actual chip showing sparking before improvement;
FIG. 12 is an actual photograph of the improved spark failure;
in the figure, 1 is a silicon carbide substrate, 2 is an epitaxial layer, 3 is a P-type doped region, 4 is a first field oxide, 5 is a second field oxide, 6 is a front metal contact electrode, 7 is an upper metal layer, 8 is a first passivation layer, 9 is a second passivation layer, 10 is PI glue, 11 is an ohmic contact electrode, 12 is a lower metal layer, and 13 is a scribing way.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
The present invention is illustrated in FIGS. 1-12; taking a SiC schottky diode as an example, a typical device manufacturing process includes:
a silicon carbide Schottky diode comprises an epitaxial layer 2 arranged on the front surface of a silicon carbide substrate 1 and an ohmic contact electrode 11 on the back surface; a lower metal layer 12 is arranged on the ohmic contact electrode 11; further comprising:
a P-type doped region 3, wherein the P-type doped region 3 extends downwards from the top of the epitaxial layer 2;
the first field oxide 4 is arranged at the top of the epitaxial layer 2, so that the P-type doped region 3 can be prevented from being damaged in the metal etching process, and a field plate is formed with the front metal contact electrode 6 and the upper metal layer 7 to adjust an electric field;
the second field oxide 5 is arranged at the top of the epitaxial layer 2, is positioned on the side part of the first field oxide 4, covers the whole scribing channel region 13, has high relative dielectric constant and good insulating property, and can effectively avoid the sparking phenomenon;
the front metal contact electrode 6 is arranged above the P-type doped region 3, and the side part of the front metal contact electrode 6 is connected with the field oxide I4;
an upper metal layer 7, wherein the upper metal layer 7 is arranged above the front metal contact electrode 6;
the passivation layer is arranged above the metal layer 7 and the field oxide I4; and
a PI glue 10, said PI glue 10 being located on top of the device (or called termination) and extending down through said passivation layer to said epitaxial layer 2; and a distance is reserved between the PI glue 10 and the side part of the device to form a scribing channel 13. The scribing channel 13 is decomposed into individual chips through wafer cutting equipment for packaging and testing devices;
specifically, the passivation layer includes:
a first passivation layer 8, wherein the first passivation layer 8 is disposed above the upper metal layer 7 and the first field oxide 4;
and the second passivation layer 9, wherein the second passivation layer 9 is arranged above the second field oxide 5.
The first passivation layer 8 and the second passivation layer 9 are respectively arranged above the field oxygen (the first field oxygen 4 or the second field oxygen 5), the bottom of the first passivation layer is contacted with the epitaxial layer 2, and the side parts of the first passivation layer and the second passivation layer are respectively contacted with the front metal contact electrode and the upper metal layer. Because the silicon nitride in the passivation layer has good waterproof effect, the passivation layer covers and wraps the field oxygen, so that water vapor can be effectively prevented from entering the field oxygen, and the reliability of the device is improved;
specifically, the passivation layer (including the passivation layer I8 and the passivation layer II 9) sequentially consists of a semi-insulating polycrystalline silicon (SIPOS) layer and a silicon nitride layer from bottom to top.
The resistivity of SiPOS in the passivation layer is greatly lower than that of an organic insulating material, when the temperature is high, movable ions in the outer organic material are respectively transported to two electrodes under the action of an electric field, and because the semi-insulating layer has more current carriers, induced charges are generated in the semi-insulating layer, so that power lines of the charges in the organic material are stopped in the semi-insulating layer and cannot reach the surface of a tube core, the effects of shielding the charges and homogenizing the electric field are achieved to a certain extent, the influence of external charges or the electric field on the surface of a device is reduced, and the long-term stability and the reliability of the voltage resistance of the device can be effectively protected. The silicon nitride layer on the upper layer has good waterproof effect, can effectively prevent water vapor from entering and further improves the reliability of the device.
Specifically, the second field oxide 5 and the passivation layer 9 are matched with the area of the scribe lane 13.
In this case, the second field oxide 5 and the passivation layer 9 are spread over the entire scribe line 13 region, and both are high dielectric constant materials.
Specifically, the first field oxide 4 and the second field oxide 5, and the first passivation layer 8 and the second passivation layer 9 are respectively arranged at intervals;
the passivation layer I8 is wrapped on the field oxide I4;
the second passivation layer 9 is wrapped on the second field oxide 5.
Because the silicon nitride in the passivation layer has good waterproof effect, the passivation layer covers and wraps the field oxygen to effectively prevent water vapor from entering the field oxygen, and the interval structure ensures that the outermost layer is the passivation layer with good waterproof effect;
a method for manufacturing a silicon carbide Schottky diode comprises the following steps:
s001, growing an epitaxial layer 2 with the thickness of 5-15um on the silicon carbide substrate 1; as shown with reference to FIG. 2; the conductivity types of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 are both generally N type;
s002, forming a P-type doped region 3 in the epitaxial layer 2 through ion implantation; as shown with reference to FIG. 3;
the ion implantation adopted in the step can be single implantation or multiple implantation, the doping impurity is generally Al, the implantation temperature is 400-600 ℃, a P-type doping junction of 0.4-1.0um is generally formed when the implantation is finished, the implantation energy range of the ion implantation covers 30-500keV, and the implantation dosage range covers 1E12-1E16 cm-2. After the implantation is finished, high-temperature annealing at 1600-1900 ℃ is needed for ion activation.
S003, depositing a layer of SiO2 on the front surface (above the epitaxial layer 2) of the device by a chemical vapor deposition method, and then forming a sectional type first deposited field oxide 4 and a sectional type second deposited field oxide 5 by wet etching; the field oxygen thickness of the field oxygen I4 and the field oxygen II 5 is 0.5-2 um; as shown with reference to FIG. 4;
s004, refer to FIG. 5; forming a metal contact electrode 6 on the front surface of the device;
s005, depositing an upper metal layer 7 with the thickness of 1-6um above the metal contact electrode 6 to be taken as an electrode to be led out; as shown with reference to FIG. 6;
s006, respectively manufacturing a first passivation layer 8 and a passivation layer 9 at the terminal positions of the device; as shown with reference to FIG. 7;
in the invention, the first passivation layer 8 and the second passivation layer 9 are both of a double-layer structure and comprise a semi-insulating polysilicon (SIPOS) layer and an inorganic passivation layer of silicon nitride material.
S007 as shown in FIG. 8; a PI glue layer 10 is manufactured at the terminal position of the device, and the PI glue layer is an organic passivation layer mainly made of Polyimide;
s008, as shown in fig. 9; manufacturing an ohmic contact electrode 11 on the back surface of the silicon carbide substrate 1; the manufacturing sequence needs to be adjusted according to whether the wafer is thinned, typically, taking a thinning process as an example, the ohmic electrode 11 on the back side is placed after the thinning process, and the ohmic alloy is completed through laser annealing.
And S009, depositing a lower metal layer 12 of 1-3um on the ohmic contact electrode 11 to finish the manufacture of the device, and referring to FIG. 10.
Specifically, in step S002, a P-type doped region is formed by one-time ion implantation, the doped impurity is Al, the implantation temperature is 400-.
Specifically, step S003 is to form a layer of SiO2 by chemical vapor deposition in advance, and then to form field oxide one 4 and field oxide two 5 by etching.
Specifically, before the passivation layer one 8 and the passivation layer two 9 are formed in step S006, a SIPOS film and a silicon nitride film are sequentially deposited from bottom to top.
In fig. 1, the first field oxide layer 4, the second field oxide layer 5, the first passivation layer 8 and the second passivation layer 9 are typically designed to be a segmented structure formed by deposition and etching, the right side of the first passivation layer 8 completely covers the first field oxide layer 4, the left side of the second passivation layer 9 completely covers the second field oxide layer 5, and a certain distance is maintained between the first passivation layer 8 and the second passivation layer 9. Silicon nitride outside the passivation layer has an excellent waterproof effect, and field oxygen 4 can be effectively prevented from being carried out by water vapor through the interval type passivation structure.
The disclosure of the present application also includes the following points:
(1) the drawings of the embodiments disclosed in the specification only relate to the structures related to the embodiments disclosed in the specification, and other structures can refer to common designs;
(2) in case of conflict, the embodiments and features of the embodiments disclosed in this application can be combined with each other to arrive at new embodiments;
the above embodiments are only embodiments disclosed in the present disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the scope of the claims.
Claims (10)
1. A silicon carbide Schottky diode comprises an epitaxial layer (2) arranged on the front surface of a silicon carbide substrate (1) and an ohmic contact electrode (11) arranged on the back surface; a lower metal layer (12) is arranged on the ohmic contact electrode (11); it is characterized by also comprising:
a P-type doped region (3), wherein the P-type doped region (3) extends downwards from the top of the epitaxial layer (2);
a first field oxide (4), wherein the first field oxide (4) is arranged on the top of the epitaxial layer (2);
a second field oxide (5), wherein the second field oxide (5) is arranged at the top of the epitaxial layer (2) and positioned at the side part of the first field oxide (4),
the front metal contact electrode (6) is arranged above the P-type doped region (3), and the side part of the front metal contact electrode (6) is connected with the field oxide I (4);
an upper metal layer (7), the upper metal layer (7) being disposed above the front side metal contact electrode (6);
the passivation layer is arranged above the metal layer (7) and the field oxide I (4); and
PI glue (10), the PI glue (10) is positioned on the top of the device and extends to the epitaxial layer (2) downwards through the passivation layer; and a distance is reserved between the PI glue (10) and the side part of the device to form a scribing channel (13).
2. The silicon carbide schottky diode of claim 1 wherein the passivation layer comprises:
a first passivation layer (8), wherein the first passivation layer (8) is arranged above the upper metal layer (7) and the first field oxide (4);
and the second passivation layer (9), wherein the second passivation layer (9) is arranged above the second field oxide (5).
3. The SiC Schottky diode according to claim 2, wherein the first passivation layer (8) and the second passivation layer (9) are composed of a semi-insulating polysilicon layer (SIPOS) and a silicon nitride layer from bottom to top.
4. A silicon carbide schottky diode according to claim 1 wherein the second field oxide (5) and passivation layer (9) are adapted to the scribe lane (13) area.
5. The silicon carbide schottky diode as claimed in claim 1, wherein the first field oxide (4) and the second field oxide (5) and the first passivation layer (8) and the second passivation layer (9) are respectively disposed at intervals;
the first passivation layer (8) is wrapped on the first field oxide (4);
the second passivation layer (9) is wrapped on the second field oxide (5).
6. The silicon carbide schottky diode as claimed in claim 1, wherein the P-type doped regions have a plurality of rectangular cross-sections spaced apart from each other.
7. A method for manufacturing a silicon carbide Schottky diode is characterized by comprising the following steps:
s001, growing an epitaxial layer (2) on the silicon carbide substrate (1);
s002, forming a P-type doped region (3) in the epitaxial layer (2) through ion implantation;
s003, depositing field oxygen I (4) and field oxygen II (5) at the front position of the device;
s004, forming a metal contact electrode (6) on the front surface of the device;
s005, depositing an upper metal layer (7) above the metal contact electrode (6) to be taken as an electrode to be led out;
s006, respectively manufacturing a first passivation layer (8) and a second passivation layer (9) at the terminal positions of the device;
s007, manufacturing a PI adhesive layer (10) at the terminal position of the device;
s008, manufacturing an ohmic contact electrode (11) on the back surface of the silicon carbide substrate (1);
and S009, depositing a lower metal layer (12) on the ohmic contact electrode (11) to finish the manufacture of the device.
8. The method as claimed in claim 7, wherein in step S002, a P-type doped region is formed by ion implantation once, the doped impurity is Al, the implantation temperature is 400-1900 ℃, and after the implantation is completed, the ion activation is performed by high temperature annealing at 1600-1900 ℃.
9. The method of claim 7, wherein step S003 is carried out by chemical vapor deposition of a layer of SiO2 and etching to form the first field oxide (4) and the second field oxide (5).
10. The method of claim 7, wherein a SiPOS film and a silicon nitride film are sequentially deposited from bottom to top before the passivation layers I (8) and II (9) are formed in step S006, and then the passivation layers I (8) and II (9) are formed by etching.
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| CN118213273A (en) * | 2024-05-20 | 2024-06-18 | 扬州扬杰电子科技股份有限公司 | Diode for improving reliability of HV-H3TRB and preparation method thereof |
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