CN114864653A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114864653A
CN114864653A CN202110148369.7A CN202110148369A CN114864653A CN 114864653 A CN114864653 A CN 114864653A CN 202110148369 A CN202110148369 A CN 202110148369A CN 114864653 A CN114864653 A CN 114864653A
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Prior art keywords
fins
fin
seed
forming
layer
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CN202110148369.7A
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Chinese (zh)
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王文博
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110148369.7A priority Critical patent/CN114864653A/en
Publication of CN114864653A publication Critical patent/CN114864653A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present application provides a semiconductor structure and a method of forming the same, the structure comprising: a semiconductor substrate; an isolation layer on the surface of the semiconductor substrate; the seed fin is positioned on the side surface of the isolation layer, and the bottom of the seed fin is coplanar with the semiconductor substrate and coplanar with the side surface of the isolation layer; the plurality of fins are positioned on the top surface of the isolation layer and two sides of the seed fin, and the seed fin is coplanar with the top surfaces of the plurality of fins; the metal grid is positioned on the surface of the isolating layer and completely covers the fin; and the interlayer dielectric layers are positioned on the surfaces of the isolation layers on the two sides of the metal grid, and the top surfaces of the interlayer dielectric layers and the top surface of the metal grid are coplanar. The application provides a semiconductor structure and a forming method thereof, wherein sacrificial layers are adopted to support fins, so that the fins can be prevented from toppling over or being adhered.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost continues to increase. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, and the design of three-dimensional structures such as fin field effect transistors (finfets) is becoming a focus of attention in the semiconductor field.
However, as FIN FET technology is further developed, the width of the FINs becomes smaller, the height thereof becomes higher, and the interval between the FINs is also reduced, so that the FINs are easily toppled or stuck to the adjacent FINs. Therefore, there is a need to provide a more effective and reliable solution to prevent the fins from falling or sticking.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can prevent fins from toppling over or being adhered.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a seed fin and isolation layers positioned on two sides of the seed fin are formed on the surface of the semiconductor substrate, and the top surface of each isolation layer is lower than that of the seed fin; alternately forming a plurality of sacrificial layers and a plurality of fins on the side wall of the seed fin; forming a dummy gate layer on the top surfaces and the side walls of the plurality of fins and the plurality of sacrificial layers; forming an interlayer dielectric layer on the surface of the isolation layer, wherein the top surface of the interlayer dielectric layer is coplanar with the top surface of the dummy gate layer; removing the dummy gate layer and the sacrificial layers; a metal gate is formed that completely covers the fins and seed fins.
In some embodiments of the present application, a method of alternately forming a number of sacrificial layers and a number of fins on sidewalls of the seed fins comprises: alternately forming a plurality of sacrificial material layers and fin material layers on the top surface and the side wall of the seed fin; forming a dielectric layer which completely covers the plurality of sacrificial material layers and the fin material layers; grinding the dielectric layer, the sacrificial material layers and the fin material layer by using a chemical mechanical grinding process until the seed fins are exposed; and removing the dielectric layer.
In some embodiments of the present application, the method of alternately forming a plurality of sacrificial material layers and fin material layers on the top surface and sidewalls of the seed fin comprises epitaxial growth.
In some embodiments of the present application, a method of forming the seed fin and the isolation layer includes: providing a semiconductor substrate; etching the semiconductor substrate to form the seed fin; forming a layer of spacer material overlying the semiconductor substrate and the seed fins; grinding the spacer material layer to expose the top surface of the seed fin; and etching back the isolation material layer to form the isolation layer.
In some embodiments of the present application, a height difference between the seed fin and the spacer is 10-100 nanometers.
In some embodiments of the present application, the number of sacrificial layers has a thickness of 5-30 nanometers and the number of fins and the seed fins have a thickness of 3-10 nanometers.
In some embodiments of the present application, the material of the number of sacrificial layers comprises silicon germanium and the material of the number of fins comprises silicon.
Another aspect of the present application also provides a semiconductor structure comprising: a semiconductor substrate; an isolation layer on the surface of the semiconductor substrate; the seed fin is positioned on the side surface of the isolation layer, and the bottom of the seed fin is coplanar with the semiconductor substrate and coplanar with the side surface of the isolation layer; the plurality of fins are positioned on the top surface of the isolation layer and two sides of the seed fin, and the seed fin is coplanar with the top surfaces of the plurality of fins; the metal grid is positioned on the surface of the isolating layer and completely covers the fin; and the interlayer dielectric layers are positioned on the surfaces of the isolation layers on the two sides of the metal grid, and the top surfaces of the interlayer dielectric layers and the top surface of the metal grid are coplanar.
In some embodiments of the present application, a height difference between the seed fin and the spacer is 10-100 nanometers.
In some embodiments of the present application, the seed fin and the plurality of fins have a spacing between 5-30 nanometers and the plurality of fins and the seed fin have a thickness between 3-10 nanometers.
The application provides a semiconductor structure and a forming method thereof, wherein sacrificial layers are adopted to support fins, so that the fins can be prevented from toppling over or being adhered.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 14 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
In the current FIN FET structure manufacturing process, FINs are formed by using a side wall pattern transfer method, and the FINs lack support and are easy to topple (especially when the FINs are thinner and taller), and moreover, the distance between the FINs is also reduced, and the FINs are easy to adhere to each other.
In order to solve the above problems, the present application provides a semiconductor structure and a method for forming the same, in which a high-density fin array is formed by an alternating epitaxy method, and a sacrificial layer is used to support the fins until a metal gate is formed, so as to prevent the fins from toppling over or adhering during the process.
Fig. 1 to 14 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. The semiconductor structure and the forming method thereof according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1 to 5, a semiconductor substrate 100 is provided, a seed fin 110 and an isolation layer 120 located at two sides of the seed fin 110 are formed on a surface of the semiconductor substrate 100, and a top surface of the isolation layer 120 is lower than a top surface of the seed fin 110.
Referring to fig. 1, a semiconductor substrate 100 is provided.
In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
Referring to fig. 2, the semiconductor substrate 100 is etched to form the seed fin 110. The method for etching the semiconductor substrate 100 includes wet etching, dry etching, or the like.
In some embodiments of the present application, the location of the seed fin 110 is located in a central portion of the current semiconductor substrate 100. For the sake of simplicity, the drawings do not necessarily show the structure of the entire semiconductor substrate, but only a portion of the semiconductor substrate (e.g., a separate active region or device region). The seed fin 110 is located at the center to facilitate the growth of the remaining fins to both sides.
Referring to fig. 3, a spacer material layer 120a is formed to cover the semiconductor substrate 100 and the top surface and sidewalls of the seed fins 110. The method for forming the isolation material layer 120a includes a chemical vapor deposition process or a physical vapor deposition process. The material of the isolation material layer 120a includes silicon oxide.
Referring to fig. 4, the spacer material layer 120a is polished to expose the top surface of the seed fin 110. The polishing is, for example, a chemical mechanical polishing process.
Referring to fig. 5, the isolation material layer 120a is etched back to form the isolation layer 120. The back etching is, for example, wet etching or dry etching. The isolation layer 120 may isolate subsequent fins from the semiconductor substrate and may also isolate adjacent active regions.
In some embodiments of the present application, the height difference between the seed fin 110 and the spacer 120 is 10-100 nanometers. The height difference may define the height of the subsequently formed fins, which may be set according to specific requirements.
Referring to fig. 6 to 9, a plurality of sacrificial layers 130 and a plurality of fins 140 are alternately formed on sidewalls of the seed fins 110.
Referring to fig. 6, a plurality of sacrificial material layers 130a and fin material layers 140a are alternately formed on the top surface and sidewalls of the seed fin 110.
In some embodiments of the present application, the method of alternately forming the sacrificial material layers 130a and the fin material layers 140a on the top surface and the sidewalls of the seed fin 110 includes epitaxial growth.
Referring to fig. 7, a dielectric layer 150 is formed to completely cover the plurality of sacrificial material layers 130a and fin material layers 140 a. The method for forming the dielectric layer 150 includes a chemical vapor deposition process or a physical vapor deposition process. The material of the dielectric layer 150 includes silicon oxide or silicon nitride.
Referring to fig. 8, the dielectric layer 150, the sacrificial material layers 130a and the fin material layer 140a are polished by a chemical mechanical polishing process until the top surfaces of the seed fins 110 are exposed.
Referring to fig. 9, the dielectric layer 150 is removed, and a plurality of sacrificial layers 130 and a plurality of fins 140 are alternately formed on the sidewalls of the seed fins 110. The method for removing the dielectric layer 150 includes wet etching or dry etching.
In some embodiments of the present application, the thickness of the number of sacrificial layers 130 is 5-30 nanometers. The thickness of the sacrificial layers 130 is the spacing between the fins.
In some embodiments of the present application, the number of fins 140 and the seed fin 110 have a thickness of 3-10 nanometers. The seed FIN 110 and the FINs 140 together form a FIN structure of a FIN FET device, and thus the seed FIN 110 and the FINs 140 preferably have the same thickness, material, and the like.
In some embodiments of the present application, the material of the number of sacrificial layers 130 comprises silicon germanium and the material of the number of fins 140 comprises silicon.
In some embodiments of the present application, the number of the plurality of fins 140 may be set according to specific process and device performance requirements.
In the conventional process, the fins are separated and disconnected when being formed initially, the fins are not supported, the fins are easy to topple in the subsequent process, and the fins are easy to adhere to each other due to the small space between the fins. In the method for forming a semiconductor structure described herein, referring to fig. 9, the initial fins 140 are supported by the sacrificial layer 130, so that the fins do not fall down, and adhesion between the fins 140 does not occur until the sacrificial layer 130 is removed before the metal gate is formed.
In addition, the fins 140 are isolated from the semiconductor substrate 100 by the isolation layer 120, so that the formation of parasitic transistors in parallel at positions where the gate at the root of the fin 140 cannot be controlled can be avoided, and the fluctuation of the turn-on voltage of the device or the increase of the leakage current can be avoided.
Referring to fig. 10, a dummy gate layer 160 is formed on top surfaces and sidewalls of the plurality of fins 140 and the plurality of sacrificial layers 130 and the seed fins 110. The material of the dummy gate layer 160 includes polysilicon. The method for forming the dummy gate layer 160 includes a chemical vapor deposition process, an etching process, and the like.
In some embodiments of the present application, the top surfaces and sidewalls of the dummy gate layer 160 and the fins 140 and the sacrificial layers 130 and the seed fins 110 may also be formed with an oxide layer (not shown).
In some embodiments of the present application, the method for forming a semiconductor structure may further include: well region ion implantation; forming a side wall; source and drain are formed. The processes for forming the well region, the side wall, and the source and drain are similar to those of the conventional process, and are not described herein.
Referring to fig. 11, an interlayer dielectric layer 170 is formed on the surface of the isolation layer 120, and a top surface of the interlayer dielectric layer 170 is coplanar with a top surface of the dummy gate layer 160. The material of the interlayer dielectric layer 170 includes silicon oxide. The method for forming the interlayer dielectric layer 170 includes a chemical vapor deposition process, a chemical mechanical polishing process, and the like.
Referring to fig. 12, the dummy gate layer 160 is removed. The method for removing the dummy gate layer 160 includes wet etching or dry etching.
Referring to fig. 13, the sacrificial layers 130 are removed. The method for removing the sacrificial layers 130 includes wet etching or dry etching.
The sacrificial layer 130 is removed after the dummy gate layer 160 is removed, and at this time, source and drain regions are already formed at two ends (a direction perpendicular to the plane of the drawing) of the fins 140, and the source and drain regions can continuously support the fins to prevent the fins from toppling over or being adhered.
Referring to fig. 14, a metal gate 180 is formed to completely cover the number of fins 140 and the seed fin 110. The material of the metal gate 180 includes aluminum. The method for forming the metal gate 180 includes a chemical vapor deposition process, a chemical mechanical polishing process, and the like.
In some embodiments of the present application, the method for forming a semiconductor structure may further include: forming contact holes on the surfaces of the metal gate and the source drain; forming metal silicide at the bottom of the contact hole; and forming a contact structure on the surface of the metal silicide. The processes for forming the contact hole, the metal silicide and the contact structure are similar to those of the conventional process, and are not described herein.
In the forming method of the semiconductor structure, before the metal gate is formed, the sacrificial layer is adopted to support the fins, and the sacrificial layer is removed until the metal gate is formed, so that the fins can be prevented from toppling or being adhered in the process.
Embodiments of the present application also provide a semiconductor structure, shown with reference to fig. 14, comprising: a semiconductor substrate 100, wherein a seed fin 110 and an isolation layer 120 located at two sides of the seed fin 110 are formed on the surface of the semiconductor substrate 100, and the top surface of the isolation layer 120 is lower than the top surface of the seed fin 110; a plurality of fins 140 on the isolation layer 120 at both sides of the seed fin 110; a metal gate 180 located on the surface of the isolation layer 120 and completely covering the fins 140 and the seed fins 110; and the interlayer dielectric layer 170 is positioned on the surfaces of the isolation layers 120 at two sides of the metal gate 180, and the top surface of the interlayer dielectric layer 170 is coplanar with the top surface of the metal gate 180.
Referring to fig. 14, in some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) an alloy semiconductor such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, the location of the seed fin 110 is located in a central portion of the current semiconductor substrate 100. For the sake of simplicity, the drawings do not necessarily show the structure of the entire semiconductor substrate, but only a portion of the semiconductor substrate (e.g., a separate active region or device region).
With continued reference to fig. 14, the isolation layer 120 may isolate subsequent fins from the semiconductor substrate, as well as adjacent active regions. The material of the isolation layer 120 includes silicon oxide.
In some embodiments of the present application, the height difference between the seed fin 110 and the spacer 120 is 10-100 nanometers. The height difference may define the height of the subsequently formed fins, which may be set according to specific requirements.
With continued reference to fig. 14, fins 140 are formed on the spacer layer 120 on both sides of the seed fin 110.
In some embodiments of the present application, the pitch between the seed fin 110 and the number of fins 140 is 5-30 nanometers.
In some embodiments of the present application, the number of fins 140 and the seed fin 110 have a thickness of 3-10 nanometers. The seed FIN 110 and the FINs 140 together form a FIN structure of a FIN FET device, and thus the seed FIN 110 and the FINs 140 preferably have the same thickness, material, and the like.
In some embodiments of the present application, the material of the number of sacrificial layers 130 comprises silicon germanium and the material of the number of fins 140 comprises silicon.
In some embodiments of the present application, the number of the plurality of fins 140 may be set according to specific process and device performance requirements.
In the semiconductor structure described herein, the plurality of fins 140 are isolated from the semiconductor substrate 100 by the isolation layer 120, so that a parasitic transistor connected in parallel can be prevented from being formed at a position where the root gate of the fin 140 cannot be controlled, which may cause a device turn-on voltage fluctuation or a leakage current increase.
With continued reference to fig. 14, the isolation layer 120 is formed with a metal gate 180 that completely covers the fins 140 and the seed fins 110. The material of the metal gate 180 includes aluminum.
With reference to fig. 14, an interlayer dielectric layer 170 is formed on the surface of the isolation layer 120 on both sides of the metal gate 180, and the top surface of the interlayer dielectric layer 170 is coplanar with the top surface of the metal gate 180. The material of the interlayer dielectric layer 170 includes silicon oxide.
According to the semiconductor structure and the forming method thereof, the sacrificial layer is adopted to support the fins, so that the fins can be prevented from toppling or being adhered.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements.
It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein a seed fin and isolation layers positioned on two sides of the seed fin are formed on the surface of the semiconductor substrate, and the top surface of each isolation layer is lower than that of the seed fin;
alternately forming a plurality of sacrificial layers and a plurality of fins on the side wall of the seed fin;
forming a dummy gate layer on the top surfaces and the side walls of the plurality of fins and the plurality of sacrificial layers;
forming an interlayer dielectric layer on the surface of the isolation layer, wherein the top surface of the interlayer dielectric layer is coplanar with the top surface of the dummy gate layer;
removing the dummy gate layer and the sacrificial layers;
forming a metal gate completely covering the fins and the seed fin.
2. The method of forming a semiconductor structure of claim 1, wherein the step of alternately forming a plurality of sacrificial layers and a plurality of fins on sidewalls of the seed fins comprises:
alternately forming a plurality of sacrificial material layers and fin material layers on the top surface and the side wall of the seed fin;
forming a dielectric layer which completely covers the plurality of sacrificial material layers and the fin material layers;
grinding the dielectric layer, the sacrificial material layers and the fin material layer by using a chemical mechanical grinding process until the seed fins are exposed;
and removing the dielectric layer.
3. The method of forming a semiconductor structure of claim 2, wherein the step of forming alternating layers of sacrificial material and fin material on the top surface and sidewalls of the seed fin comprises epitaxial growth.
4. The method of forming a semiconductor structure of claim 1, wherein forming the seed fin and the spacer comprises:
providing a semiconductor substrate;
etching the semiconductor substrate to form the seed fin;
forming a layer of spacer material overlying the semiconductor substrate and the seed fins;
grinding the isolation material layer until the top surface of the seed fin is exposed;
and etching back the isolation material layer to form the isolation layer.
5. The method of claim 1, wherein a height difference between the seed fin and the spacer is 10-100 nm.
6. The method of claim 1, wherein the sacrificial layers have a thickness of 5-30nm, and the fins and the seed fins have a thickness of 3-10 nm.
7. The method of forming a semiconductor structure of claim 1, wherein the material of the sacrificial layers comprises silicon germanium and the material of the fins comprises silicon.
8. A semiconductor structure, comprising:
a semiconductor substrate;
an isolation layer on the surface of the semiconductor substrate;
the seed fin is positioned on the side surface of the isolation layer, and the bottom of the seed fin is coplanar with the semiconductor substrate and coplanar with the side surface of the isolation layer;
the plurality of fins are positioned on the top surface of the isolation layer and two sides of the seed fin, and the seed fin is coplanar with the top surfaces of the plurality of fins;
the metal grid is positioned on the surface of the isolating layer and completely covers the fin;
and the interlayer dielectric layers are positioned on the surfaces of the isolation layers on the two sides of the metal grid, and the top surfaces of the interlayer dielectric layers and the top surface of the metal grid are coplanar.
9. The semiconductor structure of claim 8, wherein a height difference between the seed fin and the spacer is 10-100 nanometers.
10. The semiconductor structure of claim 8, wherein a pitch between the seed fin and the plurality of fins is 5-30nm, and a thickness of the plurality of fins and the seed fin is 3-10 nm.
CN202110148369.7A 2021-02-03 2021-02-03 Semiconductor structure and forming method thereof Pending CN114864653A (en)

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Application Number Priority Date Filing Date Title
CN202110148369.7A CN114864653A (en) 2021-02-03 2021-02-03 Semiconductor structure and forming method thereof

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Application Number Priority Date Filing Date Title
CN202110148369.7A CN114864653A (en) 2021-02-03 2021-02-03 Semiconductor structure and forming method thereof

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CN114864653A true CN114864653A (en) 2022-08-05

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