CN114005754A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114005754A
CN114005754A CN202010734868.XA CN202010734868A CN114005754A CN 114005754 A CN114005754 A CN 114005754A CN 202010734868 A CN202010734868 A CN 202010734868A CN 114005754 A CN114005754 A CN 114005754A
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China
Prior art keywords
isolation
layer
forming
fin
fins
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CN202010734868.XA
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Chinese (zh)
Inventor
刘中元
唐建新
徐广州
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Zhongxin Nanfang Integrated Circuit Manufacturing Co ltd
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Zhongxin Nanfang Integrated Circuit Manufacturing Co ltd
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Priority to CN202010734868.XA priority Critical patent/CN114005754A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present application provides a semiconductor structure and a method of forming the same, the structure comprising: the semiconductor substrate comprises fin areas and isolation areas, the isolation areas are used for isolating the adjacent fin areas, and a plurality of fins are formed on the semiconductor substrate of the fin areas; the first isolation layer is positioned on the surface of the semiconductor substrate and partial side walls of the plurality of fins; and the second isolation layer is positioned in the isolation region and penetrates through the first isolation layer. According to the semiconductor structure and the forming method thereof, on one hand, a second isolation material layer is formed in the isolation region, the stress of the second isolation material layer is low, and the stress on the outermost fins in the plurality of fins can be reduced; on the other hand, the stress of the first isolation material layer and the second isolation material layer can be further released by carrying out the annealing process twice. The problem of fin defects can be solved, and the product yield is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost continues to increase. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, and the design of three-dimensional structures such as fin field effect transistors (finfets) is becoming a focus of attention in the semiconductor field.
However, the problem of fin defects still exists in the present FinFET, and a more effective and reliable technical solution needs to be provided.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can solve the problem that fins in a FinFET structure have defects and improve the yield of products.
One aspect of the present application is a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of fin areas and a plurality of isolation areas, the isolation areas are used for isolating adjacent fin areas, and a plurality of fins are formed on the semiconductor substrate of the fin areas; forming a first isolation material layer on the surface of the semiconductor substrate, wherein the surface of the first isolation material layer is higher than the tops of the fins; carrying out a first annealing process on the first isolation material layer; forming a groove penetrating through the first isolation material layer in the isolation region; forming a second isolation material layer in the trench; and carrying out a second annealing process on the second isolation material layer.
In some embodiments of the present application, a method of forming the number of isolation regions comprises: and etching part of the fins on the semiconductor substrate to form a plurality of fin areas and a plurality of isolation areas for isolating the fin areas.
In some embodiments of the present application, the method of forming the trench penetrating through the first isolation material layer in the isolation region includes an etching process, and a mask used in the etching process is the same as a mask used in etching the plurality of fins formed on the semiconductor substrate in the plurality of fin regions and in the plurality of isolation regions isolating the fin regions.
In some embodiments of the present application, the method of forming the first layer of isolation material is FCVD and the method of forming the second layer of isolation material in the trench includes HARP and HDPCVD.
In some embodiments of the present application, the method of forming a semiconductor structure further comprises: and removing part of the first isolation material layer and the second isolation material layer to expose the top surfaces and part of the side walls of the plurality of fins to form a first isolation layer and a second isolation layer.
In some embodiments of the present application, the method of removing portions of the first and second spacer material layers includes a chemical mechanical polishing process and an etching process.
In some embodiments of the present application, the method of forming a semiconductor structure further comprises: forming a gate oxide layer on the exposed top surface and the exposed side wall of the fin; and forming a gate layer on the surfaces of the first isolation layer, the second isolation layer and the gate oxide layer.
In some embodiments of the present application, the material of the first layer of spacer material is the same as the material of the second layer of spacer material.
Another aspect of the present application also provides a semiconductor structure comprising: the semiconductor substrate comprises fin areas and isolation areas, the isolation areas are used for isolating the adjacent fin areas, and a plurality of fins are formed on the semiconductor substrate of the fin areas; the first isolation layer is positioned on the surface of the semiconductor substrate and partial side walls of the plurality of fins; and the second isolation layer is positioned in the isolation region and penetrates through the first isolation layer.
In some embodiments of the present application, the semiconductor structure further comprises: the gate oxide layer is positioned on the top surface of the fin and part of side wall connected with the top surface; and the grid layer is positioned on the surfaces of the first isolation layer, the second isolation layer and the grid oxide layer.
In some embodiments of the present application, the material of the first isolation layer is the same as the material of the second isolation layer.
According to the semiconductor structure and the forming method thereof, on one hand, a second isolation material layer is formed in the isolation region, the stress of the second isolation material layer is low, and the stress on the outermost fins in the plurality of fins can be reduced; on the other hand, the stress of the first isolation material layer and the second isolation material layer can be further released by carrying out the annealing process twice. The fin on the outermost side of the fins can be prevented from being damaged due to unbalanced stress in a high-temperature process after the gate electrode layer is formed, the defect problem of the fins is solved, and the yield of products is improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 8 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
At present, in some methods for forming semiconductor structures, in some high temperature processes after forming a gate layer, a stress caused by the gate layer to a fin is unbalanced with a stress caused by an isolation layer to the fin, so that a part of the fin structure is damaged, functions related to the fin structure are affected, and even all the functions fail, and the yield of products is reduced.
In view of the above problems, the present application provides a semiconductor structure and a method for forming the same, in which a second isolation material layer is formed in the isolation region, and the stress of the second isolation material layer is low, so that the stress on the outermost fin among the fins can be reduced; on the other hand, the stress of the first isolation material layer and the second isolation material layer can be further released by carrying out the annealing process twice. The fin on the outermost side of the fins can be prevented from being damaged due to unbalanced stress in a high-temperature process after the gate electrode layer is formed, the defect problem of the fins is solved, and the yield of products is improved.
Fig. 1 to 8 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. A method for forming a semiconductor structure according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1 to 2, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a plurality of fin regions 101 and a plurality of isolation regions 102, the isolation regions 102 are used for isolating adjacent fin regions 101, and a plurality of fins 110 are formed on the semiconductor substrate 100 of the fin regions 101.
Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 having a plurality of fins 110 formed thereon.
In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, a method of forming the plurality of fins 110 may include: growing an epitaxial layer on the semiconductor substrate 100; forming a patterned mask layer on the epitaxial layer; the fin 110 is formed by etching the epitaxial layer and the semiconductor substrate 100 using the patterned mask layer as a mask. For example, the etching may be performed using a dry etching process, a wet etching process, or a combination thereof. In some embodiments of the present application, the mask layer may be a thin film including silicon oxide formed using a thermal oxidation process. In other embodiments of the present application, the mask layer may be a thin film comprising silicon nitride formed using a low pressure chemical vapor deposition process (LPCVD) or plasma enhanced cvd (pecvd).
Referring to fig. 2, a portion of the fins 110 on the semiconductor substrate 100 is etched to form the plurality of fin regions 101 and a plurality of isolation regions 102 isolating the fin regions 101. It should be noted that, for the sake of simplicity, only two fin regions and one isolation region are shown in the drawings, and in practice, a plurality of fin regions and a plurality of isolation regions for isolating adjacent fin regions may be formed as needed.
In some embodiments of the present application, the isolation region 102 may be a structure surrounding the fin region 101, or may be located on a specific outer side.
Referring to fig. 3, a first isolation material layer 120a is formed on the surface of the semiconductor substrate 100, and the surface of the first isolation material layer 120a is higher than the tops of the fins 110.
In some embodiments of the present application, the method of forming the first isolation material layer 120a is a flowable chemical vapor deposition process (FCVD), which can form a flowable material layer, such as flowable silicon oxide. The depth-to-width ratio of the gaps between the fins 110 is large, the gaps are difficult to fill by conventional deposition processes, and the filling capability can be improved by adopting FCVD.
In some embodiments of the present application, the material of the first isolation material layer 120a may include silicon oxide, silicon nitride, silicon oxynitride, or fluoride-doped silicate glass (FSG), or the like.
With continued reference to fig. 3, a first annealing process is performed on the first isolation material layer 120a to cure the first isolation material layer 120 a. The FCVD forms the first isolation material layer 120a with a loose structure, and an annealing process is required to bond and cure the first isolation material layer 120a and release stress.
Referring to fig. 4, a trench 130 is formed in the isolation region 102 through the first isolation material layer 120 a. The groove 130 is not connected to the fins 110, and the environment around the fins 110 may be kept unchanged, so as to avoid direct influence on the fins 110 and influence on the functions thereof.
In some embodiments of the present application, the trench 130 coincides with a projection of the isolation region 102 in a vertical direction. In other embodiments of the present application, the width of the trench 130 may be smaller than the width of the isolation region 102, i.e., the trench 130 is located in a portion of the isolation region 102.
In some embodiments of the present application, the method of forming the trench 130 penetrating through the first isolation material layer 120a in the isolation region 102 includes an etching process, and a mask used in the etching process is the same as a mask used in fig. 2 for etching a plurality of fins on the semiconductor substrate to form the plurality of fin regions and a plurality of isolation regions for isolating the fin regions. When the projection of the trench 130 and the isolation region 102 in the vertical direction coincide, the mask used in the process of fig. 2 may be directly used, so that a new mask does not need to be designed, and the cost may be saved.
In some high temperature processes after the subsequent formation of the gate layer, the first isolation material layer may still shrink, which may cause a portion of the fin structure to be damaged, and the functions related to the fin structure may be affected or even completely failed, thereby reducing the yield of the product. Therefore, in the method for forming a semiconductor structure described herein, the first isolation material layer located in the isolation region 102 is replaced by the second isolation material layer with lower stress, so as to avoid damaging the fin structure.
Referring to fig. 5, a second isolation material layer 140a is formed in the trench 130. The second spacer material layer 140a is not connected to the fins 110, and the environment around the fins 110 may be kept unchanged, so as to avoid direct influence on the fins 110 and influence on the functions thereof. The second isolation material layer 140a can reduce the volume of the first isolation material layer 120a, and reduce the stress influence of the first isolation material layer 120a on the fin structure; the interface of the second spacer material layer 140a and the first spacer material layer 140a may also function to release stress.
In some embodiments of the present application, the method of forming the second isolation material layer 140a in the trench includes a High Aspect Ratio Process (HARP) and a High Density Plasma Chemical Vapor Deposition (HDPCVD) Process. The material layer formed by the HARP and HDPCVD processes has lower stress. The fin structure is not greatly shrunk to damage in the subsequent high-temperature process. The trench 130 fills well without the need for FCVD due to its high aspect ratio.
In some embodiments of the present application, the material of the first isolation material layer 120a is the same as the material of the second isolation material layer 140a, which does not adversely affect the subsequent processes.
With continued reference to fig. 5, a second annealing process is performed on the second isolation material layer 140 a. The first and second spacer material layers 120a and 140a are further cured, releasing the stress. The first isolation material layer 120a and the second isolation material layer 140a are prevented from being greatly shrunk in the subsequent high-temperature process to damage the fin structure.
Referring to fig. 6, a portion of the first isolation material layer 120a and the second isolation material layer 140a are removed to expose the top surfaces and a portion of the sidewalls of the fins 110, thereby forming a first isolation layer 120 and a second isolation layer 140. Wherein the first isolation layer 120 may isolate the plurality of fins 110; the second isolation layer 140 may isolate adjacent fin regions 102.
In some embodiments of the present application, the method of removing a portion of the first isolation material layer 120a and the second isolation material layer 140a includes a chemical mechanical polishing process and an etching process. For example, the first and second spacer material layers 120a and 140a are polished using a chemical mechanical polishing process until top surfaces of the first and second spacer material layers 120a and 140a are coplanar with top surfaces of the fins 110; the first isolation material layer 120a and the second isolation material layer 140a are then etched to form the first isolation layer 120 and the second isolation layer 140.
Referring to fig. 7, a gate oxide layer 150 is formed on the top surface and sidewalls of the exposed fin 110.
In some embodiments of the present application, the method of forming the gate oxide layer 150 includes a thermal oxidation process.
In some embodiments of the present application, the material of the gate oxide layer 150 includes silicon oxide.
Referring to fig. 8, a gate layer 160 is formed on the surfaces of the first isolation layer 120, the second isolation layer 140, and the gate oxide layer 150.
In some embodiments of the present application, the method of forming the gate layer 160 includes a chemical vapor deposition process or a physical vapor deposition process. In some methods for forming a semiconductor structure, the gate layer fixes the top portion of the fin, and in a subsequent high temperature process, the isolation layer shrinks to cause uneven stress on the top and bottom portions of the fin, thereby damaging the fin structure. In the method for forming the semiconductor structure of the present application, the stress of the second isolation layer 140 is low, and the stress of the first isolation layer 120 and the second isolation layer 140 after the two annealing processes is fully released, so that the fin structure is not damaged in the subsequent high temperature process.
In some embodiments of the present application, the material of the gate layer 160 includes polysilicon.
According to the forming method of the semiconductor structure, on one hand, a second isolation material layer is formed in the isolation region, the stress of the second isolation material layer is low, and the stress on the outermost fins in the plurality of fins can be reduced; on the other hand, the stress of the first isolation material layer and the second isolation material layer can be further released by carrying out the annealing process twice. The fin on the outermost side of the fins can be prevented from being damaged due to unbalanced stress in a high-temperature process after the gate electrode layer is formed, the defect problem of the fins is solved, and the yield of products is improved.
Embodiments of the present application also provide a semiconductor structure, referring to fig. 8, comprising: the semiconductor device comprises a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a fin region 101 and an isolation region 102, the isolation region 102 is used for isolating the adjacent fin regions 101, and a plurality of fins 110 are formed on the semiconductor substrate 100 of the fin region 101; a first isolation layer 120 located on the surface of the semiconductor substrate 100 and on a portion of sidewalls of the plurality of fins 110; a second isolation layer 120 is disposed in the isolation region 102 and penetrates the first isolation layer 120.
In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, the isolation region 102 may be a structure surrounding the fin region 101, or may be located on a specific outer side. It should be noted that, for the sake of simplicity, only two fin regions and one isolation region are shown in the drawings, and in practice, a plurality of fin regions and a plurality of isolation regions for isolating adjacent fin regions may be formed as needed.
Referring to fig. 8, a first isolation layer 120 is formed on the surface of the semiconductor substrate 100 and on a portion of the sidewalls of the plurality of fins 110.
In some embodiments of the present application, the material of the first isolation layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, or fluoride-doped silicate glass (FSG), among others.
With continued reference to fig. 8, the second isolation layer 140 is not connected to the fins 110, and the environment around the fins 110 may remain unchanged, so as to avoid direct influence on the fins 110 and influence on the functions thereof. The second isolation layer 140 can reduce the volume of the first isolation layer 120, and reduce the stress influence of the first isolation layer 120 on the fin structure; the interface of the second release layer 140 and the first release layer 140 may also function to relieve stress.
In some embodiments of the present application, the second isolation layer 140 coincides with a projection of the isolation region 102 in a vertical direction. In other embodiments of the present application, the width of the second isolation layer 140 may be smaller than the width of the isolation region 102, that is, the second isolation layer 140 is located in a part of the isolation region 102.
In some high temperature processes after the gate layer is formed, the first isolation layer may still shrink, which may cause a portion of the fin structure to be damaged, and the functions related to the fin structure may be affected or even completely failed, thereby reducing the yield of the product. Therefore, in the semiconductor structure described herein, the first isolation layer located in the isolation region 102 is replaced by a second isolation layer with lower stress, so as to avoid damaging the fin structure.
In some embodiments of the present application, the method of forming the second isolation layer 140 includes a High Aspect Ratio Process (HARP) and a High Density Plasma Chemical Vapor Deposition (HDPCVD). The material layer formed by the HARP and HDPCVD processes has lower stress. The fin structure is not greatly shrunk to damage in the subsequent high-temperature process.
In some embodiments of the present application, the material of the first isolation layer 120 is the same as the material of the second isolation layer 140, which does not adversely affect the subsequent processes.
With continued reference to fig. 8, a gate oxide layer 150 is formed on the top surface and sidewalls of the fin 110.
In some embodiments of the present application, the material of the gate oxide layer 150 includes silicon oxide.
With continued reference to fig. 8, a gate layer 160 is formed on the surfaces of the first isolation layer 120, the second isolation layer 140, and the gate oxide layer 150.
In some semiconductor structures, the gate layer may fix the top portion of the fin, and in subsequent high temperature processes, the isolation layer may shrink, which may cause uneven stress on the top and bottom portions of the fin, thereby causing damage to the fin structure. In the method for forming the semiconductor structure of the present application, the stress of the second isolation layer 140 is low, and the stress of the first isolation layer 120 and the second isolation layer 140 after the two annealing processes is fully released, so that the fin structure is not damaged in the subsequent high temperature process.
In some embodiments of the present application, the material of the gate layer 160 includes polysilicon.
According to the semiconductor structure and the forming method thereof, on one hand, a second isolation material layer is formed in the isolation region, the stress of the second isolation material layer is low, and the stress on the outermost fins in the plurality of fins can be reduced; on the other hand, the stress of the first isolation material layer and the second isolation material layer can be further released by carrying out the annealing process twice. The fin on the outermost side of the fins can be prevented from being damaged due to unbalanced stress in a high-temperature process after the gate electrode layer is formed, the defect problem of the fins is solved, and the yield of products is improved.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (11)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of fin areas and a plurality of isolation areas, the isolation areas are used for isolating adjacent fin areas, and a plurality of fins are formed on the semiconductor substrate of the fin areas;
forming a first isolation material layer on the surface of the semiconductor substrate, wherein the surface of the first isolation material layer is higher than the tops of the fins;
carrying out a first annealing process on the first isolation material layer;
forming a groove penetrating through the first isolation material layer in the isolation region;
forming a second isolation material layer in the trench;
and carrying out a second annealing process on the second isolation material layer.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the plurality of isolation regions comprises: and etching part of the fins on the semiconductor substrate to form a plurality of fin areas and a plurality of isolation areas for isolating the fin areas.
3. The method of claim 2, wherein the forming the trench in the isolation region through the first layer of isolation material comprises etching using the same mask as a mask used to etch the plurality of fins on the semiconductor substrate to form the plurality of fin regions and the plurality of isolation regions separating the plurality of fin regions.
4. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first layer of isolation material is FCVD and the method of forming the second layer of isolation material in the trench comprises HARP and HDPCVD.
5. The method of forming a semiconductor structure of claim 1, further comprising: and removing part of the first isolation material layer and the second isolation material layer to expose the top surfaces and part of the side walls of the plurality of fins to form a first isolation layer and a second isolation layer.
6. The method for forming a semiconductor structure of claim 5, wherein the step of removing portions of the first and second spacer material layers comprises a chemical mechanical polishing process and an etching process.
7. The method of forming a semiconductor structure of claim 5, further comprising: forming a gate oxide layer on the exposed top surface and the exposed side wall of the fin; and forming a gate layer on the surfaces of the first isolation layer, the second isolation layer and the gate oxide layer.
8. The method of forming a semiconductor structure of claim 1, wherein a material of the first layer of spacer material is the same as a material of the second layer of spacer material.
9. A semiconductor structure, comprising:
the semiconductor substrate comprises fin areas and isolation areas, the isolation areas are used for isolating the adjacent fin areas, and a plurality of fins are formed on the semiconductor substrate of the fin areas;
the first isolation layer is positioned on the surface of the semiconductor substrate and partial side walls of the plurality of fins;
and the second isolation layer is positioned in the isolation region and penetrates through the first isolation layer.
10. The semiconductor structure of claim 9, further comprising: the gate oxide layer is positioned on the top surface of the fin and part of side wall connected with the top surface; and the grid layer is positioned on the surfaces of the first isolation layer, the second isolation layer and the grid oxide layer.
11. The semiconductor structure of claim 9, in which a material of the first isolation layer is the same as a material of the second isolation layer.
CN202010734868.XA 2020-07-28 2020-07-28 Semiconductor structure and forming method thereof Pending CN114005754A (en)

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Citations (4)

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US20140231919A1 (en) * 2013-02-18 2014-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fin Deformation Modulation
US20170018452A1 (en) * 2015-07-13 2017-01-19 GlobalFoundries, Inc. Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
CN107731688A (en) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN107887272A (en) * 2016-09-30 2018-04-06 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140231919A1 (en) * 2013-02-18 2014-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fin Deformation Modulation
US20170018452A1 (en) * 2015-07-13 2017-01-19 GlobalFoundries, Inc. Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
CN107731688A (en) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN107887272A (en) * 2016-09-30 2018-04-06 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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