CN114334818A

CN114334818A - Semiconductor structure and forming method thereof

Info

Publication number: CN114334818A
Application number: CN202011068749.1A
Authority: CN
Inventors: 徐娟; 任飞; 肖芳元
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-10-09
Filing date: 2020-10-09
Publication date: 2022-04-12

Abstract

The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: the semiconductor device comprises a semiconductor substrate, wherein a fin is formed on the semiconductor substrate, and a metal gate is formed on part of the top surface and the side wall of the fin; and the SDB isolation structure is positioned between the fins where the adjacent metal gates are positioned and used for isolating the fins where the adjacent metal gates are positioned. According to the semiconductor structure and the forming method thereof, the first mask layer is used as the mask to etch to form the first groove, the SDB isolation structure is formed in the first groove, the position precision of the SDB isolation structure can be improved, and residues on the side wall of the SDB isolation structure are reduced, so that the quality of the SDB isolation structure is improved, and the reliability of a device is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost continues to increase. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, and the design of three-dimensional structures such as fin field effect transistors (finfets) is becoming a focus of attention in the semiconductor field.

With the continuous miniaturization of devices, in order to manufacture fins with smaller size and more dense distribution, a new technology for manufacturing isolation structures has appeared, such as a technology for manufacturing single diffusion isolation structures (SDB isolation structures), which are generally distributed along the length direction of the fins, and one or more isolation trenches are formed in the fins by removing some regions of the fins, and after insulating materials such as silicon dioxide are filled in the trenches, the fins can be separated into a plurality of small fins, so that leakage current between two adjacent regions of the fins and between two adjacent fins can be prevented, and bridging (source-drain bridge) between a source region and a drain region formed in the fins can also be avoided. Therefore, the isolation performance of the SDB isolation structure may be affected by the manufacturing process of the SDB isolation structure and the forming structure thereof, and even the performance of the FinFET device may be affected by the defects of the surrounding fin and gate structures.

However, current manufacturing techniques for SDB isolation structures still have drawbacks. Therefore, there is a need to provide a more reliable and efficient solution.

Disclosure of Invention

The application provides a semiconductor structure and a forming method thereof, which can improve the position precision of an SDB isolation structure and reduce residues on the side wall of the SDB isolation structure, thereby improving the quality of the SDB isolation structure and improving the reliability of a device.

One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a fin is formed on the semiconductor substrate, and a dummy gate material layer is formed on the top surface and the side wall of the fin; forming a first mask layer covering a part of the dummy gate material layer on the top surface of the dummy gate material layer, wherein the first part of the first mask layer corresponds to the dummy gate layer of the semiconductor structure, and the second part of the first mask layer corresponds to the SDB isolation structure of the semiconductor structure; etching to remove the second part of the first mask layer and continuously etching the pseudo gate material layer to form a first groove in the pseudo gate material layer; etching the dummy gate material layer by taking the first part of the first mask layer as a mask until the surface of the fin is exposed, and simultaneously etching along the first groove until the bottom of the first groove is coplanar with the bottom of the fin, wherein the dummy gate material layer forms a dummy gate layer; and filling a dielectric material in the first trench to form an SDB isolation structure.

In some embodiments of the present application, the etching process removes the second portion of the first mask layer and continues to etch the dummy gate material layer, and the method for forming the first trench in the dummy gate material layer includes: forming a second mask layer on the surface of the pseudo gate material layer and the side wall and the top surface of the first mask layer; forming a photoresist layer comprising an opening on the surface of the second mask layer, wherein the opening exposes the second mask layer on the top surface of the second part of the first mask layer; etching the second mask layer, the first mask layer and the dummy gate material layer in sequence along the opening, and forming the first groove in the dummy gate material layer; and removing the photoresist layer and the second mask layer.

In some embodiments of the present application, the second mask layer, the first mask layer, and the dummy gate material layer are sequentially etched along the opening, and the method for forming the first trench in the dummy gate material layer includes: etching the second mask layer along the opening to form a second opening, wherein the first mask layer is exposed by the second opening; etching the first mask layer along the second opening until the dummy gate material layer is exposed; and continuously etching the pseudo gate material layer along the second opening, and forming the first groove in the pseudo gate material layer.

In some embodiments of the present application, a height difference between the bottom of the first trench and the top surface of the dummy gate material layer is 5 nm to 50 nm.

In some embodiments of the present application, the method for forming the SDB isolation structure by filling the first trench with a dielectric material includes: forming a first dielectric layer on the side wall of the dummy gate layer and the side wall and the bottom of the first groove; forming a source electrode and a drain electrode in the fins on two sides of the pseudo gate layer; forming a second dielectric layer with the top higher than the first mask layer and completely covering the fins and the first mask layer, wherein the second dielectric layer fills the first groove; and removing the second dielectric layer and the first mask layer which are higher than the top surface of the dummy gate layer.

In some embodiments of the present application, the method of forming a first dielectric layer on the dummy gate layer sidewalls and the first trench sidewalls and bottom comprises: forming a first dielectric layer on the top surface and the side wall of the first mask layer, the top surface of the fin and the side wall and the bottom of the first groove; and etching and removing the top surfaces of the first mask layer and the first dielectric layer on the top surfaces of the fins.

In some embodiments of the present application, the method of forming a semiconductor structure further comprises: removing the dummy gate layer to form a second trench; and forming a metal gate in the second groove.

In some embodiments of the present application, a pad oxide layer is formed between the surface of the semiconductor substrate and the bottom of the fin.

Another aspect of the present application also provides a semiconductor structure comprising: the semiconductor device comprises a semiconductor substrate, wherein a fin is formed on the semiconductor substrate, and a metal gate is formed on part of the top surface and the side wall of the fin; and the SDB isolation structure is positioned between the fins where the adjacent metal gates are positioned and used for isolating the fins where the adjacent metal gates are positioned.

In some embodiments of the present application, the semiconductor structure further comprises: and the first dielectric layer is positioned on the side wall of the metal grid electrode.

In some embodiments of the present application, the semiconductor structure further comprises: and the source electrode and the drain electrode are positioned in the fins at two sides of the metal gate.

In some embodiments of the present application, the semiconductor structure further comprises: and the top surface of the second dielectric layer is coplanar with the top surface of the metal gate.

According to the semiconductor structure and the forming method thereof, the first mask layer is used as a mask to etch to form the first groove, the SDB isolation structure is formed in the first groove, the position precision of the SDB isolation structure can be improved, and residues on the side wall of the SDB isolation structure are reduced, so that the quality of the SDB isolation structure is improved, and the reliability of a device is improved.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic perspective view of a semiconductor structure;

FIG. 2 is a schematic cross-sectional view of a semiconductor structure;

fig. 3 to 18 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

FIG. 1 is a schematic perspective view of a semiconductor structure; fig. 2 is a schematic cross-sectional view of a semiconductor structure. Fig. 2 is a cross-sectional view taken along a plane where a dashed line box 150 in fig. 1 is located.

Referring to fig. 1 and 2, a FinFET device generally includes: a semiconductor substrate 100 and a plurality of thin fins 110 (only one fin is shown for simplicity) extending vertically upward on the semiconductor substrate 100; an isolation structure 120 located on the semiconductor substrate 100 and surrounding a portion of the sidewall of the fin 110 for isolating adjacent fins 110; and a gate structure 130 located on a portion of the top surface and sidewalls of the fin 110.

With the increasing miniaturization of devices, new isolation techniques, such as SDB isolation structure fabrication techniques, have emerged in order to fabricate smaller sized, more densely distributed fins 110. Referring to fig. 1 and 2, the SDB isolation structures are generally distributed along the length direction of the fin 110, one or more isolation trenches 140 are formed in the fin 110 by removing certain regions of the fin 110, and after the isolation trenches 140 are filled with insulating materials such as silicon dioxide, the single fin 110 can be separated into a plurality of small fins, so that leakage current between two adjacent regions of the fin 110 and between two adjacent fins 110 can be prevented, and bridging between a source region and a drain region formed in the fin 110 can be avoided. Therefore, the isolation performance of the SDB isolation structure may be affected by the manufacturing process of the SDB isolation structure and the forming structure thereof, and even the performance of the FinFET device may be affected by the defects of the surrounding fin and gate structures.

In order to form the SDB isolation structure with better quality and more reliability, the application provides the semiconductor structure and the forming method thereof.

Fig. 3 to 18 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. It should be noted that fig. 3-18 are cross-sectional views for the sake of brevity, but it should be understood that fig. 3-18 are cross-sectional views taken along the length of a fin on a semiconductor structure, similar to fig. 2 with respect to fig. 1. A method for forming a semiconductor structure according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

An embodiment of the present application provides a method for forming a semiconductor structure, including: referring to fig. 3, a semiconductor substrate 200 is provided, a fin 220 is formed on the semiconductor substrate 200, and a dummy gate material layer 230a is formed on the top surface and the sidewall of the fin 220; referring to fig. 4, a first mask layer 240 is formed on the top surface of the dummy gate material layer 230a to cover a portion of the dummy gate material layer 230a, a first portion 241 of the first mask layer 240 corresponds to the dummy gate layer of the semiconductor structure, and a second portion 242 of the first mask layer 240 corresponds to the SDB isolation structure of the semiconductor structure; referring to fig. 5 to 10, the second portion 242 of the first mask layer 240 is removed by etching and the dummy gate material layer 230a is continuously etched, so as to form a first trench 250 in the dummy gate material layer 230 a; referring to fig. 11, the dummy gate material layer 230a is etched using the first portion 241 of the first mask layer 240 as a mask until the surface of the fin 220 is exposed, and simultaneously etched along the first trench 250 to the bottom of the first trench 250 and coplanar with the bottom of the fin 220, the dummy gate material layer 230a forms a dummy gate layer 230, and referring to fig. 12 to 16, the first trench 250 is filled with a dielectric material to form an SDB isolation structure 280.

In the method for forming the semiconductor structure according to the embodiment of the present application, the first mask layer 240 is used as a mask to etch and form the first trench 250, and the SDB isolation structure 280 is formed in the first trench 250, so that the position accuracy of the SDB isolation structure 280 can be improved, and residues on the side wall of the SDB isolation structure 280 are reduced, thereby improving the quality of the SDB isolation structure 280 and improving the reliability of a device.

Referring to fig. 3, a semiconductor substrate 200 is provided, a fin 220 is formed on the semiconductor substrate 200, and a dummy gate material layer 230a is formed on the top surface and the sidewall of the fin 220.

In some embodiments of the present application, a pad oxide layer 210 is formed between the surface of the semiconductor substrate 200 and the bottom of the fin 220. The pad oxide layer 210 may be used as an etching stop layer when the first trench is subsequently etched until the bottom of the first trench is coplanar with the bottom of the fin, so as to prevent the semiconductor substrate from being damaged by excessive etching.

In some embodiments of the present application, the material of the pad oxide layer 210 includes silicon oxide, etc.

In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

In some embodiments of the present application, a method of forming the fin 220 may include: forming a fin material layer on the pad oxide layer 210; forming a patterned mask layer on the fin material layer; the fin material layer is etched using the patterned mask layer as a mask to form the fin 220. For example, the etching may be performed using a dry etching process, a wet etching process, or a combination thereof. In some embodiments of the present application, the mask layer may be a thin film including silicon oxide formed using a thermal oxidation process. In other embodiments of the present application, the mask layer may be a thin film comprising silicon nitride formed using a low pressure chemical vapor deposition process (LPCVD) or plasma enhanced cvd (pecvd).

In some embodiments of the present application, the material of the dummy gate material layer 230a includes polysilicon. The method of forming the dummy gate material layer 230a includes a chemical vapor deposition process.

Referring to fig. 4, a first mask layer 240 is formed on the top surface of the dummy gate material layer 230a to cover a portion of the dummy gate material layer 230a, a first portion 241 of the first mask layer 240 corresponds to the dummy gate layer of the semiconductor structure, and a second portion 242 of the first mask layer 240 corresponds to the SDB isolation structure of the semiconductor structure.

In subsequent processes, an etching process is performed to form a dummy gate layer and an SDB isolation structure by using the first portion 241 and the second portion 242 as masks, respectively. The correspondence means that projections of the first portion 241 and the second portion 242 in a vertical direction coincide with projections of the dummy gate layer and the SDB isolation structure in a vertical direction, respectively.

In some embodiments of the present application, the material of the first mask layer 240 may be a material forming a gate driver.

Referring to fig. 5 to 10, the second portion 242 of the first mask layer 230 is removed by etching and the dummy gate material layer 230a is continuously etched, so that a first trench 250 is formed in the dummy gate material layer 230 a.

Referring to fig. 5, a second mask layer 251 is formed on the surface of the dummy gate material layer 230a and the sidewalls and top surface of the first mask layer 240. The second mask layer 251 can increase a process window for etching the first trench, improve the accuracy of etching the first trench, and implement the specific process of the above-described function as will be described in detail below.

In some embodiments of the present application, the material selection of the second mask layer 251 may satisfy that the etching selectivity ratio of the second mask layer 251 is relatively different from that of the first mask layer 240, and the first mask layer 240 may serve as an etching stop layer when the second mask layer 251 is etched.

Referring to fig. 6, a photoresist layer 252 including an opening 253 is formed on the surface of the second mask layer 251, and the opening 253 exposes the second mask layer 251 on the top surface of the second portion 242 of the first mask layer 240.

It should be noted that the drawings in this application are schematic only and do not represent true dimensional proportions of the semiconductor structures. In practical structures, the width (dimension in the horizontal direction) of the second portion 242 is very small, and it is difficult to achieve such a small dimension with the minimum width of the opening 253 formed by exposure in some current photolithography processes, and it is difficult to directly etch the second portion 242 through the opening 253. Therefore, a layer of the second mask layer 251 may be added, the second mask layer 251 is etched to form a second opening 254 having a width smaller than that of the opening 253, and then the second portion 242 is etched through the second opening 254.

In other embodiments of the present application, if the precision of the photolithography process can achieve that the minimum width of the opening 253 formed by exposure can reach the width of the second portion 242, the second mask layer 251 can be omitted, and the second portion 242 can be directly etched through the opening 253.

Referring to fig. 7 to 9, the second mask layer 251, the first mask layer 240, and the dummy gate material layer 230a are sequentially etched along the opening 253, and the first trench 250 is formed in the dummy gate material layer 230 a.

Referring to fig. 7, the second mask layer 251 is etched along the opening 253 to form a second opening 254, and the second opening 254 exposes the second portion 242 of the first mask layer 240. Because the etching selection ratio of the second mask layer 251 is different from that of the first mask layer 240, the first mask layer 240 can be used as an etching stop layer, so that the etching stops on the surface of the first mask layer 240.

In some embodiments of the present application, the method for etching the second mask layer 251 includes dry etching. The dry etch may form a second opening 254 having a width less than the opening 253. This further etches the second portion 242 along the second opening 254 more precisely than directly etching the second portion 242 along the opening 253, i.e., increasing the window of the etching process.

Referring to fig. 8, the second portion 242 of the first mask layer 240 is etched along the second opening 254 to expose the dummy gate material layer 230 a. The material of the first mask layer 240 is different from that of the second mask layer 251, and therefore, the etching process needs to be replaced with a suitable etching gas or etching solution. The second portion 242 is used as a tool for positioning the first trench 250, so that the position accuracy of forming the SDB isolation structure is improved.

In some embodiments of the present application, the method for etching the first mask layer 240 includes dry etching or wet etching.

Referring to fig. 9, the etching of the dummy gate material layer 230a is continued along the second opening 254, and the first trench 250 is formed in the dummy gate material layer 230 a. The material of the first mask layer 240 is different from that of the dummy gate material layer 230a, and therefore, the etching process needs to be replaced with an appropriate etching gas or etching solution.

In some embodiments of the present application, the method for etching the dummy gate material layer 230a includes dry etching or wet etching.

It should be noted that, for the sake of brevity, details of each etching are not specifically listed in the embodiments of the present application, and in an actual process, an appropriate etching gas or an appropriate etching solution may be respectively selected according to the materials of the first mask layer 240, the second mask layer 251, and the dummy gate material layer 230 a.

Referring to fig. 10, the photoresist layer 252 and the second mask layer 251 are removed.

In some embodiments of the present application, the photoresist layer 252 is removed by, for example, an ashing process.

In some embodiments of the present application, a method for removing the second mask layer 251 is, for example, an etching process.

In some embodiments of the present application, a height difference between the bottom of the first trench 250 and the top surface of the dummy gate material layer 230a is 5 nm to 50 nm. The height difference is the depth of the first trench 250, and in the subsequent process, the first trench 250 is etched to the bottom of the fin 220 while the dummy gate material layer 230a is etched to form a dummy gate layer, so that, in order to save process materials and improve efficiency as much as possible, it is preferable that the first trench 250 is also etched to the bottom of the fin 220 substantially right when the dummy gate layer is formed. Thus, the optimal depth of the first trench 250 at this time can be calculated according to the etching time of the fin 220 and the etching time of the dummy gate layer 230 a.

In some embodiments of the present application, the etching selectivity of the dummy gate material layer 230a is close to that of the fin 220, so the etching rate of the dummy gate material layer 230a is close to that of the fin 220, and the optimal depth of the first trench 250 at this time is the height of the fin 220. The bottom of the first trench 250 is located at a distance from the bottom of the fin 220 that is exactly equal to the height of the dummy gate material layer 230 a. Such that the time for subsequent etching of the dummy gate material layer 230a is substantially equal to the time for etching the first trench 250 to the bottom of the fin 220.

Referring to fig. 11, the dummy gate material layer 230a is etched using the first portion 241 of the first mask layer 240 as a mask until the surface of the fin 220 is exposed, and simultaneously etched along the first trench 250 until the bottom of the first trench 250 is coplanar with the bottom of the fin 220, so that the dummy gate material layer 230a forms a dummy gate layer 230.

In some embodiments of the present application, the etch selectivity of the dummy gate material layer 230a is close to the etch selectivity of the fin 220, so that the dummy gate material layer 230a and the fin 220 can be etched simultaneously in the same etching process.

In some embodiments of the present application, the pad oxide layer 210 may serve as an etch stop layer to prevent excessive etching from damaging the semiconductor substrate 200.

In some embodiments of the present application, the method for etching the dummy gate material layer 230a includes wet etching or dry etching.

Referring to fig. 12 to 16, a dielectric material is filled in the first trench 250 to form an SDB isolation structure 280.

Referring to fig. 12 to 13, a first dielectric layer 260 is formed on sidewalls of the dummy gate layer 230 and sidewalls and a bottom of the first trench 250. The first dielectric layer 260 located on the sidewall of the dummy gate layer 230 may serve as a sidewall spacer of the dummy gate layer 230; the first dielectric layer 260 on the sidewalls and bottom of the first trench 250 may be used as a part of the dielectric material of the SDB isolation structure.

Referring to fig. 12, a first dielectric layer 260 is formed on the top surface and sidewalls of the first portion 241 of the first mask layer 240, the top surface of the fin 220, and the sidewalls and bottom of the first trench 250.

In some embodiments of the present application, the method of forming the first dielectric layer 260 includes a chemical vapor deposition process.

In some embodiments of the present application, the material of the first dielectric layer 260 includes silicon nitride, etc.

Referring to fig. 13, the top surface of the first portion 241 of the first mask layer 240 and the first dielectric layer 260 on the top surface of the fin 220 are etched away, and only the first dielectric layer 260 on the sidewalls of the dummy gate layer 230 and the sidewalls and the bottom of the first trench 250 remains.

In some embodiments of the present application, the method for etching the first dielectric layer 260 includes wet etching, dry etching, or the like.

Referring to fig. 14, a source 270 and a drain 271 are formed in the fin 220 on both sides of the dummy gate layer 230.

In some embodiments of the present application, the source 270 and the drain 271 are formed by, for example: etching grooves in the fins 220 on two sides of the dummy gate layer 230; the source electrode 270 and the drain electrode 271 are formed in the trench by epitaxial growth.

Referring to fig. 15, a second dielectric layer 261 is formed, the top of which is higher than the first masking layer 240 and completely covers the fins 220 and the first masking layer 240, and the first trench 250 is filled with the second dielectric layer 261. Wherein the second dielectric layer 261 in the first trench 250 is used as a part of the SDB isolation structure.

In some embodiments of the present application, the method of forming the second dielectric layer 261 comprises a chemical vapor deposition process.

In some embodiments of the present application, the material of the second dielectric layer 261 includes silicon oxide, etc.

Referring to fig. 16, the second dielectric layer 261 and the first mask layer 240 above the top surface of the dummy gate layer 230 are removed. The first dielectric layer 260 located on the sidewall and the bottom of the first trench 250 and the second dielectric layer 261 located in the first trench 250 together form the SDB isolation structure 280.

In some embodiments of the present application, the method for removing the second dielectric layer 261 and the first mask layer 240 above the top surface of the dummy gate layer 230 includes a chemical mechanical polishing process, a wet etching process, and the like.

Referring to fig. 17, the dummy gate layer 230 is removed to form a second trench 291; a metal gate 290 is formed in the second trench 291 with reference to fig. 18.

In some embodiments of the present application, the method for removing the dummy gate layer 230 includes wet etching or dry etching.

In some embodiments of the present application, the method of forming the metal gate 290 includes a chemical vapor deposition process or a physical vapor deposition process.

In some embodiments of the present application, the material of the metal gate 290 includes aluminum or the like.

According to the method for forming the semiconductor structure, the first mask layer is used as a mask to etch to form the first groove, the SDB isolation structure is formed in the first groove, the position precision of the SDB isolation structure can be improved, and residues on the side wall of the SDB isolation structure are reduced, so that the quality of the SDB isolation structure is improved, and the reliability of a device is improved.

Embodiments of the present application also provide a semiconductor structure, referring to fig. 18, comprising: the semiconductor device comprises a semiconductor substrate 200, wherein a fin 220 is formed on the semiconductor substrate 200, and a metal gate 290 is formed on part of the top surface and the side wall of the fin 220; SDB isolation structures 280 are located between the fins 220 where adjacent metal gates 290 are located to isolate the fins 220 where adjacent metal gates 290 are located.

Referring to fig. 18, in some embodiments of the present application, a pad oxide layer 210 is formed between the surface of the semiconductor substrate 200 and the bottom of the fin 220.

With continued reference to fig. 18, the SDB isolation structure 280 is formed by a portion of the first dielectric layer 260 and a portion of the second dielectric layer 261. The SDB isolation structures 280 serve to isolate adjacent fins 220.

With continued reference to fig. 18, a first dielectric layer 260 is also formed on the sidewalls of the metal gate 290. The first dielectric layer 260 located on the sidewall of the metal gate 290 may be used as a sidewall spacer of the metal gate 290.

With continued reference to fig. 18, the semiconductor structure further includes a source 270 and a drain 271 in the fin 220 on either side of the metal gate 290.

With continued reference to fig. 18, the semiconductor structure further includes a second dielectric layer 261 completely covering the fins 220, wherein a top surface of the second dielectric layer 261 is coplanar with a top surface of the metal gate 290.

The semiconductor structure of the embodiment of the application takes the first mask layer as a mask to etch to form the first groove, the SDB isolation structure is formed in the first groove, the position precision of the SDB isolation structure can be improved, and residues on the side wall of the SDB isolation structure are reduced, so that the quality of the SDB isolation structure is improved, and the reliability of a device is improved.

In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein a fin is formed on the semiconductor substrate, and a dummy gate material layer is formed on the top surface and the side wall of the fin;

forming a first mask layer covering a part of the dummy gate material layer on the top surface of the dummy gate material layer, wherein the first part of the first mask layer corresponds to the dummy gate layer of the semiconductor structure, and the second part of the first mask layer corresponds to the SDB isolation structure of the semiconductor structure;

etching to remove the second part of the first mask layer and continuously etching the pseudo gate material layer to form a first groove in the pseudo gate material layer;

etching the dummy gate material layer by taking the first part of the first mask layer as a mask until the surface of the fin is exposed, and simultaneously etching along the first groove until the bottom of the first groove is coplanar with the bottom of the fin, wherein the dummy gate material layer forms a dummy gate layer;

and filling a dielectric material in the first trench to form an SDB isolation structure.

2. The method of forming a semiconductor structure of claim 1, wherein etching removes the second portion of the first mask layer and continues to etch the dummy gate material layer, the method of forming the first trench in the dummy gate material layer comprising:

forming a second mask layer on the surface of the pseudo gate material layer and the side wall and the top surface of the first mask layer;

forming a photoresist layer comprising an opening on the surface of the second mask layer, wherein the opening exposes the second mask layer on the top surface of the second part of the first mask layer;

etching the second mask layer, the first mask layer and the dummy gate material layer in sequence along the opening, and forming the first groove in the dummy gate material layer;

and removing the photoresist layer and the second mask layer.

3. The method for forming a semiconductor structure according to claim 2, wherein the second mask layer, the first mask layer, and the dummy gate material layer are sequentially etched along the opening, and the method for forming the first trench in the dummy gate material layer includes:

etching the second mask layer along the opening to form a second opening, wherein the first mask layer is exposed by the second opening;

etching the first mask layer along the second opening until the dummy gate material layer is exposed;

and continuously etching the pseudo gate material layer along the second opening, and forming the first groove in the pseudo gate material layer.

4. The method of claim 2, wherein a height difference between a bottom of the first trench and a top surface of the dummy gate material layer is between 5 nm and 50 nm.

5. The method for forming a semiconductor structure of claim 1, wherein the step of filling the first trench with a dielectric material to form an SDB isolation structure comprises:

forming a first dielectric layer on the side wall of the dummy gate layer and the side wall and the bottom of the first groove;

forming a source electrode and a drain electrode in the fins on two sides of the pseudo gate layer;

forming a second dielectric layer with the top higher than the first mask layer and completely covering the fins and the first mask layer, wherein the second dielectric layer fills the first groove;

and removing the second dielectric layer and the first mask layer which are higher than the top surface of the dummy gate layer.

6. The method of forming a semiconductor structure of claim 5, wherein forming a first dielectric layer on the dummy gate layer sidewalls and the first trench sidewalls and bottom comprises:

forming a first dielectric layer on the top surface and the side wall of the first mask layer, the top surface of the fin and the side wall and the bottom of the first groove;

and etching and removing the top surfaces of the first mask layer and the first dielectric layer on the top surfaces of the fins.

7. The method of forming a semiconductor structure of claim 1, further comprising: removing the dummy gate layer to form a second trench; and forming a metal gate in the second groove.

8. The method of claim 1, wherein a pad oxide layer is formed between the surface of the semiconductor substrate and the bottom of the fin.

9. A semiconductor structure, comprising:

the semiconductor device comprises a semiconductor substrate, wherein a fin is formed on the semiconductor substrate, and a metal gate is formed on part of the top surface and the side wall of the fin;

and the SDB isolation structure is positioned between the fins where the adjacent metal gates are positioned and used for isolating the fins where the adjacent metal gates are positioned.

10. The semiconductor structure of claim 9, wherein a pad oxide layer is formed between the surface of the semiconductor substrate and the bottom of the fin.

11. The semiconductor structure of claim 9, further comprising: and the first dielectric layer is positioned on the side wall of the metal grid electrode.

12. The semiconductor structure of claim 9, further comprising: and the source electrode and the drain electrode are positioned in the fins at two sides of the metal gate.

13. The semiconductor structure of claim 9, further comprising: and the top surface of the second dielectric layer is coplanar with the top surface of the metal gate.