CN114860057B - Device and method for optimizing power supply unit of server - Google Patents
Device and method for optimizing power supply unit of server Download PDFInfo
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- CN114860057B CN114860057B CN202210607694.XA CN202210607694A CN114860057B CN 114860057 B CN114860057 B CN 114860057B CN 202210607694 A CN202210607694 A CN 202210607694A CN 114860057 B CN114860057 B CN 114860057B
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- 230000002159 abnormal effect Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
- G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention belongs to the technical field of servers, and particularly provides a device and a method for optimizing a power supply unit of a server, wherein the device comprises the following steps: the input end of the CPLD is connected with the key signal output end and the in-place signal output end of the hardware of the power supply unit; the output end of the CPLD is connected with a rear-stage startup control circuit, and the rear-stage startup control circuit derives the voltage required by startup operation according to key signals forwarded by the CPLD from the hardware of the power supply unit. The invention can ensure that the problem that the server cannot be started can be effectively avoided, improves the stability of products, and improves the customer satisfaction and the competitiveness of the products.
Description
Technical Field
The invention belongs to the technical field of servers, and particularly relates to a device and a method for optimizing a power supply unit of a server.
Background
With the advent of big data, cloud computing and artificial intelligence, the internet business volume has been increased drastically, and the computing amount and computing frequency have been increased; in the server system, the service calculation amount is increased, so that the carrying pressure of the server is increased, and the higher requirement on the stability of the server is provided under the condition; if the unstable condition occurs in the running process of the server to cause abnormal shutdown, the service interruption of the client and the data loss are the results caused; if the machine cannot be started again after being shut down, the server cannot be reused, and losses are caused to clients.
The server system contains more key components and elements, and the normal operation of the server needs close coordination among the key elements. PSU (power supply unit: power Supply Unit) is a source of power supply for the server, and signals output by psu_pwrok directly affect the start-up of the server. After the key signals of PSU are output, some column voltages required for the start-up operation of the following servers are derived, so that the stability of PSU signals is important. More devices are connected with the PSU on the main board, some devices have leakage current due to the difference between the processes of the devices, when the leakage current is larger, the key signals of the PSU can be influenced, especially when the PSU is out of place, the key signals are more obvious, the startup time sequence behind the server is further influenced, and the server cannot be started up to run.
Disclosure of Invention
The invention provides a device and a method for optimizing a server power supply unit to solve the technical problems.
The invention provides a server power supply unit optimizing device, comprising:
the input end of the CPLD is connected with the key signal output end and the in-place signal output end of the hardware of the power supply unit; the output end of the CPLD is connected with a rear-stage startup control circuit, and the rear-stage startup control circuit derives the voltage required by startup operation according to key signals forwarded by the CPLD from the hardware of the power supply unit.
Further, the post-stage startup control circuit includes:
the input end of the logic AND gate is connected with the output end of the CPLD, and a pull-down resistor is arranged on a connecting branch of the input end of the logic AND gate and the output end of the CPLD; the output end of the logic AND gate is respectively connected with the P12V conversion cable and the time sequence control chip.
Further, the resistance value of the pull-down resistor is 200KΩ.
Further, a first input end of the CPLD is connected with a key signal output end and an in-place signal output end of the first power supply unit hardware; the second input end of the CPLD is connected with the key signal output end and the in-place signal output end of the second power supply unit hardware; the first output end of the CPLD is connected with the first input end of the logic AND gate, and a first pull-down resistor is arranged on a first connection branch between the first input end of the logic AND gate and the first output end of the CPLD; the second output end of the CPLD is connected with the second input end of the logic AND gate, and a second pull-down resistor is arranged on a second connecting branch between the second input end of the logic AND gate and the second output end of the CPLD; the first output end of the CPLD forwards the signal of the first input end, and the second output end of the CPLD forwards the signal of the second input end.
Further, the resistance values of the first pull-down resistor and the second pull-down resistor are 200KΩ.
The invention also provides a server power supply unit optimization method, which comprises the following steps:
after the CPLD receives the key signals of the power supply unit hardware, judging whether the on-site signals of the power supply unit hardware are received at the same time or not:
if yes, forwarding the key signal to a rear-stage startup control line;
if not, the key signal is not forwarded.
Further, forwarding the key signal to a post-stage power-on control line includes:
and filtering the key signals and sending the processed key signals to a post-stage startup control line.
Further, not forwarding the critical signal includes:
the key signal is forcibly assigned to a low level.
The optimization device and the optimization method for the power supply unit of the server have the beneficial effects that the optimization processing is carried out on the signals by adopting a mode of combining hardware design and CPLD logic design, so that the situation that the server cannot be started up due to abnormal high caused by leakage current of external equipment when PSU is out of place is prevented, meanwhile, the double guarantee of the signals is realized by optimizing the existing hardware circuit, the problem that the server cannot be started up is effectively avoided, the stability of products is improved, and the customer satisfaction and the competitiveness of the products are improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a server power supply unit optimizing apparatus according to an embodiment of the present application.
Fig. 2 is an exemplary flowchart of a server power supply unit optimization method according to one embodiment of the present application.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art in a specific case.
The invention will be described in detail below with reference to the drawings in connection with embodiments.
The hardware circuit of the existing PSU (power supply unit) is that the hardware of different power supply units is connected with the input end of a logic AND gate through a pull-down resistor, and the output end of the logic AND gate is respectively connected with a P12V conversion circuit and a CPLD time sequence control chip. The pull-down resistors have resistance values of 1MΩ. When the leakage current is large, the structure can influence key signals of the PSU, particularly when the PSU is out of position, the PSU is more remarkable, and further the power-on time sequence behind the server is influenced, so that the server cannot be started and operated.
Referring to fig. 1, in this embodiment, a server power supply unit optimizing device is provided, including a CPLD, where an input end of the CPLD is connected to a key signal output end and an in-place signal output end of power supply unit hardware; the output end of the CPLD is connected with a rear-stage startup control circuit, and the rear-stage startup control circuit derives the voltage required by startup operation according to key signals forwarded by the CPLD from the hardware of the power supply unit. The post-stage startup control circuit comprises: the input end of the logic AND gate is connected with the output end of the CPLD, and a pull-down resistor is arranged on a connecting branch of the input end of the logic AND gate and the output end of the CPLD; the output end of the logic AND gate is respectively connected with the P12V conversion cable and the time sequence control chip. The pull-down resistor has a resistance of 200kΩ.
In the following, two power supply unit hardware is taken as an example for explanation, and a first input end of the CPLD is connected with a key signal output end and an in-place signal output end of the first power supply unit hardware (psu_1); the second input end of the CPLD is connected with the key signal output end and the bit signal output end of the second power supply unit hardware (PSU_2); the first output end of the CPLD is connected with the first input end of the logic AND gate, and a first pull-down resistor is arranged on a first connection branch between the first input end of the logic AND gate and the first output end of the CPLD; the second output end of the CPLD is connected with the second input end of the logic AND gate, and a second pull-down resistor is arranged on a second connecting branch between the second input end of the logic AND gate and the second output end of the CPLD; the first output end of the CPLD forwards the signal of the first input end, and the second output end of the CPLD forwards the signal of the second input end. The resistance values of the first pull-down resistor and the second pull-down resistor are 200KΩ.
According to the server power supply unit optimizing device provided by the embodiment, whether the state of the PSU key signal is normal is confirmed by adding judgment on whether the PSU is in-place or not, and based on the judgment, the optimization processing is performed in the CPLD, and meanwhile, the hardware pull-down resistor design is optimized, so that the PSU key signal is not influenced. Specifically, the present invention relates to a method for manufacturing a semiconductor device. Firstly, adding two key designs on a hardware circuit, namely, modifying a pull-down resistance value to 200KΩ for a key signal (PSU_PWROK) of PSU; secondly, a PSU bit signal (PSU_PRESENT) is accessed into the CPLD, and a PSU_PWROK signal is also accessed into the CPLD, and is input to a later-stage line after CPLD processing. Then, when the psu_pwrok signal is inputted to a high level, it is first determined whether the PSU is in place, if so, it is considered normal, the CPLD performs a filtering operation on the key signal psu_pwrok to ensure its stability and then outputs it to the latter stage line, if not in place, it is considered as an abnormal signal, and the CPLD forces the signal to be assigned to a low level and then outputs it to the latter stage line. Therefore, when the PSU is out of place but the PSU key signal PSU_PWROK is abnormally high due to external factors, the design optimization can be adopted, the overcurrent protection caused by abnormal starting of a later-stage line is avoided, the problem that a server cannot be started is effectively prevented, the stability of a product is improved, and further the customer satisfaction degree and the competitiveness of the product are improved. In addition, the pull-down resistor of the PSU key signal PSU_PWROK is modified from 1MΩ to 200KΩ, so that the pull-down strength is enhanced, and the signal is doubly ensured.
Referring to fig. 2, the present embodiment provides a method for optimizing a power supply unit of a server, including the following steps:
when the CPLD receives that the key signal of a certain power supply unit hardware is input to be high level, firstly judging whether the input power supply unit hardware in-place signal is logic 1, if the input power supply unit hardware in-place signal is logic 1, indicating that PSU is in place, the CPLD only plays a role in filtering optimization, if the input power supply unit hardware in-place signal is logic 0, indicating that the input power supply unit hardware is not in place, the CPLD can force the key signal of the power supply unit hardware to be assigned to be low level, and preventing false triggering.
Although the present invention has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and it is intended that all such modifications and substitutions be within the scope of the present invention/be within the scope of the present invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A server power supply unit optimizing apparatus, comprising:
the input end of the CPLD is connected with the key signal output end and the in-place signal output end of the hardware of the power supply unit; the output end of the CPLD is connected with a rear-stage starting-up control circuit, and the rear-stage starting-up control circuit derives the voltage required by starting-up operation according to key signals forwarded by the CPLD from the hardware of the power supply unit;
the rear-stage startup control circuit comprises:
the input end of the logic AND gate is connected with the output end of the CPLD, and a pull-down resistor is arranged on a connecting branch of the input end of the logic AND gate and the output end of the CPLD; the output end of the logic AND gate is respectively connected with the P12V conversion cable and the time sequence control chip;
after the CPLD receives the key signals of the power supply unit hardware, judging whether the on-site signals of the power supply unit hardware are received at the same time or not:
if yes, forwarding the key signal to a later-stage startup control line, wherein the key signal is a PSU_PWROK signal;
if not, not forwarding the key signal;
forwarding the key signal to a post-stage startup control line, including:
filtering the key signals, and sending the processed key signals to a post-stage startup control circuit;
not forwarding the critical signal, including:
the key signal is forcibly assigned to a low level.
2. The apparatus of claim 1, wherein the pull-down resistor has a resistance of 200kΩ.
3. The device of claim 1, wherein a first input of the CPLD is connected to a critical signal output and an on-bit signal output of the first power supply unit hardware; the second input end of the CPLD is connected with the key signal output end and the in-place signal output end of the second power supply unit hardware; the first output end of the CPLD is connected with the first input end of the logic AND gate, and a first pull-down resistor is arranged on a first connection branch between the first input end of the logic AND gate and the first output end of the CPLD; the second output end of the CPLD is connected with the second input end of the logic AND gate, and a second pull-down resistor is arranged on a second connecting branch between the second input end of the logic AND gate and the second output end of the CPLD; the first output end of the CPLD forwards the signal of the first input end, and the second output end of the CPLD forwards the signal of the second input end.
4. The apparatus of claim 3, wherein the first pull-down resistor and the second pull-down resistor each have a resistance of 200kΩ.
5. A server power supply unit optimization method performed by the apparatus of any one of claims 1-4, the method comprising:
after the CPLD receives the key signals of the power supply unit hardware, judging whether the on-site signals of the power supply unit hardware are received at the same time or not:
if yes, forwarding the key signal to a rear-stage startup control line;
if not, not forwarding the key signal;
forwarding the key signal to a post-stage startup control line, including:
filtering the key signals, and sending the processed key signals to a post-stage startup control circuit;
not forwarding the critical signal, including:
the key signal is forcibly assigned to a low level.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016061771A1 (en) * | 2014-10-22 | 2016-04-28 | 华为技术有限公司 | Power-on circuit and electronic device |
| CN106201758A (en) * | 2016-07-15 | 2016-12-07 | 浪潮电子信息产业股份有限公司 | The method and device that a kind of server node hard disk powers on |
| CN108549279A (en) * | 2018-04-02 | 2018-09-18 | 郑州云海信息技术有限公司 | A kind of method and apparatus for preventing server master board core voltage from leaking electricity |
| WO2022007414A1 (en) * | 2020-07-10 | 2022-01-13 | 苏州浪潮智能科技有限公司 | Server fan control device and method based on control chip |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016061771A1 (en) * | 2014-10-22 | 2016-04-28 | 华为技术有限公司 | Power-on circuit and electronic device |
| CN106201758A (en) * | 2016-07-15 | 2016-12-07 | 浪潮电子信息产业股份有限公司 | The method and device that a kind of server node hard disk powers on |
| CN108549279A (en) * | 2018-04-02 | 2018-09-18 | 郑州云海信息技术有限公司 | A kind of method and apparatus for preventing server master board core voltage from leaking electricity |
| WO2022007414A1 (en) * | 2020-07-10 | 2022-01-13 | 苏州浪潮智能科技有限公司 | Server fan control device and method based on control chip |
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