CN114860057A - Server power supply unit optimization device and method - Google Patents
Server power supply unit optimization device and method Download PDFInfo
- Publication number
- CN114860057A CN114860057A CN202210607694.XA CN202210607694A CN114860057A CN 114860057 A CN114860057 A CN 114860057A CN 202210607694 A CN202210607694 A CN 202210607694A CN 114860057 A CN114860057 A CN 114860057A
- Authority
- CN
- China
- Prior art keywords
- cpld
- output end
- power supply
- supply unit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000005457 optimization Methods 0.000 title claims abstract description 15
- 238000001914 filtration Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
- G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The invention belongs to the technical field of servers, and particularly provides a server power supply unit optimization device and a server power supply unit optimization method, wherein the device comprises the following steps: the input end of the CPLD is connected with the key signal output end and the on-site signal output end of the power supply unit hardware; the output end of the CPLD is connected with a rear-stage startup control circuit, and the rear-stage startup control circuit deduces the voltage required by startup operation according to the key signal of the CPLD forwarding self-powered unit hardware. The invention can effectively avoid the problem that the server cannot be started, improves the stability of the product, and improves the customer satisfaction and the competitiveness of the product.
Description
Technical Field
The invention belongs to the technical field of servers, and particularly relates to a server power supply unit optimization device and method.
Background
With the advent of big data, cloud computing and artificial intelligence era, the internet business volume is drastically increased, and the computing volume and the computing frequency are increased; in a server system, the increase of the traffic calculation amount causes the carrying pressure of the server to become large, and in this case, higher requirements are put on the stability of the server; if the server is abnormally shut down due to unstable conditions in the running process, the service interruption of the client and data loss are caused; if the machine cannot be restarted after being shut down, the server cannot be used again, and loss is caused to the client.
The server system comprises more key components and parts, and the normal operation of the server requires close cooperation among the key components. The PSU (Power Supply Unit) is the source of the server Power Supply, and the output signal such as PSU _ PWROK directly affects the startup of the server. After the critical signal of the PSU is output, a series of voltages required for the subsequent server to start up and operate can be derived, so that the stability of the PSU signal is very important. The main board is provided with more devices connected with the PSU, some devices have leakage current due to the difference between the manufacturing processes of the devices, when the leakage current is larger, the leakage current can affect the key signals of the PSU, especially when the PSU is not in place, the leakage current is more remarkable, and then the starting time sequence behind the server is affected, so that the server cannot be started and operated.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides an apparatus and a method for optimizing a server power supply unit, so as to solve the above-mentioned technical problems.
The invention provides a server power supply unit optimizing device, comprising:
the input end of the CPLD is connected with the key signal output end and the on-site signal output end of the power supply unit hardware; the output end of the CPLD is connected with a rear-stage startup control circuit, and the rear-stage startup control circuit deduces the voltage required by startup operation according to the key signal of the CPLD forwarding self-powered unit hardware.
Further, the post-stage boot control circuit includes:
the input end of the logic AND gate is connected with the output end of the CPLD, and a pull-down resistor is arranged on a connecting branch of the input end of the logic AND gate and the output end of the CPLD; the output end of the logic AND gate is respectively connected with the P12V switching cable and the timing control chip.
Further, the resistance value of the pull-down resistor is 200K Ω.
Furthermore, a first input end of the CPLD is connected with a key signal output end and an in-place signal output end of the first power supply unit hardware; the second input end of the CPLD is connected with the key signal output end and the in-place signal output end of the second power supply unit hardware; the first output end of the CPLD is connected with the first input end of the logic AND gate, and a first pull-down resistor is arranged on a first connecting branch between the first input end of the logic AND gate and the first output end of the CPLD; the second output end of the CPLD is connected with the second input end of the logic AND gate, and a second pull-down resistor is arranged on a second connecting branch between the second input end of the logic AND gate and the second output end of the CPLD; the first output end of the CPLD forwards the signal of the first input end, and the second output end of the CPLD forwards the signal of the second input end.
Further, the resistance values of the first pull-down resistor and the second pull-down resistor are both 200K Ω.
The invention also provides a server power supply unit optimization method, which comprises the following steps:
after receiving a key signal of power supply unit hardware, the CPLD judges whether an in-place signal of the power supply unit hardware is received at the same time:
if yes, forwarding the key signal to a rear-stage startup control circuit;
and if not, not forwarding the key signal.
Further, forwarding the key signal to a subsequent stage startup control line includes:
and filtering the key signals, and sending the processed key signals to a rear-stage startup control circuit.
Further, not forwarding the critical signal, including:
and forcibly assigning the key signal to be low level.
The server power supply unit optimization device and method provided by the invention have the beneficial effects that the signal is optimized by adopting a mode of combining hardware design and CPLD logic design, the phenomenon that the server cannot be started due to abnormal height increase caused by leakage current of external equipment when the PSU is not in place is prevented, meanwhile, the double guarantee of the signal is realized by optimizing the existing hardware circuit, the problem that the server cannot be started is effectively avoided, the stability of the product is improved, and the customer satisfaction and the competitiveness of the product are improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a server power supply unit optimization apparatus according to an embodiment of the present application.
Fig. 2 is an exemplary flowchart of a server power supply unit optimization method according to an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
The hardware circuit of the existing PSU (power supply unit) is that different power supply unit hardware is connected with the input end of a logic AND gate through a pull-down resistor, and the output end of the logic AND gate is respectively connected with a P12V conversion circuit and a CPLD sequential control chip. The resistance values of the pull-down resistors are all 1M omega. When the leakage current is large, the structure can affect the key signals of the PSU, especially when the PSU is not in place, the PSU is more remarkable, and then the subsequent startup time sequence of the server is affected, so that the server cannot be started to operate.
Referring to fig. 1, the present embodiment provides a server power supply unit optimization device, which includes a CPLD, where an input end of the CPLD is connected to a key signal output end and an in-place signal output end of power supply unit hardware; the output end of the CPLD is connected with a rear-stage startup control circuit, and the rear-stage startup control circuit deduces the voltage required by startup operation according to the key signal of the self-powered unit hardware forwarded by the CPLD. The back stage boot control circuit includes: the input end of the logic AND gate is connected with the output end of the CPLD, and a pull-down resistor is arranged on a connecting branch of the input end of the logic AND gate and the output end of the CPLD; the output end of the logic AND gate is respectively connected with the P12V switching cable and the timing control chip. The resistance of the pull-down resistor is 200K omega.
Taking two power supply unit hardware as an example for explanation, a first input end of the CPLD is connected with a key signal output end and an in-place signal output end of the first power supply unit hardware (PSU _ 1); a second input end of the CPLD is connected with a key signal output end and an in-place signal output end of second power supply unit hardware (PSU _ 2); the first output end of the CPLD is connected with the first input end of the logic AND gate, and a first pull-down resistor is arranged on a first connecting branch between the first input end of the logic AND gate and the first output end of the CPLD; the second output end of the CPLD is connected with the second input end of the logic AND gate, and a second pull-down resistor is arranged on a second connecting branch between the second input end of the logic AND gate and the second output end of the CPLD; the first output end of the CPLD forwards the signal of the first input end, and the second output end of the CPLD forwards the signal of the second input end. The resistance values of the first pull-down resistor and the second pull-down resistor are both 200K omega.
The server power supply unit optimization device provided by the embodiment confirms whether the state of the PSU key signal is normal or not by additionally judging whether the PSU is in-place information or not, and performs optimization processing inside the CPLD based on the judgment, and simultaneously optimizes the design of a hardware pull-down resistor, thereby doubly ensuring that the PSU key signal is not influenced. Specifically, the method comprises the following steps: firstly, two key designs are added on a hardware circuit, namely, a pull-down resistance value is modified to 200 Komega for a PSU key signal (PSU _ PWROK); and secondly, the in-place signal (PSU _ PRESENT) of the PSU is accessed into the CPLD, and the PSU _ PWROK signal is also accessed into the CPLD, processed by the CPLD and then input into a post-stage circuit. Then, designing the internal logic of the CPLD, when the PSU _ PWROK signal is input to high level, firstly judging whether the PSU is in place, if so, judging that the PSU is normal, carrying out filtering operation on the CPLD aiming at the key signal PSU _ PWROK to ensure the stability of the PSU and then outputting the PSU to a post-stage line, if not, judging that the PSU is an abnormal signal, and forcibly assigning the signal to low level by the CPLD and then outputting the signal to the post-stage line. Therefore, when the PSU is not in place but the PSU key signal PSU _ PWROK is abnormally increased due to external factors, the overcurrent protection caused by abnormal opening of a later-stage line can be avoided through the design optimization, the problem that the server cannot be started is effectively prevented, the stability of the product is improved, and the customer satisfaction and the competitiveness of the product are improved. In addition, the pull-down resistor of the PSU key signal PSU _ PWROK is modified from 1M omega to 200K omega, the pull-down strength is enhanced, and double guarantee of signals is achieved.
Referring to fig. 2, the present embodiment provides a method for optimizing a power supply unit of a server, including the following steps:
when the CPLD receives that the key signal input of certain power supply unit hardware is at a high level, whether the input power supply unit hardware in-place signal is logic 1 or not is judged firstly, if the input power supply unit hardware in-place signal is logic 1, the PSU is in place, the CPLD only plays a role in filtering optimization, if the input power supply unit hardware in-place signal is logic 0, the PSU is not in place, the CPLD forces the key signal of the power supply unit hardware to be assigned to a low level, and false triggering is avoided.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A server power supply unit optimization apparatus, comprising:
the input end of the CPLD is connected with the key signal output end and the on-site signal output end of the power supply unit hardware; the output end of the CPLD is connected with a rear-stage startup control circuit, and the rear-stage startup control circuit deduces the voltage required by startup operation according to the key signal of the CPLD forwarding self-powered unit hardware.
2. The apparatus of claim 1, wherein the post-stage power-on control circuit comprises:
the input end of the logic AND gate is connected with the output end of the CPLD, and a pull-down resistor is arranged on a connecting branch of the input end of the logic AND gate and the output end of the CPLD; the output end of the logic AND gate is respectively connected with the P12V switching cable and the timing control chip.
3. The apparatus of claim 2, wherein the pull-down resistor has a resistance of 200K Ω.
4. The device of claim 1, wherein the first input terminal of the CPLD is connected to the critical signal output terminal and the in-place signal output terminal of the first power supply unit hardware; the second input end of the CPLD is connected with the key signal output end and the in-place signal output end of the second power supply unit hardware; the first output end of the CPLD is connected with the first input end of the logic AND gate, and a first pull-down resistor is arranged on a first connecting branch between the first input end of the logic AND gate and the first output end of the CPLD; the second output end of the CPLD is connected with the second input end of the logic AND gate, and a second pull-down resistor is arranged on a second connecting branch between the second input end of the logic AND gate and the second output end of the CPLD; the first output end of the CPLD forwards the signal of the first input end, and the second output end of the CPLD forwards the signal of the second input end.
5. The apparatus of claim 4, wherein the first pull-down resistor and the second pull-down resistor each have a resistance of 200K Ω.
6. A method for optimizing a power supply unit of a server, the method comprising:
after receiving a key signal of power supply unit hardware, the CPLD judges whether an in-place signal of the power supply unit hardware is received at the same time:
if yes, forwarding the key signal to a rear-stage startup control circuit;
if not, the key signal is not forwarded.
7. The method of claim 6, wherein forwarding the critical signal to a subsequent stage power-on control line comprises:
and filtering the key signals, and sending the processed key signals to a rear-stage startup control circuit.
8. The method of claim 6, wherein not forwarding the critical signal comprises:
and forcibly assigning the key signal to be low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210607694.XA CN114860057B (en) | 2022-05-31 | 2022-05-31 | Device and method for optimizing power supply unit of server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210607694.XA CN114860057B (en) | 2022-05-31 | 2022-05-31 | Device and method for optimizing power supply unit of server |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114860057A true CN114860057A (en) | 2022-08-05 |
| CN114860057B CN114860057B (en) | 2023-07-14 |
Family
ID=82641330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210607694.XA Active CN114860057B (en) | 2022-05-31 | 2022-05-31 | Device and method for optimizing power supply unit of server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114860057B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016061771A1 (en) * | 2014-10-22 | 2016-04-28 | 华为技术有限公司 | Power-on circuit and electronic device |
| CN106201758A (en) * | 2016-07-15 | 2016-12-07 | 浪潮电子信息产业股份有限公司 | The method and device that a kind of server node hard disk powers on |
| CN108549279A (en) * | 2018-04-02 | 2018-09-18 | 郑州云海信息技术有限公司 | A kind of method and apparatus for preventing server master board core voltage from leaking electricity |
| WO2022007414A1 (en) * | 2020-07-10 | 2022-01-13 | 苏州浪潮智能科技有限公司 | Server fan control device and method based on control chip |
-
2022
- 2022-05-31 CN CN202210607694.XA patent/CN114860057B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016061771A1 (en) * | 2014-10-22 | 2016-04-28 | 华为技术有限公司 | Power-on circuit and electronic device |
| CN106201758A (en) * | 2016-07-15 | 2016-12-07 | 浪潮电子信息产业股份有限公司 | The method and device that a kind of server node hard disk powers on |
| CN108549279A (en) * | 2018-04-02 | 2018-09-18 | 郑州云海信息技术有限公司 | A kind of method and apparatus for preventing server master board core voltage from leaking electricity |
| WO2022007414A1 (en) * | 2020-07-10 | 2022-01-13 | 苏州浪潮智能科技有限公司 | Server fan control device and method based on control chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114860057B (en) | 2023-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102714607B (en) | Connectivity fault management timeout period control | |
| CN107070731B (en) | Master-slave arbitration method and system | |
| CN107729205B (en) | Fault processing method and device for business system | |
| CN104969222A (en) | Method and system for using a recursive event listener on a node in hierarchical data structure | |
| CN104049709A (en) | Power management method of server system | |
| EP4024765B1 (en) | Method and apparatus for extracting fault propagation condition, and storage medium | |
| CN111176897A (en) | Closed BIOS self-repairing method, system, terminal and storage medium | |
| CN111163172B (en) | Message processing system, method, electronic device and storage medium | |
| CN114860057A (en) | Server power supply unit optimization device and method | |
| CN112231145B (en) | CPLD (Complex programmable logic device) -based switching structure and method for controlling BMC (baseboard management controller) restart | |
| CN111381660B (en) | Power supply control system and method of multi-node server based on CPLD (complex programmable logic device) | |
| CN117687778A (en) | Redis cluster switching method and device, electronic equipment and storage medium | |
| CN111090537B (en) | Cluster starting method and device, electronic equipment and readable storage medium | |
| CN117076196A (en) | Database disaster recovery management and control method and device | |
| CN116719639A (en) | Link dynamic adjustment and data processing method, device, computer equipment and medium | |
| CN115344290A (en) | Distributed storage grouping online upgrading method, device, terminal and medium | |
| CN112799879B (en) | Fault processing method, device, equipment and storage medium of node | |
| CN112379763A (en) | Method, system, equipment and medium for preventing electric leakage | |
| CN113839656B (en) | Time sequence discharging circuit of server power supply | |
| CN118118010B (en) | Clock detection circuit, clock detection method, chip and communication system | |
| CN115174708B (en) | Message receiving and information determining method, device, exchange chip, equipment and system | |
| CN118102152B (en) | Power failure warning system and network equipment | |
| CN114338369B (en) | Annular two-place three-center fault diagnosis method, system and device | |
| CN107483290B (en) | Main engine election method and device based on switch | |
| CN118337629A (en) | Data transmission system, method, device, equipment and medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |