WO2016061771A1

WO2016061771A1 - Power-on circuit and electronic device

Info

Publication number: WO2016061771A1
Application number: PCT/CN2014/089203
Authority: WO
Inventors: 喻俊峰
Original assignee: 华为技术有限公司
Priority date: 2014-10-22
Filing date: 2014-10-22
Publication date: 2016-04-28

Abstract

A power-on circuit and an electronic device, which relate to the technical field of communications and are used for powering on the electronic device when the electronic device is in a power-off state. In the power-on circuit, one end of a first switch unit (2) is connected to an input end of a first conversion unit (3). An output end of the first conversion unit (3) is connected to a first input end of an AND gate (6). One end of a second switch unit (5) is connected to a second input end of the AND gate (6), and the other end of the second switch unit (5) is grounded. An output end of the AND gate (6) is connected to a controller (4). When the state of the first switch unit (2) is changed, the first conversion unit (3) outputs a first signal to the AND gate (6), so that the AND gate (6) outputs a power-on triggering signal to the controller (4), and the controller (4) executes a power-on operation according to the power-on triggering signal. When the state of the second switch unit (5) is changed, the AND gate (6) outputs a power-on triggering signal to the controller (4), and the controller (4) executes a power-on operation according to the power-on triggering signal.

Description

Boot circuit and electronic device

Technical field

The embodiments of the present invention relate to the field of communications technologies, and in particular, to a booting circuit and an electronic device.

Background technique

With the continuous development of information technology and electronic technology, electronic devices, such as mobile phones, digital cameras, notebook computers, etc., have gradually become one of the essential devices in people's lives.

Currently, existing electronic devices are provided with a power button, which can be used to turn the electronic device on or off. Take the power button configured in the mobile phone as an example. When the mobile phone is in the off state, press and hold the power button to turn on the phone. When the phone is turned on, press and hold the power button to turn off the phone.

However, when the electronic device is in the off state, only the long press of the power button can realize the booting of the electronic device, and the electronic device cannot be turned on by other means.

Summary of the invention

Embodiments of the present invention provide a booting circuit and an electronic device for enabling booting of an electronic device when the electronic device is in a power off state.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In a first aspect, an embodiment of the present invention provides a booting circuit, which is applied to an electronic device, where the booting circuit includes: a first switch unit, a second switch unit, an AND gate, a first conversion unit, and a controller;

One end of the first switching unit is connected to an input end of the first conversion unit, an output end of the first conversion unit is connected to a first input end of the AND gate, and one end of the second switching unit is The second input end of the door is connected, the other end of the second switch unit is grounded, and the output end of the AND gate is connected to the controller;

When the state of the first switching unit changes, the first converting unit outputs a first signal to the AND gate, so that the AND gate outputs a power-on trigger signal to the control The controller performs a booting operation according to the boot trigger signal;

When the state of the second switch unit changes, the AND gate outputs a power-on trigger signal to the controller, and the controller performs a power-on operation according to the power-on trigger signal.

In a first possible implementation manner of the first aspect, the booting circuit further includes: a first power source; the first power source is connected to another end of the first switch unit;

The state change of the first switch unit is specifically: the first switch unit changes from an open state to a closed state.

In a second possible implementation manner of the first aspect, the other end of the first switch unit is grounded;

The state change of the first switch unit is specifically: the first switch unit changes from a closed state to an open state.

In a first aspect or any one of the first two possible implementations of the first aspect, a third possible implementation manner of the first aspect is further provided, where the state change of the second switch unit is specifically: The two switching units are changed from the off state to the closed state.

In a first aspect, or any one of the first three possible implementation manners of the first aspect, the fourth possible implementation manner of the first aspect is further provided, where the power-on trigger signal is a low-level signal; The signal is a low level signal.

In the first aspect or the first four possible implementation manners of the first aspect, a fifth possible implementation manner of the first aspect is further provided, the booting circuit further includes: an OR gate, where the OR gate is connected Between the first conversion unit and the AND gate;

An output end of the first conversion unit is connected to a first input end of the OR gate, and a first universal input output pin of the controller is connected to a second input end of the OR gate, the OR gate The output terminal is connected to the first input end of the AND gate; wherein, when the electronic device is in a shutdown state, the signal output by the first universal input/output pin of the controller is a low level signal.

In a fifth possible implementation manner of the first aspect, a sixth possible implementation manner of the first aspect is further provided, where the booting circuit further includes: a second converting unit;

An input end of the second conversion unit is connected to a first universal input/output pin of the controller, and an output end of the second conversion unit is connected to a second input end of the OR gate; the second conversion The unit is configured to convert a signal output by the first universal input/output pin of the controller to a low level signal when the electronic device is in a power off state.

In a sixth possible implementation manner of the first aspect, a seventh possible implementation manner of the first aspect is further provided, when the electronic device is in a power on state, the first universal input and output tube of the controller The signal output by the pin is a high level signal; the second conversion unit is configured to convert a signal output by the first universal input/output pin of the controller to a high level signal when the electronic device is in a power on state.

In the first aspect or any of the first seven possible implementation manners of the first aspect, the eighth possible implementation manner of the first aspect is further provided, where the booting circuit further includes: a third converting unit, a third power source ;

a first input end of the third conversion unit is connected to an input end of the first conversion unit, a second input end of the third conversion unit is connected to the third power source, and an output of the third conversion unit The end is connected to the second universal input and output pin of the controller; the third converting unit is configured to output a control signal to the second universal input and output pin of the controller when the first switch unit is closed So that the controller performs a corresponding operation according to the control signal.

In an eighth possible implementation manner of the first aspect, the ninth possible implementation manner of the first aspect is further provided, wherein the controller sends an alarm message according to the control signal, or issues positioning information.

In a first possible implementation manner of the first aspect, a tenth possible implementation manner of the first aspect is further provided, where the first conversion unit includes a first NMOS transistor, a first resistor, and a second resistor;

The first power source is connected to the drain of the first NMOS transistor through a first resistor; the drain of the first NMOS transistor is further connected to a first input end of the OR gate, the first NMOS transistor a gate is connected to one end of the first switching unit, a source of the first NMOS transistor is grounded; one end of the second resistor is connected to a gate of the first NMOS transistor, and the other end of the second resistor is The source of the first NMOS transistor is connected.

In a second possible implementation manner of the first aspect, the eleventh possible implementation manner of the first aspect is further provided, where the first conversion unit includes: a second power source, a first PMOS transistor, and a third resistor Fourth resistance;

The second power source is connected to a source of the first PMOS transistor, a gate of the first PMOS is connected to one end of the first switching unit, and a drain of the first PMOS transistor is opposite to the third One end of the resistor is connected, the drain of the first PMOS transistor is also connected to the first input end of the AND gate, and the other end of the third resistor is grounded; the fourth resistor One end is connected to the source of the first PMOS transistor, and the other end of the fourth resistor is connected to the gate of the first PMOS transistor.

In a second to a ninth possible implementation manner of the first aspect, a twelfth possible implementation manner of the first aspect is further provided, where the second conversion unit includes: a second NMOS transistor, a three NMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;

The first power source is connected to the drain of the second NMOS transistor through the fifth resistor, and the gate of the second NMOS transistor is connected to the first universal input and output pin of the controller, The source of the two NMOS transistors is grounded; the first power source is connected to the drain of the third NMOS transistor through the sixth resistor, and the drain of the third NMOS transistor is further connected to the second input of the OR gate An end connection, a gate of the third NMOS transistor is connected to a drain of the second NMOS transistor, a source of the third NMOS transistor is grounded; and one end of the seventh resistor is opposite to the second NMOS transistor The gate is connected, and the other end of the seventh resistor is connected to the source of the second NMOS transistor.

In a sixth to a ninth possible implementation manner of the first aspect, the thirteenth possible implementation manner of the first aspect is further provided, where the second conversion unit includes: a fourth NMOS transistor, Two PMOS tubes and eighth resistors;

The first power source is connected to the drain of the fourth NMOS transistor through the eighth resistor, and the gate of the fourth NMOS transistor is connected to the first universal input and output pin of the controller, where the a source of the fourth NMOS transistor is grounded; a source of the second PMOS transistor is connected to the first power source, a gate of the second PMOS transistor is connected to a drain of the fourth NMOS transistor, and the second A drain of the PMOS transistor is coupled to a second input of the OR gate.

In any of the eighth to ninth possible implementation manners of the first aspect, the fourteenth possible implementation manner of the first aspect is further provided, where the third conversion unit includes a fifth NMOS transistor and a ninth resistance;

a gate of the fifth NMOS transistor is connected to a gate of the first NMOS transistor, a drain of the fifth NMOS transistor is connected to the second power source, and a source of the fifth NMOS transistor is A second universal input/output pin of the controller is connected; one end of the ninth resistor is connected to a source of the fifth NMOS transistor, and the other end of the ninth resistor is grounded.

In a first aspect or any one of the first fourteen possible implementation manners of the first aspect, the fifteenth possible implementation manner of the first aspect is further provided, the first switch unit is a pull ring switch or used for Alarm switch.

In a second aspect, an embodiment of the present invention provides an electronic device, including a display screen. The processor, the memory, and the transceiver, further comprising the booting circuit of the first aspect or any of the fifteen possible implementations of the first aspect.

The booting circuit provided by the embodiment of the present invention, when the electronic device is in the off state, changes the state of the first switch unit or the second switch unit, so that the AND gate outputs a power-on trigger signal to the controller, and the controller according to the The power-on trigger signal is used to perform the power-on operation. In the prior art, the power-on of the electronic device is implemented by using a long-pressing power button. Compared with the prior art, the embodiment of the present invention can implement the power-on of the electronic device in other manners.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a schematic diagram of a booting circuit according to an embodiment of the present invention;

2 is a schematic diagram of a booting circuit provided on the basis of FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the booting circuit shown in FIG. 2 according to an embodiment of the present invention; FIG.

4 is a schematic diagram of another booting circuit provided on the basis of FIG. 1 according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another booting circuit provided on the basis of FIG. 2 according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic diagram of the booting circuit shown in FIG. 5 according to an embodiment of the present invention; FIG.

FIG. 7 is a schematic diagram of another booting circuit provided on the basis of FIG. 5 according to an embodiment of the present invention; FIG.

FIG. 8 is a schematic diagram of a booting circuit shown in FIG. 7 according to an embodiment of the present invention; FIG.

FIG. 9 is a schematic diagram of another boot circuit shown in FIG. 7 according to an embodiment of the present invention. schematic diagram;

FIG. 10 is a schematic diagram of another booting circuit provided on the basis of FIG. 7 according to an embodiment of the present invention; FIG.

FIG. 11 is a schematic diagram of a booting circuit shown in FIG. 10 according to an embodiment of the present invention; FIG.

FIG. 12 is a schematic diagram of an electronic device according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Embodiment 1

The embodiment of the invention provides a booting circuit, which is applied to an electronic device. As shown in FIG. 1 , the booting circuit includes: a first switching unit 2, a first converting unit 3, a controller 4, a second switching unit 5, and an AND gate 6.

One end of the first switch unit 2 is connected to the input end of the first conversion unit 3, and the output end of the first conversion unit 3 is connected to the first input end of the AND gate 6. One end of the two switch unit 5 is connected to the second input end of the AND gate 6, the other end of the second switch unit 5 is grounded, and the output end of the AND gate 6 is connected to the controller 4; for example, The output end of the gate 6 can be connected to the boot pin 41 of the controller 4;

When the state of the first switching unit 2 changes, the first converting unit 3 outputs a first signal to the AND gate 6 to cause the AND gate 6 to output a power-on trigger signal to the controller 4, The controller 4 performs a power-on operation according to the power-on trigger signal;

When the state of the second switching unit 5 changes, the AND gate 6 outputs a power-on trigger signal to the controller 4, and the controller 4 performs a power-on operation according to the power-on trigger signal.

The states of the first switch unit 2 and the second switch unit 5 may be a closed state or an open state, and therefore, the state of the first switch unit 2 changes and The state change of the second switching unit 5 is a change between a closed state and an open state.

The embodiment of the present invention can implement the booting of the electronic device by the state change of the first switch unit or the second switch unit. When the powering on of the electronic device is implemented by the state change of the first switch, there are two ways: one is to start the power from the off state to the closed state by the first switch unit 2, or the first switch unit can also be used. 2 Start from the closed state to the disconnected state. These two methods correspond to different specific implementations. The following two implementations are described separately.

First type: When the first switching unit 2 is changed from the off state to the closed state, the electronic device is turned on. See Figure 2 and Figure 3 for details.

As shown in FIG. 2, on the basis of the embodiment shown in FIG. 1, the booting circuit further includes: a first power source 1; and the first power source 1 is connected to the other end of the first switch unit 2.

Specifically, when the first switch unit 2 is closed, the first conversion unit 3 outputs a first signal to the AND gate 6 to cause the AND gate 6 to output a power-on trigger signal to the controller 4, The controller 4 performs a power-on operation according to the power-on trigger signal; when the second switch unit 5 is closed, the AND gate 6 outputs a power-on trigger signal to the controller 4, and the controller 4 according to the The power-on trigger signal performs a power-on operation.

Preferably, when the first switching unit 2 is closed, the first signal output by the first converting unit 3 is a low level signal, and the power-on trigger signal output by the AND gate 6 is a low level signal; When the second switching unit 5 is closed, the power-on trigger signal output by the AND gate 6 is a low level signal.

For the first conversion unit shown in FIG. 1 , optionally, as shown in FIG. 3 , the first conversion unit 3 may include a first NMOS transistor 31 , a first resistor 32 and a second resistor 33 , wherein The first power source 1 (represented by VCC1 in FIG. 3) is connected to the drain of the first NMOS transistor 31 through the first resistor 32; the drain of the first NMOS transistor 31 and the boot pin of the controller 4 41 is connected, a gate of the first NMOS transistor 31 is connected to one end of the first switching unit 2, a drain of the first NMOS transistor 31 is grounded; and one end of the second resistor 33 is connected to the first NMOS transistor The gate of 31 is connected, and the other end of the second resistor 33 is connected to the source of the first NMOS transistor 31.

Thus, when the first switching unit 2 is closed, the gate and the first NMOS transistor 31 are When the power source VCC1 is connected, the first NMOS transistor 31 is turned on, and the drain voltage of the first NMOS transistor 31 is equivalent to the source voltage of the first NMOS transistor 31. Since the source of the first NMOS transistor 31 is connected to the ground, and The drain of an NMOS transistor 31 is connected to the first input terminal Y of the AND gate 6, and the signal input to the first input terminal Y of the AND gate 6 is a low level signal; according to the characteristics of the AND gate, only when input to and When the signal of the gate is a high level signal, the output of the AND gate is a high level signal, otherwise the output of the AND gate is a low level signal. Then, according to the above description, when the first switching unit 2 is closed, the input is The signal of the first input terminal Y of the AND gate 6 is a low level signal. Therefore, regardless of whether the second switching unit 5 is open or closed, the signal outputted from the output terminal Z of the AND gate 6 is a low level signal. Further, The low level signal outputted from the output terminal Z of the AND gate 6 is input to the boot pin 41 of the controller 4, that is, the power-on trigger signal is a low level signal, and the controller 4 performs a power-on operation according to the low level signal.

Alternatively, when the second switching unit 5 is closed, since one end of the second switching unit 5 is grounded, the signal input to the second input terminal X of the first AND gate 6 is a low level signal; likewise, according to the AND gate Characteristic, the output of the AND gate is high only when the signal input to the AND gate is high level, otherwise the output of the AND gate is low level, then, according to the above description, when the second switching unit 5 is closed The signal input to the second input terminal X of the AND gate 6 is a low level signal. Therefore, regardless of whether the first switching unit 2 is open or closed, the signal output from the output terminal Z of the AND gate 6 is a low level signal. Further, the low level signal outputted from the output terminal Z of the AND gate 6 is input to the boot pin 41 of the controller 4, that is, the power-on trigger signal is a low level signal, and the controller 4 performs a power-on operation according to the low level signal.

Further, as the functions of the electronic device are integrated, the power-on and power-off functions of the electronic device are integrated. Therefore, the controller of the electronic device uses the same pin (the boot pin 41 as shown in FIG. 1 to FIG. 3). Receiving a power-on trigger signal and a power-off trigger signal; in general, a pin for receiving a power-on trigger signal or a power-off trigger signal in a controller of the electronic device performs a power-on or power-off operation when receiving a low-level signal. For example, when the electronic device is in the power-off state, when the power-on pin 41 of the controller 4 receives the low-level signal, the controller 4 performs the power-on operation according to the level signal; when the electronic device is turned on, the controller 4 When the boot pin 41 receives the low level signal, the controller 4 performs a shutdown operation based on the level signal. of course, By simple replacement, the switch pin of the electronic device performs the power-on or power-off operation when receiving the high-level signal, which also belongs to the scope to be protected by the embodiment of the present invention. The embodiment of the present invention is described by taking an example of performing a power on or power off operation at a low level signal.

Specifically, the boot circuit shown in FIG. 3 is taken as an example for description. When the electronic device is turned on, the first switching unit 2 and the second switching unit 5 are turned off. At this time, the first NMOS transistor 31 is turned off, the signal of the first power source VCC1 input to the first input terminal Y of the AND gate 6 through the first resistor 32 is a high level signal, and is input to the second input terminal X of the AND gate 6. The signal is also a high level signal; according to the characteristics of the AND gate, the signal output from the output of the AND gate 6 is a high level signal, and at the same time, the high level signal output from the AND gate 6 is input to the boot tube of the controller 4. Foot 41, the signal does not affect the power-on state of the electronic device.

Further, if the electronic device needs to be turned from the power-on state to the power-off state, when the first switch unit 2 is closed, the first NMOS transistor is turned on, and at this time, the signal input to the first input terminal Y of the AND gate 6 is low. Flat signal; then, according to the characteristics of the AND gate, whether the second switching unit 5 is open or closed, the signal output from the output terminal Z of the AND gate 6 is a low level signal, and further, the output terminal Z of the AND gate 6 The output low level signal is input to the boot pin 41 of the controller 4, and the controller 4 performs a shutdown operation based on the low level signal.

Alternatively, if the electronic device needs to be turned from the power-on state to the power-off state, when the second switch unit 5 is closed, since one end of the second switch unit 5 is grounded, the signal input to the second input terminal X of the AND gate 6 is low. Flat signal; then, according to the characteristics of the AND gate, whether the first switching unit 2 is open or closed, the signal output from the output terminal Z of the AND gate 6 is a low level signal, and further, the output terminal Z of the AND gate 6 The output low level signal is input to the boot pin 41 of the controller 4, and the controller 4 performs a shutdown operation based on the low level signal.

If the booting circuit described above is applied to the mobile phone, the controller 4 may be a Micro Controller Unit (MCU), and the voltage of the first power source 1 is the battery voltage of the mobile phone. In general, the mobile phone The battery voltage is between 3.2V and 4.35V, and the current maximum battery voltage is 4.2V.

It should be noted that, in FIG. 3, the first conversion unit 3 includes a single NMOS transistor as an example, but is not limited thereto. Meanwhile, in FIG. 3, only the first resistor and the second resistor include one resistor as an example for description. The first resistor and the second resistor may also be a series or a parallel connection of a plurality of resistors.

Second type: When the first switch unit 2 is changed from the closed state to the open state, the electronic device is turned on. See Figure 4 for details.

As shown in FIG. 4, on the basis of the embodiment shown in FIG. 1, one end of the first switching unit 2 is connected to the gate of the first PMOS 34, and the other end of the first switching unit 2 is grounded.

When the other end of the first switch unit 2 is grounded, as shown in FIG. 4, the first conversion unit 3 may include: a first PMOS transistor 34, a third resistor 35, and a fourth resistor 36. a second power source; wherein the second power source (indicated by VCC2 in FIG. 4) is connected to a source of the first PMOS transistor 34, and a gate of the first PMOS 34 and one end of the first switching unit 2 Connecting, the drain of the first PMOS transistor 34 is connected to one end of the third resistor 35, and the drain of the first PMOS transistor 34 is also connected to the first input terminal Y of the AND gate 6. The other end of the third resistor 35 is grounded; one end of the fourth resistor 36 is connected to the source of the first PMOS transistor 34, and the other end of the fourth resistor 36 is connected to the gate of the first PMOS transistor 34. connection.

Thus, when the first switching unit 2 is turned off, the voltage of the gate and the source of the first PMOS transistor 34 is substantially the same by the pull-up of the fourth resistor 36, and the first PMOS transistor 34 is turned off, and the third resistor is passed through the third resistor. The pull-down effect of 35, the signal input to the first input terminal Y of the AND gate 6 is a low level signal; according to the characteristics of the AND gate 6, at this time, regardless of whether the second switching unit 5 is open or closed, the AND gate 6 The signal outputted by the output terminal Z is a low level signal. Further, the low level signal outputted from the output terminal Z of the gate 6 is input to the boot pin 41 of the controller 4, that is, the power-on trigger signal is a low level signal, and the control is performed. The device 4 performs a power-on operation based on the low level signal.

Alternatively, when the second switching unit 5 is closed, since one end of the second switching unit 5 is grounded, the signal input to the second input terminal X of the AND gate 6 is a low level signal; likewise, according to the characteristics of the AND gate, Only when the signal input to the AND gate is high, the output of the AND gate is high, otherwise the output of the AND gate is low, then, according to the above description, when the second switching unit 5 is closed, the input The signal to the second input terminal X of the AND gate 6 is a low level signal. Therefore, regardless of whether the first switching unit 2 is open or closed, the signal output from the output terminal Z of the AND gate 6 is a low level signal, further The low level signal outputted from the output terminal Z of the AND gate 6 is input to the boot pin 41 of the controller 4, that is, the power-on trigger signal is a low level signal, and the controller 4 performs a power-on operation according to the low level signal.

When the electronic device is in the on state, the first switching unit 2 is in the closed state, and the second switching unit 5 is in the off state. At this time, since the first switching unit 2 is closed, the first PMOS transistor is turned on, the signal input to the first input terminal Y of the AND gate 6 is a high level signal, and at the same time, since the second switching unit 5 is turned off, The signal input to the second input terminal X of the AND gate 6 is also a high level signal; according to the characteristics of the AND gate, the signal outputted from the output terminal of the AND gate 6 is a high level signal, and further, the output of the AND gate 6 is high. The level signal is input to the boot pin 41 of the controller 4, and the signal does not affect the power-on state of the electronic device.

As described above, the power-on and power-off pins are integrated into the same pin, and the boot pin 41 (or the switch pin) of the controller 4 in the electronic device performs booting when receiving the low-level signal. Or shut down the operation. Then, if the electronic device needs to be turned from the power-on state to the power-off state, when the first switch unit 2 is turned off, the first PMOS transistor is turned off, and at this time, the signal input to the first input terminal Y of the AND gate 6 is low. Signal; then, according to the characteristics of the AND gate, whether the second switching unit 5 is open or closed, the signal output from the output terminal Z of the AND gate 6 is a low level signal, and further, the output Z of the AND gate 6 is output. The low level signal is input to the boot pin 41 of the controller 4, and the controller 4 performs a shutdown operation based on the low level signal.

Alternatively, if the electronic device needs to be turned from the power-on state to the power-off state, when the second switch unit 5 is closed, since one end of the second switch unit 5 is grounded, the signal input to the second input terminal X of the first AND gate 6 is a low level signal; then, according to the characteristics of the AND gate, whether the first switching unit 2 is open or closed, the signal output from the output terminal Z of the AND gate 6 is a low level signal, and further, the output of the AND gate 6 The low level signal of the terminal Z output is input to the boot pin 41 of the controller 4, and the controller 4 performs a shutdown operation according to the low level signal.

It should be noted that, in FIG. 4, the first conversion unit 3 includes a single PMOS transistor as an example, but is not limited thereto. Meanwhile, in FIG. 4, the third resistor and the fourth resistor include a resistor as an example for description. The third resistor and the fourth resistor may also be a series or a parallel of a plurality of resistors.

The booting circuit provided by the embodiment of the present invention, when the electronic device is in the off state, changes the state of the first switch unit or the second switch unit, so that the AND gate outputs a power-on trigger signal to the controller, and the controller according to the The power-on trigger signal performs a power-on operation, and in the prior art, the electronic device is powered on only by long pressing the power button. Compared with the prior art, the embodiment of the present invention can implement booting of the electronic device by other means.

Embodiment 2

The embodiment of the present invention further provides a booting circuit based on the foregoing embodiments. Based on the booting circuits described above, the booting circuit further includes: an OR gate; the OR gate is connected between the first converting unit and the AND gate. An output end of the first conversion unit is connected to a first input end of the OR gate, and a first universal input output pin of the controller is connected to a second input end of the OR gate, the OR gate The output terminal is connected to the first input end of the AND gate; wherein, when the electronic device is in a shutdown state, the signal output by the first universal input/output pin of the controller is a low level signal.

Further, the booting circuit may further include: a second converting unit. An input end of the second conversion unit is connected to a first universal input/output pin of the controller, and an output end of the second conversion unit is connected to a second input end of the OR gate; the second conversion The unit is configured to convert a signal output by the first universal input/output pin of the controller to a low level signal when the electronic device is in a power off state.

Specifically, when the electronic device is in a power-on state, a signal output by the first universal input/output pin of the controller is a high level signal; and the second conversion unit is configured to be the first of the controller The general-purpose input/output pin converts a signal outputted when the electronic device is turned on to a high level signal.

The structure of the OR gate and the second conversion unit will be described below on the basis of the booting circuit shown in FIG. 2 or FIG. 3. As shown in FIG. 5, the booting circuit specifically includes: a first power source 1, a first switching unit 2, a first converting unit 3, a controller 4, a second switching unit 5, an AND gate 6, or an OR gate 7.

One end of the first switch unit 2 is connected to the first power source 1, and the other end of the first switch unit 2 is connected to an input end of the first conversion unit 3, the first conversion unit 3 The output terminal is connected to the first input end of the OR gate 7; the first general input input output (GPIO) 42 of the controller 4 and the second input end of the OR gate 7 Connecting, the output end of the OR gate 7 is connected to the first input end of the AND gate 6; one end of the second switch unit 5 is connected to the second input end of the AND gate 6, the AND gate 6 The output is connected to the boot pin 41 of the controller 4; wherein when the electronic device is off In the state of the machine, the signal output by the first universal input/output pin 42 of the controller 4 is a low level signal.

Thus, when the first switch unit 2 is closed, the OR gate 7 outputs a first signal to the AND gate 6. After the AND gate 6 receives the first signal, the AND gate 6 outputs a power-on trigger signal. To the controller 4, the controller 4 performs a power-on operation according to the power-on trigger signal; when the second switch unit 5 is closed, the AND gate 6 outputs a power-on trigger signal to the controller, The controller 4 performs a power-on operation according to the power-on trigger signal.

Preferably, the first signal is a low level signal, and the power on trigger signal is a low level signal.

For example, as shown in FIG. 6, the first conversion unit 3 in this embodiment adopts the same first conversion unit 3 as that in FIG. 3 of the first embodiment. For the specific connection manner of the first conversion unit 3, reference may be made. The description in the first embodiment will not be repeated here.

Specifically, when the electronic device needs to be from the power-off state to the power-on state, if the first switch unit 2 is closed, the gate of the first NMOS transistor 31 is connected to the first power source VCC1, and the first NMOS transistor 31 is turned on, the first NMOS The drain voltage of the transistor 31 is equivalent to the source voltage of the first NMOS transistor 31, since the source of the first NMOS transistor 31 is connected to the ground, and the drain of the first NMOS transistor 31 and the first input terminal of the AND gate 6 Y is connected, the signal input to the first input terminal B of the OR gate 7 is a low level signal, and at the same time, when the electronic device is in the off state, the signal output by the first general purpose input and output pin 42 of the controller 4 is Is a low level signal, which is the input signal of the second input terminal A of the OR gate 7, according to the characteristics of the OR gate, only when the signal input to the OR gate is a low level signal, the OR gate The output is a low level signal, otherwise the output of the OR gate is a high level signal, then, according to the above description, when the first switching unit 2 is closed, the signal outputted by the output of the OR gate 7 is a low level signal; a low level signal as an input signal to the first input Y of the AND gate 6, according to the AND gate Sex, regardless of whether the second switching unit 5 is open or closed, the signal outputted from the output terminal Z of the AND gate 6 is a low level signal; further, the low level signal outputted from the output terminal Z of the AND gate 6 is input to the controller. The boot pin 41 of 4, that is, the boot trigger signal is a low level signal, and the controller 4 performs a boot operation according to the low level signal.

Alternatively, when the electronic device needs to be from the power-off state to the power-on state, if the second switch unit 5 is closed, since one end of the second switch unit 5 is grounded, the input to the AND gate is The signal of the second input terminal X of 6 is a low level signal. According to the characteristics of the AND gate, the output of the AND gate is high only when the signal input to the AND gate is high level, otherwise the output of the AND gate Is low level, then, according to the above description, when the second switching unit 5 is closed, the signal input to the second input terminal X of the AND gate 6 is a low level signal, and therefore, regardless of whether the first switching unit 2 is turned off or When closed, the signal outputted from the output terminal Z of the AND gate 6 is a low level signal. Further, the low level signal outputted from the output terminal Z of the AND gate 6 is input to the boot pin 41 of the controller 4, that is, the power-on trigger signal As a low level signal, the controller 4 performs a power on operation based on the low level signal.

When the electronic device is in the power-on state, the second switch unit 3 is in the off state. Since the electronic device is in the power-on state, the signal output by the first input/output port 42 of the controller 4 is a high level signal, then the signal input to the second input terminal A of the OR gate 7 is a high level signal; In this case, regardless of any action (open or closed) on the first switching unit, depending on the characteristics of the OR gate, the signal output from the output terminal 7 of the OR gate is a high level signal, and at the same time, since the electronic device is turned on The second switch unit 5 is turned off, and the signal input to the second input terminal X of the AND gate 6 is a high level signal, then the signal output from the output terminal Z of the OR gate 6 is a high level signal, and the high level The signal is input to the boot pin 41 of the controller 4, and the high level signal does not affect the power-on state of the electronic device. That is to say, when the electronic device is in the power-on state and the second switch unit is in the off state, no matter how the first switch unit is operated, the power-on state of the electronic device is not affected, that is, the electronic device is not turned off. .

As described in the first embodiment, the power-on and power-off pins are integrated into the same pin, and the boot pin 41 (or the switch pin) of the controller 4 in the electronic device receives a low-level signal. Perform a power on or power off operation. Then, when the electronic device needs to be from the power-on state to the power-off state, since the signal input by the first universal input/output pin 42 of the controller 4 is a high level, and the high level signal is an input signal of the OR gate 7, Therefore, the signal outputted from the output terminal C of the OR gate 7 is always a high level signal, which is an input signal of the AND gate 6; at this time, the second switching unit 5 is closed due to the second switching unit 5 One end is grounded, and the signal input to the second input terminal X of the AND gate 6 is a low level signal. According to the characteristics of the AND gate, the signal outputted from the output terminal Z of the AND gate 6 is a low level signal, and the low level signal is input to The boot pin 41 of the controller 4, the controller performs a shutdown operation according to the low level signal.

Preferably, as shown in FIG. 7, the booting circuit further includes: a second converting unit 8. The input end of the second conversion unit 8 is connected to the first universal input/output pin 42 of the controller 4, and the output end of the second conversion unit 8 and the second input end of the OR gate 7 The second conversion unit 8 is configured to convert a signal output by the first universal input/output pin 42 of the controller 4 when the electronic device is in a power-off state to a low level signal.

Optionally, as shown in FIG. 8, the second conversion unit 8 may include: a second NMOS transistor 81, a third NMOS transistor 82, a fifth resistor 83, a sixth resistor 84, and a seventh resistor 85; The first power source 1 (represented by VCC1 in FIG. 8) is connected to the drain of the second NMOS transistor 81 through the fifth resistor 83, the gate of the second NMOS transistor 81 and the controller 4 The first general-purpose input/output pin 42 is connected, the source of the second NMOS transistor 81 is grounded, and the first power source 1 is connected to the drain of the third NMOS transistor 82 through the sixth resistor 84. The drain of the third NMOS transistor 82 is also connected to the second input terminal A of the OR gate 7, the gate of the third NMOS transistor 82 is connected to the drain of the second NMOS transistor 81, and the third NMOS transistor 82 is The source is grounded; one end of the seventh resistor 85 is connected to the gate of the second NMOS transistor 81, and the other end of the seventh resistor 85 is connected to the source of the second NMOS transistor 81.

As shown in FIG. 8, when the electronic device is in the off state, the signal output by the first universal input/output pin 42 of the controller 4 is a low level signal. At this time, the second NMOS transistor 81 is turned off and the second When the three NMOS transistors 82 are turned on, the drain voltage of the third NMOS transistor 82 is equivalent to the source voltage of the third NMOS transistor 82, and the source of the third NMOS transistor 82 is grounded, and the drain of the third NMOS transistor 82 is Connected to the second input terminal A of the OR gate 7, the signal input to the second input terminal A of the OR gate 7 is a low level signal; when the electronic device is in the power on state, the first of the controller 4 The signal output from the general-purpose input/output pin 42 is a high-level signal. At this time, the second NMOS transistor 81 is turned on and the third NMOS transistor 82 is turned off, and is input to the OR gate 7 by the pull-up action of the fourth resistor 84. The signal at the two input terminals A is a high level signal.

Optionally, the second converting unit 8 may be composed of other circuit components. As shown in FIG. 9, the second converting unit 8 may include: a fourth NMOS transistor 86, a second PMOS transistor 87, and an eighth resistor 88. The first power source 1 (represented by VCC1 in FIG. 8) is connected to the drain of the fourth NMOS transistor 86 through the eighth resistor 88, the fourth NMOS The gate of the tube 86 is connected to the first universal input/output pin 42 of the controller 4, the source of the fourth NMOS transistor 86 is grounded; the source of the second PMOS transistor 87 and the first power source 1 is connected, a gate of the second PMOS transistor 87 is connected to a drain of the fourth NMOS transistor 86, and a drain of the second PMOS transistor 87 is connected to a second input end of the OR gate 7.

As shown in FIG. 9, when the electronic device is in the off state, when the signal output by the first universal input/output pin 42 of the controller 4 is a low level signal, the fourth NMOS transistor 86 is turned off and the second PMOS is turned off. The tube 87 is turned off. At this time, the signal input to the second input terminal A of the OR gate 7 is a low level signal; when the electronic device is in the power on state, the first general purpose input and output pin 42 of the controller 4 When the output signal is a high level signal, the fourth NMOS transistor 86 is turned on and the second PMOS transistor 87 is turned on. At this time, the signal input to the second input terminal A of the OR gate 7 is a high level signal. Thus, when the electronic device is in the power-on state, as long as the second switch 5 is in the off state, no shutdown operation is performed on the electronic device regardless of whether the first switch 2 is in the off state or the closed state.

It should be noted that, on the basis of the embodiment shown in FIG. 4, the booting circuit may also include an OR gate and a second converting unit. At this time, the connection relationship between the OR gate and the second conversion unit and other units can be referred to as shown in FIG. 5 to FIG. 9. For the specific structure of the second conversion unit, reference may also be made to FIG. 5 to FIG. 9 , and details are not described herein again.

Further, as shown in FIG. 10, on the basis of the foregoing embodiments, the booting circuit may further include: a third converting unit 9, a third power source 10; wherein the first input end of the third converting unit 9 Connected to the input end of the first conversion unit 3, the second input end of the third conversion unit 9 is connected to the third power source 10, the output end of the third conversion unit 11 and the controller 4 The second universal input/output pin 43 is connected; the third converting unit 9 is configured to output a control signal to the second universal input/output pin 42 of the controller 4 when the first switching unit 2 is closed, So that the controller 4 performs a corresponding operation in accordance with the control signal.

Optionally, the controller 4 may issue an alarm message according to the control signal, or issue positioning information or the like.

Specifically, as shown in FIG. 11 , the third conversion unit 11 may include a fifth NMOS transistor 91 and a ninth resistor 92; a gate of the fifth NMOS transistor 91 and a gate of the first NMOS transistor 31 Connecting, the drain of the fifth NMOS transistor 91 and the second power The source 12 is connected, the source of the fifth NMOS transistor 91 is connected to the second universal input/output pin 43 of the controller 4; one end of the ninth resistor 92 and the source of the fifth NMOS transistor 91 Connected, the other end of the ninth resistor 92 is connected to the ground.

Thus, when the first switching unit 2 is turned off, the fifth NMOS transistor is turned off; when the first switching unit 2 is closed, the fifth NMOS transistor 91 is turned on, and the current signal of the drain output of the fifth NMOS transistor 91 (ie, control) The signal is given to the second universal input/output pin 43 of the controller 4, and the controller 4 can perform a corresponding operation according to the current signal, such as issuing an alarm or positioning information.

It should be noted that, for the above-mentioned first switch unit, it is a pull-ring switch or a switch for alarming; for the above-mentioned controller 4, performing corresponding operations according to the current signal received by the second universal input/output pin 43, However, due to the difference in the type or type of the controller, the voltage supplied from the second power source 10 needs to coincide with the level of the second universal input/output pin 43 in the controller 4, so that the controller can perform the corresponding operation. In general, the voltage of the second power supply is 1.8V, 2.6V or 3.3V.

For the specific working principle of the power-on circuit shown in FIG. 11, reference may be made to the above specific description of each unit, and details are not described herein again. In the embodiment, the booting circuit is further optimized on the basis of FIG. 3. Similarly, the booting circuit can be optimized on the basis of FIG. 4, which can be specifically referred to in the embodiment.

The embodiment of the invention provides a booting circuit, by closing the first switch unit or closing the second switch unit, so that the AND gate outputs a power-on trigger signal to the controller, and the controller performs a power-on operation according to the power-on trigger signal to implement the electronic device. In the prior art, the electronic device is booted by using a long press of the power button. Compared with the prior art, the embodiment of the present invention can implement the booting of the electronic device by other means.

Embodiment 3

An embodiment of the present invention further provides an electronic device, including: a display screen, a processor, a memory, and a transceiver, and the booting circuit described in any of the above embodiments. The electronic device can be, for example, a mobile phone, a tablet computer, a notebook computer, a UMPC (Ultra-mobile Personal Computer), a netbook, a PDA (Personal Digital Assistant), or the like. The embodiment of the present invention is described by taking a mobile phone as an example. FIG. 12 is a block diagram showing a part of the structure of the mobile phone 300 related to various embodiments of the present invention.

As shown in FIG. 12, the mobile phone 300 may include components such as an RF (radio frequency) circuit 320, a memory 330, an input unit 340, a display unit 350, a gravity sensor 360, an audio circuit 370, a processor 380, and a power source 390. It will be understood by those skilled in the art that the structure of the handset shown in FIG. 12 does not constitute a limitation to the handset, and may include more or less components than those illustrated, or some components may be combined, or different component arrangements.

The components of the mobile phone 300 will be specifically described below with reference to FIG. 12:

The RF circuit 320 can be used for receiving and transmitting signals during and after receiving or transmitting information, in particular, after receiving the downlink information of the base station, and processing it to the processor 380; in addition, transmitting the uplink data to the base station. Generally, RF circuits include, but are not limited to, an antenna, at least one amplifier, a transceiver, a coupler, an LNA (low noise amplifier), a duplexer, and the like. In addition, RF circuitry 320 can also communicate with the network and other devices via wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to GSM (global system of mobile communication), GPRS (general packet radio service), CDMA (code division multiple access) , code division multiple access), WCDMA (wideband code division multiple access), LTE (long term evolution), e-mail, SMS (short messaging service), and the like.

The memory 330 can be used to store software programs and modules, and the processor 380 executes various functional applications and data processing of the mobile phone 300 by running software programs and modules stored in the memory 330. The memory 330 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application required for at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may be stored according to The data created by the use of the mobile phone 300 (such as audio data, image data, phone book, etc.) and the like. Moreover, memory 330 can include high speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

The input unit 340 can be configured to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the handset 300. In particular, the input unit 340 can include a touch screen 341 as well as other input devices 342. A touch screen 341, also referred to as a touch panel, collects touch operations on or near the user (such as a user) The use of a finger, stylus or the like on any suitable object or accessory on the touch screen 341 or in the vicinity of the touch screen 341) and driving of the corresponding connection device in accordance with a predetermined program. Alternatively, the touch screen 341 may include two parts of a touch detection device and a touch controller. Wherein, the touch detection device detects the touch orientation of the user, and detects a signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts the touch information into contact coordinates, and sends the touch information. The processor 380 is provided and can receive commands from the processor 380 and execute them. In addition, the touch screen 341 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves. In addition to the touch screen 341, the input unit 340 may also include other input devices 342. In particular, other input devices 342 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control buttons, power switch buttons, etc.), trackballs, mice, joysticks, and the like.

The display unit 350 can be used to display information input by the user or information provided to the user and various menus of the mobile phone 300. The display unit 350 may include a display panel 351. Alternatively, the display panel 341 may be configured in the form of an LCD (Liquid Crystal Display), an OLED (Organic Light-Emitting Diode), or the like. Further, the touch screen 341 can cover the display panel 351, and when the touch screen 341 detects a touch operation on or near it, transmits to the processor 380 to determine the type of the touch event, and then the processor 380 displays the panel according to the type of the touch event. A corresponding visual output is provided on the 351. Although the touch screen 341 and the display panel 351 are implemented as two separate components to implement the input and input functions of the mobile phone 300 in FIG. 12, in some embodiments, the touch screen 341 may be integrated with the display panel 351 to implement the mobile phone 300. Input and output functions.

Gravity sensor 360 can detect the acceleration of the mobile phone in all directions (usually three axes). When it is stationary, it can detect the magnitude and direction of gravity. It can be used to identify the gesture of the mobile phone (such as horizontal and vertical screen switching, related Game, magnetometer attitude calibration), vibration recognition related functions (such as pedometer, tapping).

The handset 300 can also include other sensors, such as light sensors. In particular, the light sensor can include an ambient light sensor and a proximity light sensor. The ambient light sensor can adjust the brightness of the display panel 341 according to the brightness of the ambient light; the proximity light sensor can detect whether an object approaches or contacts the mobile phone, and can close the display panel 341 and/or the backlight when the mobile phone 300 moves to the ear. . The mobile phone 300 can also be configured with a gyroscope, Other sensors such as a barometer, a hygrometer, a thermometer, an infrared sensor, and the like are not described herein.

Audio circuitry 370, speaker 371, microphone 372 can provide an audio interface between the user and handset 300. The audio circuit 370 can transmit the converted electrical data of the received audio data to the speaker 371, and convert it into a sound signal output by the speaker 371; on the other hand, the microphone 372 converts the collected sound signal into an electrical signal, by the audio circuit 370. After receiving, it is converted to audio data, and then the audio data is output to the RF circuit 320 for transmission to, for example, another mobile phone, or the audio data is output to the memory 330 for further processing.

Processor 380 is the control center of handset 300, which connects various portions of the entire handset using various interfaces and lines, by running or executing software programs and/or modules stored in memory 330, and recalling data stored in memory 330, The various functions and processing data of the mobile phone 300 are performed to perform overall monitoring of the mobile phone. Optionally, the processor 380 may include one or more processing units; preferably, the processor 380 may integrate an application processor and a modem processor, where the application processor mainly processes an operating system, a user interface, an application, and the like. The modem processor primarily handles wireless communications. It will be appreciated that the above described modem processor may also not be integrated into the processor 380.

The handset 300 also includes a power source 390 (such as a battery) that supplies power to the various components. Preferably, the power source can be logically coupled to the processor 380 via a power management system to manage functions such as charging, discharging, and power management through the power management system.

Although not shown, the mobile phone 300 may further include a WiFi (Wireless Fidelity) module, a Bluetooth module, and the like, and details are not described herein again.

The handset further includes the booting circuit of any of the preceding embodiments. The first switching unit included in the booting circuit can be, for example, an alarm switch of the mobile phone, and the second switching unit can be, for example, a power switch of the mobile phone, that is, a power button.

Through the boot circuit, when the mobile phone is turned off, the mobile phone can be turned on by the alarm switch or the power switch. Therefore, a plurality of booting modes are provided, so that the user can turn on the mobile phone through the alarm switch in an emergency use situation, and then alarm through the alarm switch.

In the several embodiments provided by the present application, it should be understood that the disclosed system, The apparatus and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some of the pins, devices or units, and may be electrical, mechanical or otherwise.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that The technical solutions described in the foregoing embodiments are modified, or the equivalents of the technical features are replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

A booting circuit is characterized in that it is applied to an electronic device, and the booting circuit comprises: a first switch unit, a second switch unit, an AND gate, a first conversion unit, and a controller;

One end of the first switching unit is connected to an input end of the first conversion unit, an output end of the first conversion unit is connected to a first input end of the AND gate, and one end of the second switching unit is The second input end of the door is connected, the other end of the second switch unit is grounded, and the output end of the AND gate is connected to the controller;

When the state of the first switching unit changes, the first converting unit outputs a first signal to the AND gate, so that the AND gate outputs a power-on trigger signal to the controller, and the controller according to the Declaring a power-on trigger signal to perform a power-on operation;

When the state of the second switch unit changes, the AND gate outputs a power-on trigger signal to the controller, and the controller performs a power-on operation according to the power-on trigger signal.
The booting circuit of claim 1 , wherein the booting circuit further comprises: a first power source; the first power source is connected to the other end of the first switching unit;

The state change of the first switch unit is specifically: the first switch unit changes from an open state to a closed state.
The booting circuit according to claim 1, wherein the other end of the first switching unit is grounded;

The state change of the first switch unit is specifically: the first switch unit changes from a closed state to an open state.
The booting circuit according to any one of claims 1 to 3, wherein the state change of the second switching unit is specifically that the second switching unit changes from an off state to a closed state.
A booting circuit according to any one of claims 1 to 4, characterized in that:

The power-on trigger signal is a low level signal;

The first signal is a low level signal.
The booting circuit according to any one of claims 1 to 5, wherein the booting circuit further comprises: an OR gate, the OR gate being connected between the first converting unit and the AND gate;

An output end of the first conversion unit is connected to a first input end of the OR gate, and a first universal input/output pin of the controller is connected to a second input end of the OR gate, the OR gate The output end is connected to the first input end of the AND gate; wherein, when the electronic device is in a shutdown state, the signal output by the first universal input/output pin of the controller is a low level signal.
The booting circuit of claim 6, wherein the booting circuit further comprises: a second converting unit;

An input end of the second conversion unit is connected to a first universal input/output pin of the controller, and an output end of the second conversion unit is connected to a second input end of the OR gate; the second conversion The unit is configured to convert a signal output by the first universal input/output pin of the controller to a low level signal when the electronic device is in a power off state.
The booting circuit according to claim 7, wherein when the electronic device is in a power-on state, a signal output by the first universal input/output pin of the controller is a high level signal; and the second conversion The unit is configured to convert a signal output by the first universal input/output pin of the controller to a high level signal when the electronic device is in a power on state.
The booting circuit according to any one of claims 1-8, wherein the booting circuit further comprises: a third converting unit and a third power source;

a first input end of the third conversion unit is connected to an input end of the first conversion unit, a second input end of the third conversion unit is connected to the third power source, and an output of the third conversion unit The end is connected to the second universal input and output pin of the controller; the third converting unit is configured to output a control signal to the second universal input and output pin of the controller when the first switch unit is closed So that the controller performs a corresponding operation according to the control signal.
The booting circuit according to claim 9, wherein the controller issues an alarm message according to the control signal or issues positioning information.
The booting circuit of claim 2, wherein the first converting unit comprises a first NMOS transistor, a first resistor, and a second resistor;

The first power source is connected to the drain of the first NMOS transistor through a first resistor; the drain of the first NMOS transistor is further connected to a first input end of the OR gate, the first NMOS transistor a gate is connected to one end of the first switching unit, a source of the first NMOS transistor is grounded; one end of the second resistor is connected to a gate of the first NMOS transistor, and the other end of the second resistor is The source of the first NMOS transistor is connected.
The booting circuit of claim 3, wherein the first converting unit comprises: a second power source, a first PMOS transistor, a third resistor, and a fourth resistor;

The second power source is connected to a source of the first PMOS transistor, a gate of the first PMOS is connected to one end of the first switching unit, and a drain of the first PMOS transistor is opposite to the third One end of the resistor is connected, a drain of the first PMOS transistor is further connected to the first input end of the AND gate, and the other end of the third resistor is grounded; one end of the fourth resistor is opposite to the first PMOS The source of the tube is connected, and the other end of the fourth resistor is connected to the gate of the first PMOS transistor.
The booting circuit according to any one of claims 7 to 10, wherein the second converting unit comprises: a second NMOS transistor, a third NMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;

The first power source is connected to the drain of the second NMOS transistor through the fifth resistor, and the gate of the second NMOS transistor is connected to the first universal input and output pin of the controller, The source of the two NMOS transistors is grounded; the first power source is connected to the drain of the third NMOS transistor through the sixth resistor, and the drain of the third NMOS transistor is further connected to the second input of the OR gate An end connection, a gate of the third NMOS transistor is connected to a drain of the second NMOS transistor, a source of the third NMOS transistor is grounded; and one end of the seventh resistor is opposite to the second NMOS transistor The gate is connected, and the other end of the seventh resistor is connected to the source of the second NMOS transistor.
The booting circuit according to any one of claims 7 to 10, wherein the second converting unit comprises: a fourth NMOS transistor, a second PMOS transistor, and an eighth resistor;

The first power source is connected to the drain of the fourth NMOS transistor through the eighth resistor, and the gate of the fourth NMOS transistor is connected to the first universal input and output pin of the controller, where the a source of the fourth NMOS transistor is grounded; a source of the second PMOS transistor is connected to the first power source, a gate of the second PMOS transistor is connected to a drain of the fourth NMOS transistor, and the second A drain of the PMOS transistor is coupled to a second input of the OR gate.
The booting circuit according to any one of claims 9 to 10, wherein the third converting unit comprises a fifth NMOS transistor and a ninth resistor;

a gate of the fifth NMOS transistor is connected to a gate of the first NMOS transistor, a drain of the fifth NMOS transistor is connected to the second power source, and a source of the fifth NMOS transistor is A second universal input/output pin of the controller is connected; one end of the ninth resistor is connected to a source of the fifth NMOS transistor, and the other end of the ninth resistor is grounded.
The booting circuit according to any one of claims 1 to 15, characterized in that the first switching unit is a pull ring switch or a switch for alarming.
An electronic device comprising: a display screen, a processor, a memory, and a transceiver, further comprising the power-on circuit of any of claims 1-16.