CN114859211A - Operational amplifier function test system - Google Patents
Operational amplifier function test system Download PDFInfo
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- CN114859211A CN114859211A CN202210462976.5A CN202210462976A CN114859211A CN 114859211 A CN114859211 A CN 114859211A CN 202210462976 A CN202210462976 A CN 202210462976A CN 114859211 A CN114859211 A CN 114859211A
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- 238000012360 testing method Methods 0.000 title claims abstract description 66
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 238000012545 processing Methods 0.000 claims abstract description 4
- 230000003321 amplification Effects 0.000 claims description 15
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 15
- 238000011990 functional testing Methods 0.000 claims description 8
- 238000005259 measurement Methods 0.000 claims description 4
- 230000000630 rising effect Effects 0.000 claims description 3
- 230000008054 signal transmission Effects 0.000 claims description 3
- 230000003068 static effect Effects 0.000 claims description 3
- 101100329719 Schizosaccharomyces pombe (strain 972 / ATCC 24843) ctr5 gene Proteins 0.000 description 13
- 101100329720 Schizosaccharomyces pombe (strain 972 / ATCC 24843) ctr6 gene Proteins 0.000 description 13
- 102100031577 High affinity copper uptake protein 1 Human genes 0.000 description 12
- 101710196315 High affinity copper uptake protein 1 Proteins 0.000 description 12
- 101100111303 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) BCK2 gene Proteins 0.000 description 11
- 101150004012 ctr4 gene Proteins 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 101100329714 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CTR3 gene Proteins 0.000 description 5
- 101000746142 Homo sapiens RNA polymerase-associated protein CTR9 homolog Proteins 0.000 description 3
- 102100039525 RNA polymerase-associated protein CTR9 homolog Human genes 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 101000741435 Homo sapiens Calcitonin receptor Proteins 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 101100102707 Cochliobolus heterostrophus (strain C5 / ATCC 48332 / race O) VOS1 gene Proteins 0.000 description 1
- 102100031145 Probable low affinity copper uptake protein 2 Human genes 0.000 description 1
- 101710095010 Probable low affinity copper uptake protein 2 Proteins 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention discloses a function test system of an operational amplifier, which comprises a double-path ring conveying and placing module, an STS8200 test machine and a DUT board; the dual-path operational amplifier module comprises an auxiliary operational amplifier and a photoelectric switch, the building and switching of a corresponding test peripheral circuit of the tested operational amplifier product are completed by inputting different photoelectric switch control signals and measuring VI sources, the STS8200 tester provides the dual-path operational amplifier module with the required resources such as VI sources, ACS, ACM, QTMU and photoelectric switch control signals, and completes the data processing and result display of various parameter tests of the tested operational amplifier product output from the dual-path operational amplifier module; and interfaces for the STS8200 tester, the two-way transport-amplifier ring module and the tested transport-amplifier product are respectively arranged on the DUT board. The invention is connected in a modularization way, thereby being convenient for quick assembly, replacement and module upgrade; the test of different operational amplifier function test items can be realized by supporting the existing STS8200 tester and controlling the double-path operational amplifier ring module through the programming of the STS8200 tester.
Description
Technical Field
The invention belongs to the technical field of integrated circuit testing, and particularly relates to an operational amplifier function testing system.
Background
The operational amplifier is called an operational amplifier (OPA). And the amplifier circuit can carry out mathematical operation on the signals. The operational amplifier manufactured by adopting the integrated circuit process not only keeps the original characteristics of very high gain and input impedance, but also has the advantages of being exquisite, cheap, flexible to use and the like. The operational amplifier is widely applied to the fields of industrial control, medical equipment, security monitoring equipment, instruments and meters, automotive electronics, smart home, consumer electronics and the like.
The significance and effect of the operational amplifier FT (function test) test are to check whether the product function is problematic, the existing test device is inconvenient to use, and the test parameters are not comprehensive.
Disclosure of Invention
The invention aims to solve the problems and provides an operational amplifier function test system, which is more convenient to construct and use, improves the test working efficiency and has more comprehensive test parameters.
The technical scheme of the invention is realized in such a way.
A functional test system of an operational amplifier is characterized by comprising a double-path amplifier ring module, an STS8200 tester and a DUT board;
the dual-path operational amplifier ring module internally comprises an auxiliary operational amplifier and a photoelectric switch, the external part of the dual-path operational amplifier ring module is provided with an input pin of a tested operational amplifier product, a control signal input pin of the photoelectric switch and a VI source measuring input pin, the building and switching of a test peripheral circuit corresponding to the tested operational amplifier product are completed by inputting different photoelectric switch control signals and VI sources to be measured, and test parameters are output to an STS8200 test machine;
the STS8200 testing machine provides resources such as a VI source, an alternating current signal source, a precise alternating current meter, a four-channel time measuring module, a photoelectric switch control signal and the like required by the double-path operational amplifier module, and completes data processing and result display of various parameter tests of the tested operational amplifier product output from the double-path operational amplifier module;
the DUT board is connected with the sorting machine, a flat cable interface connected with the STS8200 testing machine, a jack connected with a pin of the double-path transport and amplification module and an interface of the tested transport and amplification product are respectively arranged on the DUT board, and a connecting line for mutually realizing signal transmission among the flat cable interface connected with the STS8200 testing machine, the jack connected with the pin of the double-path transport and amplification module and the interface of the tested transport and amplification product is integrated on the DUT board.
Furthermore, the dual-path operational amplifier module supports peripheral circuit building and switching of parameter tests such as input offset voltage VOS, input bias current IB (IBP/IBN), input offset current IOS, open-loop voltage gain AVO, common mode rejection ratio, power supply voltage rejection ratio PSRR, output voltage swing amplitude VOH and VOL, output source current, output leakage current VOH and IOL, power supply current IS, static power consumption PD, rising edge slew rate SR +, falling edge slew rate SR-, gain bandwidth product GBP and the like of the operational amplifier product to be tested.
Furthermore, the dual-path operational amplifier module is suitable for testing different kinds of operational amplifier products, multi-gear programmable loop gain and compensation setting are provided, and the STS8200 tester programs and controls the dual-path operational amplifier module to complete the building and switching of the peripheral circuits of the IC to be tested.
Furthermore, the two-way ring conveying and placing module adopts a 2.54mm double-row pin structure and is spliced with a jack on the DUT board.
Furthermore, 2 64PIN flat cable interfaces are arranged on the DUT board and connected with the STS8200 tester through flat cables.
Furthermore, the DUT board is of a long and narrow structure, and a tested operational amplifier product interface, a double-path operational amplifier ring module pin connection jack and an STS8200 tester cable interface are sequentially arranged from left to right.
The invention has the beneficial effects that: 1. the DUT board is designed to place the tested operational amplifier product, and is connected with the double-path operational amplifier ring module and the STS8200 testing machine, and the modular connection is realized, so that the rapid assembly, the replacement and the module upgrade are facilitated; 2. the test of different operational amplifier function test items can be realized by supporting the existing STS8200 test machine and controlling the double-path operational amplifier ring module through the programming of the STS8200 test machine; 3. the installation is convenient, and the flat cable interface and the pin jack structure are adopted, so that the flat cable interface and the pin jack structure can be directly spliced with a DUT (device under test) board during installation.
Drawings
FIG. 1 is a schematic structural diagram of a test system according to the present invention.
FIG. 2 is a schematic circuit diagram of a specific test item performed by the test system of the present invention.
In the figure, 1, a DUT board, 2, a double-path transport and amplification ring module, 3, an STS8200 tester, 4, a tested transport and amplification product, 11, a tested transport and amplification product interface, 12, a double-path transport and amplification ring module pin connecting jack, and 13, an STS8200 tester flat cable interface.
Detailed Description
The technical solution of the present invention will be further described in detail by the following examples and the drawings attached to the specification.
As shown in fig. 1, an operational amplifier function test system includes a dual-path amplifier ring module 2, an STS8200 tester 3 and a DUT board 1;
the two-way operational amplifier module 2 comprises an auxiliary operational amplifier and a photoelectric switch inside, a tested operational amplifier product input pin, a photoelectric switch control signal input pin and a measurement VI source input pin are arranged outside, the building and switching of a test peripheral circuit corresponding to the tested operational amplifier product are completed by inputting different photoelectric switch control signals and measurement VI sources, and test parameters are output to the STS8200 test machine 3.
The STS8200 tester 3 provides the dual-path operational amplifier module 2 with the needed resources such as VI source, ACS, ACM, QTMU, and photoelectric switch control signal (CTR control bit), and completes data processing and result display of various parameter tests of the operational amplifier product to be tested, which are output from the dual-path operational amplifier module.
The DUT board 1 is connected with the sorting machine, the DUT board is of a long and narrow structure, and a tested transport and amplifier product interface 11 connected with a tested transport and amplifier product 4, a double-path transport and amplifier ring module pin connecting jack 12 spliced with a double-path transport and amplifier ring module, and an STS8200 tester flat cable interface 13 connected with an STS8200 tester 3 are sequentially arranged from left to right. And the DUT board 1 is integrated with a tested operational amplifier product interface 11, a dual-path operational amplifier ring module pin connection jack 12, and a connection line for realizing signal transmission among the STS8200 tester flat cable interfaces 13.
The dual-path operational amplifier ring module 2 supports peripheral circuit building and switching of parameter tests such as input offset voltage VOS, input bias current IB (IBP/IBN), input offset current IOS, open-loop voltage gain AVO, common mode rejection ratio, power supply voltage rejection ratio PSRR, output voltage swing amplitude VOH and VOL, output source current, output leakage current VOH and IOL, power supply current IS, static power consumption PD, rising edge slew rate SR +, falling edge slew rate SR-, gain bandwidth product GBP and the like of an operational amplifier product to be tested.
The double-path transport and amplification module 2 is suitable for testing various transport and amplification products, multi-gear programmable loop gain and compensation setting are provided, and the STS8200 testing machine 3 is programmed to control the double-path transport and amplification module 2 to complete the building and switching of the peripheral circuit of the IC to be tested.
The two-way ring conveying and placing module 2 adopts a 2.54mm double-row pin structure and is inserted into the jack on the DUT board 1.
The DUT board 1 is provided with 2 64PIN flat cable interfaces, and is connected with the STS8200 tester 3 through flat cables.
As shown in the schematic circuit diagram of fig. 2, the functional test system of the present invention can implement a multi-parameter test of the operational amplifier product of the circuit, and the specific test is as follows:
open/Short test: (open short circuit)
1. Each function pin force 100uA current reaches V +, V + =0V, and pin voltage VD + is tested;
2. each function pin force-100 uA current reaches V-, V- =0V, and the pin voltage VD-
B. ICC test: (quiescent Current)
1. At 5V voltage, test ICC closed CTR1, CTR4, CTR5, CTR6, CTR 7V + =2.5V, V- = -2.5V, VCM =0V, test V + current
C. VOS test (input offset voltage)
Closed CTR1, CTR4, CTR5, CTR6, CTR 7V + =0.7V, V- = -0.7V, VOS1= VOUT/Av
Av=(RI+RF)/RIV+=2.5V，V-=-2.5V, VOS2=VOUT/Av
Av=(RI+RF)/RI
D. PSRR test (Power supply voltage rejection ratio)
Closed CTR1, CTR4, CTR5, CTR6, CTR7
V+=0.7V，V-=-0.7V, V1=VOUT/Av
Av=(RI+RF)/RI
V+=3.0V，V-=-2.5V, V2=VOUT/Av
Av=(RI+RF)/RI
PSRR=20*LOG10[ABS(4.1/(V2-V1)]
E. CMRR test (common mode rejection ratio)
Closed CTR2, CTR3, CTR5, CTR6, CTR7
1. V+=2.75V, V-=-2.75V, VCM=+0.75V，VOUT=V3，
2. V+=2.75V, V-=-2.75V, VCM=-2.95V，VOUT=V4，
3. V+=2.75V, V-=-2.75V, VCM=+2.95V，VOUT=V5；
CMRR1:
CMRR1=20*LOG10[ABS(3.7/((V3-V4)/Av))]
CMRR2:
CMRR2=20*LOG10[ABS(5.9/((V4-V5)/Av))]
Av=(RI+RF)/RI
The data were stored for analysis at V3, V4, and V5.
F. IB test (input bias current) [ optional one of resistance method and capacitance method according to tester resources ]
1) Resistance method test
Closed CTR1, CTR4, CTR5, CTR6, CTR7, CTR9, CTR10
V+=2.5V,V-=-2.5V, VOUT=V6
Closed CTR1, CTR4, CTR5, CTR7, CTR9, CTR10
V+=2.5V,V-=-2.5V, VOUT=V7
Closed CTR1, CTR4, CTR6, CTR7, CTR9, CTR10
V+=2.5V,V-=-2.5V, VOUT=V8
IBp:
IBp=(V7-V6)/(Av*R)
IBn:
IBn=(V8-V6)/(Av*R)
Av=(RI+RF)/RI
2) Capacitance method test
Closed CTR1, CTR4, CTR5, CTR6, CTR7, CTR8, CTR11
V+=2.5V,V-=-2.5V, VOUT=V9
CTR6 is open, others remain closed, and after a delay t, VOUT = V10;
closed CTR1, CTR4, CTR5, CTR6, CTR7, CTR8, CTR11
V+=2.5V,V-=-2.5V, VOUT=V11
CTR5 is open, others remain closed, and after a delay t, VOUT = V12;
IBp:
IBp=(V10-V9)*C/(Av*t)
IBn:
IBn=(V12-V11)*C/(Av*t)
Av=(RI+RF)/RI
in order to prevent the capacitor from being filled in the test process, V9-V12 should be kept between (-2.4V to +2.4V)
G. VOHL test
Closed CTR1, CTR3, CTR5, CTR6, CTR7, CTR12
V+=0.7V, V-=-0.7V, VCM=+0.5V，VOH1=VOUT
V+=2.5V, V-=-2.5V, VCM=+0.5V，VOH2=VOUT
Closed CTR1, CTR3, CTR5, CTR6, CTR7, CTR12
V+=0.7V, V-=-0.7V, VCM=-0.5V，VOL1=VOUT
V+=2.5V, V-=-2.5V, VCM=-0.5V，VOL2=VOUT
H. ISC testing
Closed CTR1, CTR3, CTR5, CTR6, CTR7, CTR12
V+=2.5V, V-=-2.5V, VCM=+0.5V，Isource=IOUT
Closed CTR1, CTR3, CTR5, CTR6, CTR7, CTR12
V+=2.5V, V-=-2.5V, VCM=-0.5V，Isink=IOUT。
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (6)
1. A functional test system of an operational amplifier is characterized by comprising a double-path amplifier ring module, an STS8200 tester and a DUT board;
the two-way operational amplifier module comprises an auxiliary operational amplifier and a photoelectric switch, a tested operational amplifier product input pin, a photoelectric switch control signal input pin and a measurement VI source input pin are arranged outside the two-way operational amplifier module, the building and switching of a test peripheral circuit corresponding to the tested operational amplifier product are completed by inputting different photoelectric switch control signals and measurement VI sources, and test parameters are output to an STS8200 tester;
the STS8200 testing machine provides required VI source, ACS, ACM, QTMU and photoelectric switch control signal resources for the double-path operational amplifier module, and completes data processing and result display of various parameter tests of the tested operational amplifier product output from the double-path operational amplifier module;
the DUT board is connected with the sorting machine, a flat cable interface connected with the STS8200 testing machine, a jack connected with a pin of the double-path transport and amplification module and an interface of the tested transport and amplification product are respectively arranged on the DUT board, and a connecting line for mutually realizing signal transmission among the flat cable interface connected with the STS8200 testing machine, the jack connected with the pin of the double-path transport and amplification module and the interface of the tested transport and amplification product is integrated on the DUT board.
2. The operational amplifier functional test system of claim 1, wherein: the dual-path operational amplifier ring module supports peripheral circuit building and switching of parameter tests of input offset voltage VOS, input bias current IB, input offset current IOS, open loop voltage gain AVO, common mode rejection ratio, power supply voltage rejection ratio PSRR, output voltage swing amplitude VOH and VOL, output source current, output leakage current VOH and IOL, power supply current IS, static power consumption PD, rising edge slew rate SR +, falling edge slew rate SR-, gain bandwidth product GBP of an operational amplifier product to be tested.
3. The operational amplifier functional test system of claim 1, wherein: the dual-path operational amplifier module is suitable for testing different kinds of operational amplifier products, multi-gear programmable loop gain and compensation setting are provided, and the STS8200 testing machine is programmed to control the dual-path operational amplifier module to complete the building and switching of the peripheral circuit of the IC to be tested.
4. The operational amplifier functional test system of claim 1, wherein: the two-way ring conveying and placing module adopts a 2.54mm double-row pin structure and is spliced with a jack on the DUT board.
5. The operational amplifier functional test system of claim 1, wherein: and 2 64PIN flat cable interfaces are arranged on the DUT board and are connected with the STS8200 tester through flat cables.
6. The operational amplifier functional test system of claim 1, wherein: the DUT board is of a long and narrow structure, and a tested operational amplifier product interface, a double-path operational amplifier ring module pin connecting jack and an STS8200 tester flat cable interface are sequentially arranged from left to right.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210462976.5A CN114859211A (en) | 2022-04-29 | 2022-04-29 | Operational amplifier function test system |
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| CN202210462976.5A CN114859211A (en) | 2022-04-29 | 2022-04-29 | Operational amplifier function test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117294262A (en) * | 2023-08-15 | 2023-12-26 | 北京思凌科半导体技术有限公司 | Arithmetic circuit and test circuit |
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| CN204964702U (en) * | 2015-10-10 | 2016-01-13 | 北京华峰测控技术有限公司 | Operational amplifier detects compensating network |
| CN209044019U (en) * | 2018-10-16 | 2019-06-28 | 北京华峰测控技术股份有限公司 | A kind of auxiliary OP AMP loop stability circuit promoted when amplifier is tested |
| CN111220901A (en) * | 2020-03-02 | 2020-06-02 | 北京华峰测控技术股份有限公司 | Operational amplifier testing system and method |
| CN212031656U (en) * | 2019-12-20 | 2020-11-27 | 北京自动测试技术研究所 | Operational amplifier test module of integrated circuit test system |
| CN114062900A (en) * | 2021-12-13 | 2022-02-18 | 中国电子科技集团公司第四十七研究所 | Operational amplifier circuit offset voltage testing method |
-
2022
- 2022-04-29 CN CN202210462976.5A patent/CN114859211A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201555931U (en) * | 2009-12-16 | 2010-08-18 | 西安明泰半导体测试有限公司 | Device for testing integrated operational amplifier |
| CN201837645U (en) * | 2010-11-02 | 2011-05-18 | 航天科工防御技术研究试验中心 | Test adapter for operational amplifiers |
| CN202693755U (en) * | 2012-05-08 | 2013-01-23 | 安徽理工大学 | Comprehensive test device for integrated circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117294262A (en) * | 2023-08-15 | 2023-12-26 | 北京思凌科半导体技术有限公司 | Arithmetic circuit and test circuit |
| CN117294262B (en) * | 2023-08-15 | 2024-07-05 | 北京思凌科半导体技术有限公司 | Arithmetic circuit and test circuit |
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