CN114844493A - Time delay driving circuit of dual-drive cascade device - Google Patents
Time delay driving circuit of dual-drive cascade device Download PDFInfo
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- CN114844493A CN114844493A CN202210549174.8A CN202210549174A CN114844493A CN 114844493 A CN114844493 A CN 114844493A CN 202210549174 A CN202210549174 A CN 202210549174A CN 114844493 A CN114844493 A CN 114844493A
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- 239000003990 capacitor Substances 0.000 claims abstract description 64
- 238000007599 discharging Methods 0.000 claims abstract description 6
- 230000005669 field effect Effects 0.000 claims description 61
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 230000009977 dual effect Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to the technical field of time delay driving of a dual-drive cascade device; the invention discloses a time delay driving circuit of a double-drive cascade device, which comprises a power supply circuit for supplying power to a driving circuit, a PWM (pulse-width modulation) input control module for turning off the time delay circuit, a time delay adjusting module, a discharging circuit for controlling the discharging of a lower tube si type MOS (metal oxide semiconductor) tube of the double-drive cascade device and a capacitor charging unit for rapidly supplying voltage to the upper tube GaN type MOS tube; the power supply circuit is connected with the adjusting delay module, the adjusting delay module is connected with the lower pipe si-type MOS pipe, and the PWM input control module is respectively connected with one end of the discharge circuit and the adjusting delay module; the other end of the discharge circuit is connected between the adjusting delay module and the lower pipe Si type MOS pipe, one end of the capacitor charging unit is connected between a power supply capacitor of an upper pipe GaN of the double-drive cascade device and a grid electrode of the upper pipe GaN, and the other end of the capacitor charging unit is grounded.
Description
Technical Field
The invention relates to the field of dual-drive cascade devices, in particular to a delay drive circuit of a dual-drive cascade device.
Background
At present, most of Dual-Drive cascade device circuits (DDC Dual Drive Cascode) are shown in fig. 1, hereinafter referred to as DDC device driving mode, an upper tube GaN is driven by a capacitor Cp negative voltage, and a lower Si tube is directly driven by an input voltage signal. When the start-up duty ratio of the input voltage (voltage range: 0-15V) is relatively small, the charging time of the capacitor Cp is insufficient. At low input voltage levels, the capacitance Cp is not sufficiently negative to turn off the GaN, which can cause the GaN to mis-turn on, thereby damaging the DDC device.
Therefore, improvements and developments in the art are still needed.
Disclosure of Invention
The invention aims to provide a time delay driving circuit of a dual-drive cascade device, and aims to solve the technical problems that when the driving duty ratio of the conventional dual-drive cascade device is small, the charging time of a Cp capacitor is short, and the capacitor charge is not enough to turn off GaN, so that the dual-drive cascade device is damaged.
In order to achieve the purpose, the technical scheme of the invention is as follows: a time delay driving circuit of a double-drive cascade device comprises a power supply circuit for supplying power to a driving circuit, a PWM input control module for turning off the time delay circuit, an adjusting time delay module for adjusting time delay, a discharging circuit for controlling a lower tube si type MOS tube of the double-drive cascade device to discharge and a capacitor charging unit for rapidly providing voltage for an upper tube GaN type MOS tube; the power supply circuit is connected with the adjusting delay module, the adjusting delay module is connected with the lower pipe si-type MOS pipe, and the PWM input control module is respectively connected with one end of the discharge circuit and the adjusting delay module; the other end of the discharge circuit is connected between the adjusting delay module and the lower pipe si type MOS tube, one end of the capacitor charging unit is connected between a power supply capacitor of an upper pipe GaN of the double-drive cascade device and a grid electrode of the upper pipe GaN, and the other end of the capacitor charging unit is grounded.
The delay driving circuit of the double-drive cascade device, wherein the power supply circuit comprises a field effect transistor Q7 and a capacitor C3; the pin 1 of the field-effect transistor Q7 is grounded, the pin 2 of the field-effect transistor Q7 is connected with one end of a capacitor C3, the other end of the capacitor C3 is grounded, and the pin 3 of the field-effect transistor Q7 is connected with a power supply input end.
The delay driving circuit of the double-drive cascade device is characterized in that the PWM input control module comprises a resistor R3 and a diode D5, and the resistor R3 is connected with the diode D5 in parallel; the positive end of the diode D5 inputs a PWM-Input signal; the cathode tube of the diode D5 is connected with the adjusting time delay module through a field effect tube Q6.
The delay driving circuit of the double-drive cascade device is characterized in that the G pole of the field effect transistor Q6 is connected with the cathode of the diode D5, and the D pole and the S pole of the field effect transistor Q6 are respectively connected with the adjusting delay module and the ground.
In the delay driving circuit of the double-drive cascade device, one end of the capacitor C3 is connected with the D pole of the field effect transistor Q6 through the resistor R5.
The delay driving circuit of the dual-drive cascade device comprises a resistor R2, a field-effect transistor Q5, a field-effect transistor Q4, a field-effect transistor Q3, a capacitor C2, a resistor R1 and a resistor R6, wherein a G pole of the field-effect transistor Q5 is connected with a D pole of the field-effect transistor Q6, a D pole of the field-effect transistor Q5 is connected with one end of the capacitor C3 and an S pole of the field-effect transistor Q4 through the resistor R2, the D pole of the field-effect transistor Q5 is also connected with the G pole of the field-effect transistor Q4 and one end of the capacitor C2 respectively, the other end of the capacitor C2 is grounded, the D pole of the field-effect transistor Q3 is connected with the S pole of the field-effect transistor Q4 through the resistor R6 and the resistor R1, the G pole of the field-effect transistor Q4 is connected between the resistor R6 and the resistor R1, and the D pole of the field-effect transistor Q4 is connected with a lower tube si type MOS; the S pole of the field effect transistor Q5 and the S pole of the field effect transistor Q3 are respectively grounded.
The delay driving circuit of the double-drive cascade device comprises a resistor R4 and a diode D6, wherein the cathode of the diode D6 is connected with one end of a resistor R4, the anode of the diode D6 is connected with the D pole of a field effect transistor Q4, and the other end of the resistor R4 is connected with a PWM-Input signal Input end.
The delay driving circuit of the double-drive cascade device is characterized in that the other end of the resistor R4 is also connected with one end of a capacitor Cp for driving an upper tube GaN type MOS tube.
In the delay driving circuit of the dual-drive cascade device, the capacitor charging unit is a diode D3.
The delay driving circuit of the double-drive cascade device is characterized in that the capacitor Cp is connected with the diode D1 in parallel, and the other end of the capacitor Cp is connected with the grid electrode of the upper tube GaN type MOS tube and the anode of the diode D3.
Has the advantages that: according to the invention, through the design of the delay circuit, the lower tube of the dual-drive cascade device is started firstly by connecting the delay circuit with the dual-drive cascade device, so that the lower tube is started after the charging capacitance of the upper tube GaN grid Cp is stable, and the phenomenon of damage caused by the error conduction of the DDC device due to the instable voltage of the upper tube GaN grid at the moment of starting the device is effectively avoided.
Drawings
Fig. 1 is a circuit diagram of a conventional dual drive cascode device.
Fig. 2 is a circuit framework of the present invention.
Figure 3 is a circuit diagram of the present invention in connection with a dual drive cascode device.
In the figure: 1. a power supply circuit; 2. the PWM inputs the control module; 3. a delay adjusting module; 4. a discharge circuit; 5. a capacitor charging unit; 10. double-drive cascade devices.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples.
As shown in fig. 2-3, the invention discloses a delay driving circuit of a dual-drive cascade device, which comprises a power supply circuit 1 for supplying power to the driving circuit, a PWM input control module 2 for turning off the delay circuit, an adjusting delay module 3 for adjusting delay time, a discharging circuit 4 for controlling the discharging of a lower si-type MOS transistor of the dual-drive cascade device 10, and a capacitor charging unit 5 for rapidly supplying voltage to an upper GaN-type MOS transistor; the power supply circuit 1 is connected with an adjusting delay module 3, the adjusting delay module 3 is connected with a lower tube si-type MOS tube, and the PWM input control module 2 is respectively connected with one end of a discharge circuit 4 and the adjusting delay module 3; the other end of the discharge circuit 4 is connected between the adjusting delay module 3 and the lower pipe si type MOS tube, one end of the capacitor charging unit 5 is connected between the power supply capacitor of the upper pipe GaN of the double-drive cascade device 10 and the grid electrode of the upper pipe GaN, and the other end of the capacitor charging unit 5 is grounded.
Preferably, the input voltage of the power supply circuit 1 is 12V to 15V.
According to the invention, the PWM Input control module 2 inputs the PWM _ Input signal to control the turn-off delay circuit, and then the delay module 3 is regulated to regulate the starting time of the tube si type MOS tube under the delay, so that the Cp charging time is prolonged, and the phenomenon of mis-conduction of the GaN tube under the upper tube due to the insufficient Cp charge is avoided.
According to the invention, the tube Si type MOS tube is driven by the input voltage start delay, the charging time of the Cp capacitor is prolonged, and the problem that the DDC device is damaged due to the fact that GaN is turned off due to insufficient Cp capacitor negative pressure, a GaN drain electrode and a source electrode are conducted by mistake is solved.
Specifically, the power supply circuit 1 comprises a field effect transistor Q7 and a capacitor C3; the pin 1 of the field-effect transistor Q7 is grounded, the pin 2 of the field-effect transistor Q7 is connected with one end of a capacitor C3, the other end of the capacitor C3 is grounded, and the pin 3 of the field-effect transistor Q7 is connected with a power supply input end.
Specifically, the PWM input control module 2 includes a resistor R3 and a diode D5, and the resistor R3 is connected in parallel with the diode D5; the positive end of the diode D5 inputs a PWM-Input signal; the cathode tube of the diode D5 is connected to the adjusting delay module 3 through a field effect transistor Q6.
Specifically, the G pole of the field effect transistor Q6 is connected to the cathode of the diode D5, and the D pole and the S pole of the field effect transistor Q6 are respectively connected to the adjusting delay module 3 and the ground.
Specifically, one end of the capacitor C3 is connected to the D-pole of the fet Q6 through the resistor R5.
Specifically, the adjusting delay module 3 includes a resistor R2, a field-effect transistor Q5, a field-effect transistor Q4, a field-effect transistor Q3, a capacitor C2, a resistor R1, and a resistor R6, wherein a G pole of the field-effect transistor Q5 is connected to a D pole of the field-effect transistor Q6, a D pole of the field-effect transistor Q5 is connected to one end of a capacitor C3 and an S pole of the field-effect transistor Q4 through a resistor R2, a D pole of the field-effect transistor Q5 is also connected to a G pole of the field-effect transistor Q4 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, a D pole of the field-effect transistor Q3 is connected to an S pole of the field-effect transistor Q4 through a resistor R6 and a resistor R1, a G pole of the field-effect transistor Q4 is connected between the resistor R6 and the resistor R1, and a D pole of the field-effect transistor Q4 is connected to a si-type MOS transistor; the S pole of the field effect transistor Q5 and the S pole of the field effect transistor Q3 are respectively grounded.
Specifically, the discharge circuit 4 includes a resistor R4 and a diode D6, a cathode of the diode D6 is connected to one end of the resistor R4, an anode of the diode D6 is connected to a D electrode of the field effect transistor Q4, and the other end of the resistor R4 is connected to a PWM-Input signal Input terminal.
Specifically, the other end of the resistor R4 is further connected to one end of a capacitor Cp for driving the upper-tube GaN type MOS transistor.
Specifically, the capacitor charging unit 5 is a diode D3.
Specifically, the capacitor Cp is connected in parallel with the diode D1, and the other end of the capacitor Cp is connected to the gate of the upper tube GaN type MOS transistor and the anode of the diode D3. According to the invention, the PWM Input control module 2 is used for enabling the PWM _ Input signal to be rapidly conducted and turning off the delay circuit; when the PWM _ Input signal is at a high level, the Q6 is driven quickly through the D5, and when the PWM _ Input signal is at a low level, the resistance value of the R3 is set to be large, so that the power-off time of the grid of the Q6 can be reduced.
The adjusting delay module 3 is a circuit for adjusting the driving delay time, and can adjust the conduction delay time of the field effect transistor Q3 and the field effect transistor Q4 through an RC structure, a resistor R2, a resistor R5 and a capacitor C2, and delay the on-time of the gate of the lower tube Si type MOS transistor.
When the PWM _ Input is turned off, the gate of the lower tube Si tube discharges through D6 and R4, so that the Si tube can be turned off.
The function of the capacitor charging unit 5: when the lower tube Si tube delay driving device, the Cp capacitor can achieve the purpose of quick charging.
The working principle of the invention is as follows:
1. when the PWM _ Input is started for the first time by a PWM signal, the diode D5 drives the field effect transistor Q6, the resistor R3 prolongs the driving time of the field effect transistor Q6, the field effect transistor Q6 and the field effect transistor Q5 are conducted, and the capacitor C2 is charged quickly. When the charging time is enough, Q3 is conducted, and Q4 is controlled to be conducted. After the Q4 is conducted, the grid electrode of the lower tube Si tube supplies power, the Si tube is conducted, and the charging time of the capacitor C2 is the delay conducting time of the Si type MOS tube.
2. When the PWM _ Input is at a high level, the gate of the upper tube GaN type MOS transistor quickly establishes a charging loop through the diode D3, and when the PWM _ Input is at a low level, the Cp negative voltage drives the upper tube GaN to turn off.
3. When the PWM _ Input is low for a long time, the gate of the lower tube Si-type MOS transistor discharges through the diode D6 and the resistor R4, turning off the Si-type MOS transistor.
According to the invention, through the design of the delay circuit, the lower tube of the dual-drive cascade device is started firstly by connecting the delay circuit with the dual-drive cascade device, so that the lower tube is started after the charging capacitance of the upper tube GaN grid Cp is stable, and the phenomenon of damage caused by the error conduction of the DDC device due to the instable voltage of the upper tube GaN grid at the moment of starting the device is effectively avoided.
The above is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, modifications or equivalent substitutions of the technical solution of the present invention without inventive work may be made without departing from the scope of the present invention.
Claims (10)
1. A time delay driving circuit of a double-drive cascade device is characterized by comprising a power supply circuit, a PWM input control module, a time delay adjusting module, a discharging circuit and a capacitor charging unit, wherein the power supply circuit is used for supplying power to the driving circuit; the power supply circuit is connected with the adjusting delay module, the adjusting delay module is connected with the lower pipe si-type MOS pipe, and the PWM input control module is respectively connected with one end of the discharge circuit and the adjusting delay module; the other end of the discharge circuit is connected between the adjusting delay module and the lower pipe si type MOS tube, one end of the capacitor charging unit is connected between a power supply capacitor of an upper pipe GaN of the double-drive cascade device and a grid electrode of the upper pipe GaN, and the other end of the capacitor charging unit is grounded.
2. The delay driving circuit of the dual-drive cascade device as claimed in claim 1, wherein the power supply circuit comprises a field effect transistor Q7 and a capacitor C3; the pin 1 of the field-effect transistor Q7 is grounded, the pin 2 of the field-effect transistor Q7 is connected with one end of a capacitor C3, the other end of the capacitor C3 is grounded, and the pin 3 of the field-effect transistor Q7 is connected with a power supply input end.
3. The delay driving circuit of the double-drive cascade device as claimed in claim 2, wherein the PWM input control module comprises a resistor R3 and a diode D5, the resistor R3 is connected in parallel with the diode D5; the positive end of the diode D5 inputs a PWM-Input signal; the cathode tube of the diode D5 is connected with the adjusting time delay module through a field effect tube Q6.
4. The delay driving circuit of a dual-drive cascade device as claimed in claim 3, wherein the G pole of the FET Q6 is connected to the cathode of the diode D5, and the D pole and the S pole of the FET Q6 are respectively connected to the adjusting delay module and the ground.
5. The delay driving circuit of a dual-drive cascade device as claimed in claim 4, wherein one end of the capacitor C3 is connected to the D pole of the FET Q6 through a resistor R5.
6. The delay driving circuit of a dual-drive cascade device according to claim 5, wherein the adjusting delay module comprises a resistor R2, a fet Q5, a fet Q4, a fet Q3, a capacitor C2, a resistor R1 and a resistor R6, a G electrode of the fet Q5 is connected to a D electrode of the fet Q6, a D electrode of the fet Q5 is connected to one end of the capacitor C3 and an S electrode of the fet Q4 through a resistor R2, D electrodes of the fet Q5 are further connected to a G electrode of the fet Q4 and one end of the capacitor C2, respectively, another end of the capacitor C2 is grounded, a D electrode of the fet Q3 is connected to an S electrode of the fet Q4 through a resistor R6 and a resistor R1, a G electrode of the fet Q4 is connected between the resistor R6 and the resistor R1, and a D electrode of the fet Q4 is connected to a lower transistor si; the S pole of the field effect transistor Q5 and the S pole of the field effect transistor Q3 are respectively grounded.
7. The delay driving circuit of a dual-drive cascade device as claimed in claim 6, wherein the discharge circuit comprises a resistor R4 and a diode D6, a cathode of the diode D6 is connected to one end of the resistor R4, an anode of the diode D6 is connected to a D electrode of a field effect transistor Q4, and the other end of the resistor R4 is connected to the PWM-Input signal Input terminal.
8. The delay driving circuit of a dual-drive cascode device as claimed in claim 7, wherein said resistor R4 is further connected to a terminal of a capacitor Cp for driving a top-tube GaN type MOS transistor.
9. The delay driving circuit of a dual-drive cascade device as claimed in claim 7, wherein the capacitor charging unit is a diode D3.
10. The delay driving circuit of a dual-drive cascade device as claimed in claim 9, wherein the capacitor Cp is connected in parallel with the diode D1, and the other end of the capacitor Cp is connected to the gate of the upper tube GaN type MOS transistor and the anode of the diode D3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210549174.8A CN114844493B (en) | 2022-05-20 | 2022-05-20 | Delay driving circuit of dual-drive cascade device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210549174.8A CN114844493B (en) | 2022-05-20 | 2022-05-20 | Delay driving circuit of dual-drive cascade device |
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| CN114844493A true CN114844493A (en) | 2022-08-02 |
| CN114844493B CN114844493B (en) | 2023-07-25 |
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| CN202210549174.8A Active CN114844493B (en) | 2022-05-20 | 2022-05-20 | Delay driving circuit of dual-drive cascade device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115801042A (en) * | 2023-02-09 | 2023-03-14 | 西安集成电路设计专业孵化器有限公司 | Electric digital data transmission chip circuit |
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2022
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| CN115801042A (en) * | 2023-02-09 | 2023-03-14 | 西安集成电路设计专业孵化器有限公司 | Electric digital data transmission chip circuit |
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