CN114844493B - Delay driving circuit of dual-drive cascade device - Google Patents
Delay driving circuit of dual-drive cascade device Download PDFInfo
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- CN114844493B CN114844493B CN202210549174.8A CN202210549174A CN114844493B CN 114844493 B CN114844493 B CN 114844493B CN 202210549174 A CN202210549174 A CN 202210549174A CN 114844493 B CN114844493 B CN 114844493B
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- 239000003990 capacitor Substances 0.000 claims abstract description 64
- 238000007599 discharging Methods 0.000 claims abstract description 15
- 230000005669 field effect Effects 0.000 claims description 78
- 230000009977 dual effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Inverter Devices (AREA)
Abstract
The invention relates to the technical field of delay driving of a double-driving cascade device; the invention discloses a delay driving circuit of a double-drive cascade device, which comprises a power supply circuit for supplying power to the driving circuit, a PWM input control module for switching off the delay circuit, a delay adjusting module, a discharging circuit for controlling the discharging of a lower tube si-type MOS tube of the double-drive cascade device and a capacitor charging unit for rapidly providing voltage for an upper tube GaN-type MOS tube; the power supply circuit is connected with the adjusting delay module, the adjusting delay module is connected with the lower pipe si type MOS tube, and the PWM input control module is respectively connected with one end of the discharging circuit and the adjusting delay module; the other end of the discharging circuit is connected between the adjusting delay module and the lower tube si type MOS tube, one end of the capacitor charging unit is connected between a power supply capacitor of the upper tube GaN of the double-drive cascade device and a grid electrode of the upper tube GaN, and the other end of the capacitor charging unit is grounded.
Description
Technical Field
The invention relates to the field of dual-drive cascade devices, in particular to a delay driving circuit of a dual-drive cascade device.
Background
At present, most of the double-drive cascade device circuits (DDC Dual Drive Cascode) are shown in fig. 1, and are hereinafter referred to as a DDC device driving mode, wherein an upper tube GaN is driven by a capacitor Cp under negative pressure, and a lower Si tube is directly driven by an input voltage signal. When the input voltage (voltage range: 0-15V) has a relatively small start-up duty cycle, the capacitor Cp is charged for an insufficient time. At low input voltage levels, the capacitor Cp negative pressure is insufficient to turn off GaN, which can cause GaN to turn on erroneously, thereby damaging the DDC device.
Accordingly, improvements and developments in the art are still needed.
Disclosure of Invention
The invention aims to provide a delay driving circuit of a dual-drive cascade device, which aims to solve the technical problem that when the driving duty ratio of the existing dual-drive cascade device is smaller, the charging time of a Cp capacitor is shorter, and the capacitor charge is insufficient to turn off GaN, so that the dual-drive cascade device is damaged.
In order to achieve the above purpose, the technical scheme of the invention is as follows: the delay driving circuit of the double-driving cascade device comprises a power supply circuit for supplying power to the driving circuit, a PWM input control module for switching off the delay circuit, an adjustment delay module for adjusting delay time, a discharge circuit for controlling discharge of a lower tube si-type MOS tube of the double-driving cascade device and a capacitor charging unit for rapidly providing voltage for an upper tube GaN-type MOS tube; the power supply circuit is connected with the adjusting delay module, the adjusting delay module is connected with the lower pipe Si type MOS tube, one end of the discharging circuit is connected with the adjusting delay module and the grid electrode of the lower pipe Si type MOS tube, the other end of the discharging circuit is connected with the PWM-Input signal Input end, one end of the capacitor charging unit is connected between the power supply capacitor of the upper pipe GaN of the double-drive cascade device and the grid electrode of the upper pipe GaN, and the other end of the capacitor charging unit is grounded.
The delay driving circuit of the dual-driving cascade device comprises a field effect transistor Q7 and a capacitor C3; the 1 pin of the field effect tube Q7 is grounded, the 2 pin of the field effect tube Q7 is connected with one end of the capacitor C3, the other end of the capacitor C3 is grounded, and the 3 pin of the field effect tube Q7 is connected with the power input end.
The delay driving circuit of the dual-driving cascade device comprises a PWM input control module, a control module and a control module, wherein the PWM input control module comprises a resistor R3 and a diode D5, and the resistor R3 is connected with the diode D5 in parallel; the positive electrode end of the diode D5 is Input with a PWM-Input signal; the negative terminal of the diode D5 is connected with the delay adjusting module through a field effect transistor Q6.
And the G pole of the field effect transistor Q6 is connected with the cathode of the diode D5, and the D pole and the S pole of the field effect transistor Q6 are respectively connected with the delay adjusting module and the grounding.
And one end of the capacitor C3 is connected with the D pole of the field effect transistor Q6 through a resistor R5.
The delay driving circuit of the dual-drive cascade device comprises a resistor R2, a field effect tube Q5, a field effect tube Q4, a field effect tube Q3, a capacitor C2, a resistor R1 and a resistor R6, wherein the G electrode of the field effect tube Q5 is connected with the D electrode of the field effect tube Q6, the D electrode of the field effect tube Q5 is connected with one end of the capacitor C3 and the S electrode of the field effect tube Q4 through the resistor R2, the D electrode of the field effect tube Q5 is also connected with the G electrode of the field effect tube Q3 and one end of the capacitor C2 respectively, the other end of the capacitor C2 is grounded, the D electrode of the field effect tube Q3 is connected with the S electrode of the field effect tube Q4 through the resistor R6 and the resistor R1, the G electrode of the field effect tube Q4 is connected between the resistor R6 and the resistor R1, and the D electrode of the field effect tube Q4 is connected with a lower tube si type MOS tube; the S pole of the field effect transistor Q5 and the S pole of the field effect transistor Q3 are respectively grounded.
The delay driving circuit of the double-driving cascade device comprises a resistor R4 and a diode D6, wherein the cathode of the diode D6 is connected with one end of the resistor R4, the anode of the diode D6 is connected with the D pole of the field effect transistor Q4, and the other end of the resistor R4 is connected with a PWM-Input signal Input end.
And the other end of the resistor R4 is also connected with one end of a capacitor Cp for driving the upper tube GaN type MOS tube.
The delay driving circuit of the dual-driving cascade device is characterized in that the capacitor charging unit is a diode D3.
In the delay driving circuit of the dual-driving cascade device, the capacitor Cp is connected with the diode D1 in parallel, and the other end of the capacitor Cp is connected with the grid electrode of the upper tube GaN type MOS tube and the anode of the diode D3.
The beneficial effects are that: according to the invention, through the design of the delay circuit, the lower tube of the dynamic double-drive cascade device is started, so that after the charging capacitance of the upper tube GaN grid electrode Cp is stable, the lower tube is started, and the phenomenon of damage caused by incorrect conduction of the DDC device due to unstable voltage of the upper tube GaN grid electrode at the moment of starting the machine is effectively avoided.
Drawings
Fig. 1 is a circuit diagram of a conventional dual drive cascode device.
Fig. 2 is a circuit frame of the present invention.
Fig. 3 is a circuit diagram of the present invention connected to a dual drive cascode device.
In the figure: 1. a power supply circuit; 2. a PWM input control module; 3. adjusting a delay module; 4. a discharge circuit; 5. a capacitor charging unit; 10. a dual drive cascode device.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear and clear, the present invention will be further described in detail below with reference to the accompanying drawings and examples.
As shown in fig. 2-3, the invention discloses a delay driving circuit of a dual-driving cascade device, which comprises a power supply circuit 1 for supplying power to the driving circuit, a PWM input control module 2 for switching off the delay circuit, an adjusting delay module 3 for adjusting delay time, a discharging circuit 4 for controlling the discharging of a lower tube si-type MOS tube of the dual-driving cascade device 10, and a capacitor charging unit 5 for rapidly providing voltage to an upper tube GaN-type MOS tube; the power supply circuit 1 is connected with the adjusting delay module 3, the adjusting delay module 3 is connected with the lower pipe Si type MOS tube, one end of the discharging circuit 4 is connected with the adjusting delay module 3 and the grid electrode of the lower pipe Si type MOS tube, the other end of the discharging circuit 4 is connected with the PWM-Input signal Input end, one end of the capacitor charging unit 5 is connected between the power supply capacitor of the upper pipe GaN of the dual-drive cascade device 10 and the grid electrode of the upper pipe GaN, and the other end of the capacitor charging unit 5 is grounded.
Preferably, the input voltage of the power supply circuit 1 is 12V-15V.
According to the invention, the PWM Input control module 2 inputs the PWM_input signal to control the turn-off delay circuit, and then the delay adjustment module 3 is used for adjusting the starting time of the delay tube si-type MOS tube, so that the Cp charging time is prolonged, and the phenomenon that the upper tube GaN is turned on by mistake due to insufficient Cp charge is avoided.
According to the invention, the delay tube Si type MOS tube is started by the input voltage, so that the charging time of the Cp capacitor is prolonged, and the problem that the DDC device (namely a dual-drive cascade device) is damaged due to the fact that the GaN is turned off due to insufficient negative pressure of the Cp capacitor, and the GaN drain and source are erroneously turned on is solved.
Specifically, the power supply circuit 1 includes a field effect transistor Q7 and a capacitor C3; the 1 pin of the field effect tube Q7 is grounded, the 2 pin of the field effect tube Q7 is connected with one end of the capacitor C3, the other end of the capacitor C3 is grounded, and the 3 pin of the field effect tube Q7 is connected with the power input end.
Specifically, the PWM input control module 2 includes a resistor R3 and a diode D5, where the resistor R3 is connected in parallel with the diode D5; the positive electrode end of the diode D5 is Input with a PWM-Input signal; the negative terminal of the diode D5 is connected with the adjusting delay module 3 through a field effect transistor Q6.
Specifically, the G pole of the field effect transistor Q6 is connected to the negative pole of the diode D5, and the D pole and the S pole of the field effect transistor Q6 are respectively connected to the delay adjustment module 3 and the ground.
Specifically, one end of the capacitor C3 is connected to the D pole of the field effect transistor Q6 through the resistor R5.
Specifically, the delay adjusting module 3 includes a resistor R2, a field effect tube Q5, a field effect tube Q4, a field effect tube Q3, a capacitor C2, a resistor R1 and a resistor R6, wherein the G pole of the field effect tube Q5 is connected with the D pole of the field effect tube Q6, the D pole of the field effect tube Q5 is connected with one end of the capacitor C3 and the S pole of the field effect tube Q4 through the resistor R2, the D pole of the field effect tube Q5 is also connected with the G pole of the field effect tube Q3 and one end of the capacitor C2 respectively, the other end of the capacitor C2 is grounded, the D pole of the field effect tube Q3 is connected with the S pole of the field effect tube Q4 through the resistor R6 and the resistor R1, the G pole of the field effect tube Q4 is connected between the resistor R6 and the resistor R1, and the D pole of the field effect tube Q4 is connected with a si-type MOS tube; the S pole of the field effect transistor Q5 and the S pole of the field effect transistor Q3 are respectively grounded.
Specifically, the discharging circuit 4 includes a resistor R4 and a diode D6, wherein a cathode of the diode D6 is connected with one end of the resistor R4, an anode of the diode D6 is connected with a D pole of the field effect transistor Q4, and the other end of the resistor R4 is connected with a PWM-Input signal Input end.
Specifically, the other end of the resistor R4 is further connected to one end of the capacitor Cp for driving the upper tube GaN type MOS tube.
Specifically, the capacitor charging unit 5 is a diode D3.
Specifically, the capacitor Cp is connected in parallel with the diode D1, and the other end of the capacitor Cp is connected to the gate of the upper tube GaN type MOS tube and the anode of the diode D3. The PWM Input control module 2 is used for enabling the PWM_input signal to be rapidly conducted and switching off the delay circuit; when the PWM_input signal is in a high level, the Q6 is quickly driven by the D5, and when the PWM_input signal is in a low level, the R3 resistance value is set to be larger, so that the power-down time of the grid electrode of the Q6 can be slowed down.
The adjusting delay module 3 is an adjusting driving delay time circuit, and can adjust the on delay time of the field effect transistor Q3 and the field effect transistor Q4 through the RC structure, the resistor R2, the resistor R5 and the capacitor C2, and delay the opening time of the grid electrode of the lower tube Si type MOS tube.
And when the PWM_input is turned off, the discharging circuit 4 discharges the grid electrode of the lower tube Si tube through D6 and R4, so that the Si tube can be turned off.
The function of the capacitor charging unit 5: when the Si tube of the lower tube delays the driving device, the Cp capacitor can be charged rapidly.
The working principle of the invention is as follows:
1. when the PWM_input has the PWM signal for the first time, the diode D5 drives the field effect transistor Q6, the resistor R3 prolongs the driving time of the field effect transistor Q6, the field effect transistor Q6 and the field effect transistor Q5 are conducted, and the capacitor C2 is charged rapidly. When the charging time is enough, Q3 is conducted, and Q4 is controlled to be conducted. And after the Q4 is conducted, the grid electrode of the lower tube Si tube is powered, the Si tube is conducted, and the charging time of the capacitor C2 is the time delay conduction time of the Si-type MOS tube.
2. When the PWM_input is high, the grid electrode of the upper tube GaN MOS tube rapidly establishes a charging loop through the diode D3, and when the PWM_input is low, the Cp negative pressure drives the upper tube GaN to be closed.
3. When the PWM_input is low for a long time, the grid electrode of the lower tube Si type MOS tube discharges through the diode D6 and the resistor R4 to close the Si type MOS tube.
According to the invention, through the design of the delay circuit, the lower tube of the dynamic double-drive cascade device is started, so that after the charging capacitance of the upper tube GaN grid electrode Cp is stable, the lower tube is started, and the phenomenon of damage caused by incorrect conduction of the DDC device due to unstable voltage of the upper tube GaN grid electrode at the moment of starting the machine is effectively avoided.
The foregoing is illustrative of the preferred embodiments of the present invention, and it is not intended to limit the scope of the claims herein, but it should be noted that modifications and equivalents of the inventive arrangements can be made by those skilled in the art without departing from the scope of the invention.
Claims (5)
1. The delay driving circuit of the double-driving cascade device is characterized by comprising a power supply circuit for supplying power to the driving circuit, a PWM input control module for switching off the delay circuit, an adjustment delay module for adjusting delay time, a discharge circuit for controlling the discharge of a lower tube si-type MOS tube of the double-driving cascade device and a capacitor charging unit for rapidly providing voltage for an upper tube GaN-type MOS tube;
the power supply circuit is connected with the adjusting delay module, the adjusting delay module is connected with the lower tube Si-type MOS tube, one end of the discharging circuit is connected with the adjusting delay module and the grid electrode of the lower tube Si-type MOS tube, the other end of the discharging circuit is connected with the PWM-Input signal Input end, one end of the capacitor charging unit is connected between the power supply capacitor of the upper tube GaN of the double-drive cascade device and the grid electrode of the upper tube GaN, and the other end of the capacitor charging unit is grounded;
the power supply circuit comprises a field effect transistor Q7 and a capacitor C3; the 1 pin of the field effect tube Q7 is grounded, the 2 pin of the field effect tube Q7 is connected with one end of the capacitor C3, the other end of the capacitor C3 is grounded, and the 3 pin of the field effect tube Q7 is connected with the power input end;
the PWM input control module comprises a resistor R3 and a diode D5, and the resistor R3 is connected with the diode D5 in parallel; the positive electrode end of the diode D5 is Input with a PWM-Input signal; the negative end of the diode D5 is connected with the delay adjusting module through a field effect transistor Q6;
the G pole of the field effect tube Q6 is connected with the cathode of the diode D5, and the D pole and the S pole of the field effect tube Q6 are respectively connected with the adjusting delay module and the grounding;
one end of the capacitor C3 is connected with the D pole of the field effect transistor Q6 through a resistor R5;
the adjusting delay module comprises a resistor R2, a field effect tube Q5, a field effect tube Q4, a field effect tube Q3, a capacitor C2, a resistor R1 and a resistor R6, wherein the G electrode of the field effect tube Q5 is connected with the D electrode of the field effect tube Q6, the D electrode of the field effect tube Q5 is connected with one end of the capacitor C3 and the S electrode of the field effect tube Q4 through the resistor R2, the D electrode of the field effect tube Q5 is also respectively connected with the G electrode of the field effect tube Q3 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, the D electrode of the field effect tube Q3 is connected with the S electrode of the field effect tube Q4 through the resistor R6 and the resistor R1, and the G electrode of the field effect tube Q4 is connected between the resistor R6 and the resistor R1, and the D electrode of the field effect tube Q4 is connected with a lower tube si type MOS tube; the S pole of the field effect transistor Q5 and the S pole of the field effect transistor Q3 are respectively grounded.
2. The delay driving circuit of the dual-driving cascade device according to claim 1, wherein the discharging circuit comprises a resistor R4 and a diode D6, a cathode of the diode D6 is connected with one end of the resistor R4, an anode of the diode D6 is connected with a D pole of the field effect transistor Q4, and the other end of the resistor R4 is connected with a PWM-Input signal Input terminal.
3. The delay driving circuit of the dual-driving cascade device according to claim 2, wherein the other end of the resistor R4 is further connected to one end of a capacitor Cp for driving the upper tube GaN type MOS tube.
4. A delay drive circuit of a dual drive cascode device according to claim 3, wherein said capacitive charging unit is a diode D3.
5. The delay driving circuit of the dual driving cascade device according to claim 4, wherein the capacitor Cp is connected in parallel with the diode D1, and the other end of the capacitor Cp is connected to the gate of the upper tube GaN type MOS transistor and the anode of the diode D3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210549174.8A CN114844493B (en) | 2022-05-20 | 2022-05-20 | Delay driving circuit of dual-drive cascade device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210549174.8A CN114844493B (en) | 2022-05-20 | 2022-05-20 | Delay driving circuit of dual-drive cascade device |
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| Publication Number | Publication Date |
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| CN114844493A CN114844493A (en) | 2022-08-02 |
| CN114844493B true CN114844493B (en) | 2023-07-25 |
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| CN115801042A (en) * | 2023-02-09 | 2023-03-14 | 西安集成电路设计专业孵化器有限公司 | Electric digital data transmission chip circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN213817709U (en) * | 2020-11-23 | 2021-07-27 | 广东交通职业技术学院 | High-power IGBT drive control circuit |
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| JP5200140B2 (en) * | 2010-10-18 | 2013-05-15 | シャープ株式会社 | Driver circuit |
| US9083343B1 (en) * | 2014-05-28 | 2015-07-14 | United Silicon Carbide, Inc. | Cascode switching circuit |
| JP6483997B2 (en) * | 2014-10-10 | 2019-03-13 | ローム株式会社 | Power semiconductor drive circuit, power semiconductor circuit, and power module circuit device |
| JP6356718B2 (en) * | 2016-03-14 | 2018-07-11 | 株式会社東芝 | Semiconductor device |
| US10348293B2 (en) * | 2017-06-19 | 2019-07-09 | Psemi Corporation | Timing controller for dead-time control |
| CN111478564B (en) * | 2020-03-31 | 2021-09-03 | 深圳芯能半导体技术有限公司 | Driving circuit of depletion transistor |
| CN111404529B (en) * | 2020-04-03 | 2023-04-25 | 电子科技大学 | Segmented direct gate driving circuit of depletion type GaN power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN213817709U (en) * | 2020-11-23 | 2021-07-27 | 广东交通职业技术学院 | High-power IGBT drive control circuit |
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