CN114823700A - Three-dimensional memory, preparation method thereof, storage system and electronic equipment - Google Patents

Abstract

The application provides a three-dimensional memory, a preparation method of the three-dimensional memory, a storage system and electronic equipment. The preparation method of the three-dimensional memory comprises the following steps: forming a stacked structure including a plurality of stacked layers, and forming a plurality of step steps in the stacked structure; forming a dielectric layer covering the step, and forming a top selection gate notch vertical to the lamination surface of the lamination structure in the dielectric layer; forming a virtual channel hole penetrating through the dielectric layer and the step; and filling the top select gate notch and the virtual channel hole with an insulating material to form a top select gate structure and a virtual channel structure respectively, wherein the virtual channel hole comprises a first virtual channel hole, a projection of the first virtual channel hole on the lamination surface and a projection of the top select gate notch on the lamination surface have an overlapping region, and an extension length of the overlapping region in a first direction parallel to the top select gate notch is smaller than a maximum opening size of the first virtual channel hole in the first direction parallel to the first direction.

Description

Three-dimensional memory, preparation method thereof, storage system and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional memory, a method for manufacturing the same, a memory system, and an electronic device.

Background

With the demand for high storage density and large storage capacity of the memory, a three-dimensional memory (e.g., a 3D NAND memory) has come. In some examples, a three-dimensional memory includes a core region and a staircase region. The core region may be used to form memory cells stacked in a vertical direction and the staircase region may be used to form a power-on channel for a word line leading out of the memory cell.

In addition, a top select gate structure and a dummy channel structure may be formed in the stepped region. However, due to the spatial relationship between the top select gate cut and the dummy channel hole and the sequence of the fabrication process, over-etching (under etch) of the dummy channel hole may be caused, thereby affecting the topography of the dummy channel structure.

Disclosure of Invention

The application provides a preparation method of a three-dimensional memory, which comprises the following steps: forming a laminated structure including a plurality of stacked layers and forming a plurality of stepped steps in the laminated structure; forming a dielectric layer covering the step, and forming a top selection gate notch which is vertical to the lamination surface of the lamination structure in the dielectric layer; forming a virtual channel hole penetrating through the dielectric layer and the step; and filling the top select gate cuts and the virtual channel holes with an insulating material to form top select gate structures and virtual channel structures, respectively, wherein the virtual channel holes comprise first virtual channel holes, a projection of the first virtual channel holes on the lamination surface and a projection of the top select gate cuts on the lamination surface have an overlapping region, and an extension length of the overlapping region in a first direction parallel to the top select gate cuts is smaller than a maximum opening size of the first virtual channel holes in the first direction parallel to the first direction.

In one embodiment, the overlap region extends in a second direction perpendicular to the top select gate cutout by a length equal to a width of the top select gate cutout.

In one embodiment, the method further comprises: and forming a contact hole which penetrates through the dielectric layer and extends to the step.

In one embodiment, the virtual channel hole further comprises: the second virtual channel hole, forming a virtual channel hole penetrating through the dielectric layer and the step, includes: the second virtual channel hole and the first virtual channel hole are formed along at least two sides of the contact hole.

In one embodiment, the second virtual channel hole and the first virtual channel hole formed at least at both sides of each of the contact holes have a triangular structure.

In one embodiment, forming a dummy trench hole through the dielectric layer and the step includes: forming a patterned etching mask layer on the top surface of the dielectric layer; and etching the dielectric layer and the step by using the patterned etching mask layer as a mask to form the first virtual channel hole and the second virtual channel hole.

In one embodiment, forming a patterned etch mask layer on a top surface of the dielectric layer comprises: forming an etching mask layer on the top surface of the dielectric layer; and forming a first virtual channel hole pattern and a second virtual channel hole pattern in the etching mask layer to form the patterned etching mask layer, and etching the dielectric layer and the step by using the patterned etching mask layer as a mask comprises: etching the dielectric layer and the step through the first virtual channel hole pattern and the second virtual channel hole pattern, wherein the extension length of a preset overlapping area of the first virtual channel hole pattern and the top selection gate notch in the first direction is smaller than the maximum size of the first virtual channel hole pattern in the first direction, and the extension length of the preset overlapping area in a second direction perpendicular to the top selection gate notch is equal to the width of the top selection gate notch.

In one embodiment, the stacked structure is divided into a step region including the stepped step, and a core region adjacent to the step region, the method further comprising: forming the top select gate cutout in the core region perpendicular to a lamination plane of the laminated structure.

Another aspect of the present application provides a three-dimensional memory, including: a laminated structure including a plurality of stacked layers, the laminated structure having a stepped step formed therein; the dielectric layer covers the step steps; the top selection gate structure is positioned in the dielectric layer and is vertical to the laminated surface of the laminated structure; and a dummy channel structure penetrating through the dielectric layer and the step and including a first dummy channel structure, at least a portion of the first dummy channel structure overlapping the top select gate structure, wherein an extension length of the at least a portion in a first direction parallel to the top select gate structure is smaller than a maximum opening size of the first dummy channel structure in the first direction.

In one embodiment, the at least one portion extends in a second direction perpendicular to the top select gate structure by a length equal to a width of the top select gate structure.

In one embodiment, the three-dimensional memory further comprises: and the contact structure penetrates through the dielectric layer and extends to the step.

In one embodiment, the dummy channel structure further comprises: a second dummy channel structure, the second dummy channel structure and the first dummy channel structure being located at least at both sides of the contact structure.

In one embodiment, at least the second dummy channel structure and the first dummy channel structure at both sides of each of the contact structures have a triangular structure.

In one embodiment, the stacked structure is divided into a step region including the step, and a core region adjacent to the step region, and the three-dimensional memory further includes: the top select gate structure is located in the core region and perpendicular to the lamination surface of the lamination structure.

Another aspect of the present application provides a storage system. The storage system comprises a controller and the three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used for controlling the three-dimensional memory to store data.

Another aspect of the present application provides an electronic device, including: the storage system is provided.

The three-dimensional memory and the preparation method thereof provided according to one or more embodiments of the present application may have at least one of the following advantages:

1) the virtual channel hole is further formed after the top selection gate notch is formed, so that the top selection gate notch and the virtual channel hole can be simultaneously filled in the same subsequent process step, the process steps are reduced, and the production cost is reduced;

2) the extension length of the overlapping area in the first direction parallel to the top selection gate notch is set to be smaller than the maximum opening size of the first virtual channel hole in the first direction, so that the overlapping area of the first virtual channel hole and the top selection gate notch can be reduced, the phenomenon that the first virtual channel hole expands along the first direction in the etching process can be reduced, and the risk that the first virtual channel hole is over-etched along the first direction can be prevented; and

3) the extension length of the overlapping area in the first direction parallel to the top selection gate notch is set to be smaller than the maximum opening size of the first virtual channel hole in the first direction, so that the pattern morphology of the first virtual channel hole is optimized.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings. Wherein:

fig. 1 is a flowchart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application;

fig. 2 to 5 are process step diagrams of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 6 is a schematic top view after forming a top select gate cut and a dummy trench hole in a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 7 is an enlarged schematic view of a first virtual channel hole according to an exemplary embodiment of the present application;

fig. 8 is a schematic structural view after forming a top select gate cut and a dummy channel hole in a method of fabricating a three-dimensional memory according to the related art;

FIG. 9 is a schematic diagram of a pattern of a patterned etch mask layer according to an example embodiment of the present application;

fig. 10A and 10B are process step diagrams of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 11 is a schematic diagram of a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 12 is a schematic structural diagram of a storage system according to an embodiment of the present application; and

fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first direction discussed in this application may also be referred to as a second direction, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately," "about," and the like are used as table approximation terms, not as table degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes a region having a height. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying or overlying structure or can have a smaller extent than the underlying or overlying structure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a height less than the height of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, above, and/or below. The layer can comprise a plurality of layers.

Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an exemplary embodiment of the present application.

As shown in fig. 1, a method 1000 for manufacturing a three-dimensional memory provided by the present application may include: s1, forming a laminated structure comprising a plurality of stacked layers, and forming a plurality of step steps in the laminated structure; s2, forming a dielectric layer covering the step, and forming a top selection gate notch vertical to the lamination surface of the lamination structure in the dielectric layer; s3, forming a virtual channel hole penetrating through the dielectric layer and the step; and S4 filling the top select gate cuts and the dummy channel holes with an insulating material to form a top select gate structure and a dummy channel structure, respectively, wherein the dummy channel holes include first dummy channel holes, a projection of the first dummy channel holes on the lamination plane and a projection of the top select gate cuts on the lamination plane have an overlapping region, and an extension of the overlapping region in a first direction parallel to the top select gate cuts is smaller than a maximum opening size of the first dummy channel holes in the first direction parallel to the first direction. The steps S1 to S4 will be described in detail below.

Step S1

As shown in fig. 2, a stacked structure 100 including a plurality of stacked layers may be formed, and a plurality of step steps 200 may be formed in the stacked structure 100. Illustratively, a stacked structure 100 including a plurality of stacked layers may be formed at one side of a substrate (not shown), and a plurality of step steps 200 may be formed in the stacked structure 100. Specifically, the insulating layer 110 and the sacrificial layer 120 may be alternately stacked on one side of the substrate to form the stacked-layer structure 100. Illustratively, the plurality of step steps 200 may be formed at an edge region or a middle region of the stack structure 100. Illustratively, each of the step steps 200 may be formed of a plurality of stacked layers (i.e., a plurality of alternately stacked insulating layers 110 and sacrificial layers 120). Of course, in another exemplary embodiment, each step 200 may also be formed of one stacked layer (i.e., the adjacent insulating layer 110 and the sacrificial layer 120). It should be understood that the specific thickness of each step 200 depends on the requirement of the number of word lines that need to be controlled for each step 200 in the actual process. Exemplarily, a region of the stacked structure 100 corresponding to the plurality of step steps 200 is referred to as a step region, which may be used to arrange a word line connection structure. The region of the stacked structure 100 corresponding to the plurality of channel structures is referred to as a core region (not shown), which may be used to form an array memory cell string.

In exemplary embodiments of the present application, the substrate (not shown) may be, for example, a polycrystalline silicon substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like. In one embodiment, the substrate may also be a stacked structure, such as Si/SiGe or the like. In further embodiments, the substrate may also be other epitaxial structures, such as Silicon Germanium On Insulator (SGOI) or the like.

In an exemplary embodiment of the present application, forming the stacked structure 100 on a substrate may be accomplished by one or more deposition processes. The deposition process to form the stacked structure 100 includes, but is not limited to, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof. It is understood that the number and thickness of the insulating layer 110 and the sacrificial layer 120 are not limited to those shown in fig. 2, and those skilled in the art may provide any number and thickness of the insulating layer 110 and the sacrificial layer 120 as needed without departing from the concept of the present application. In addition, the materials of the insulating layer 110 and the sacrificial layer 120 may be selected from suitable materials known in the art. For example, the insulating layer 110 may be an oxide layer (such as silicon oxide) and the sacrificial layer 120 may be a nitride layer (such as silicon nitride).

Illustratively, forming the plurality of step steps 200 in the stacked structure 100 may include: the stacked structure 100 may be first subjected to a repeated etch-trim process by using a patterned mask (not shown) to form a plurality of step steps 200 in a step region. The patterned mask may include a photoresist or a carbon-based polymer material, and may be removed after the step is formed.

Step S2

As shown in fig. 2, a dielectric layer 300 may be formed overlying the step 200. In addition, as shown in FIG. 3, a top select gate cut 400 may be formed in dielectric layer 300 perpendicular to the lamination plane (X-Y plane) of laminated structure 100. Illustratively, the dielectric layer 300 covering the step 200 may be formed using Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof. Illustratively, top select gate cutouts 400 may be formed in the dielectric layer 300 perpendicular to the stacking plane (X-Y plane) of the stacked structure 100 by an etching process, i.e., the top select gate cutouts 400 may be disposed in a direction Z perpendicular to the stacking plane (X-Y plane) of the stacked structure 100. Illustratively, the top select gate cutout 400 may extend in a direction X parallel to the lamination plane (X-Y plane) of the laminated structure 100.

In an exemplary embodiment of the present application, the stacked structure 100 may be divided into a stepped region including a stepped step, and a core region adjacent to the stepped region. Illustratively, a top select gate cut 400 in a direction Z perpendicular to the lamination plane (X-Y plane) of the laminated structure 100 may be formed in the core region. Illustratively, there may be a spacing between at least two top select gate cutouts 400. At least two top select gate cutouts 400 may be formed in the same process step, i.e., at least two top select gate cutouts 400 may share the same reticle. The top select gate cut 400 may divide the block storage area in the three-dimensional memory into finger storage areas F (fig. 6). It should be understood that the number of stair-steps 200, the thickness of the dielectric layer penetrated by the top select gate cut 400 in the stair-step region, and the number of stacked layers penetrated by the top select gate cut 400 in the core region are not specifically limited by the present application, and the number of stair-steps 200, the thickness of the dielectric layer penetrated by the top select gate cut 400, and the number of stacked layers penetrated by the top select gate cut 400 may be adjusted as desired, depending on the need for the number of smaller memory cells in the three-dimensional memory.

In an exemplary embodiment of the present application, the dielectric layer 300 may be formed on the top surface and sidewalls of the step 200 by depositing an oxide, which may be selected from, for example, a silicon oxide-based material. Dielectric layer 300 may be formed from a TEOS based silicon oxide fill. Illustratively, the dielectric layer 300 may be a multi-layer structure, and a first sub-film layer with good step coverage is formed first, such as a silicon oxide (SiO) layer deposited by High Density Plasma (HDP) ₂ ) Or Atomic Layer Deposited (ALD) silicon oxide, or the like; then, a second sub-film layer with high filling efficiency is formed, and the second sub-film layer can be TEOS-based silicon oxide (TESO-based SiO), for example ₂ ) And the like. In an exemplary embodiment, the density of the first sub-film layer is higher than that of the second sub-film layer, whereby the first sub-film layer has good step coverage and the second sub-film layer has high filling efficiency. As an example, the formed dielectric layer 300 may be planarized by a chemical mechanical polishing process, such that the dielectric layer 300 provides a substantially flat upper surface for the step region of the stacked structure 100.

In an exemplary embodiment of the present application, the top select gate cutouts 400 may be formed using, for example, a dry or wet etching process. Illustratively, for the sake of brevity and clarity of the present application, only one top select gate cut 400 in the mesa region and one top select gate cut 400 in the core region will be described as examples. It should be understood that the number of top select gate cutouts is not specifically limited by the present application and may be adjusted as desired, depending on the need for a smaller number of memory cells in a three-dimensional memory.

Step S3

As shown in fig. 5, a dummy trench hole 500 may be formed through the dielectric layer 300 and the step 200. Illustratively, the dummy trench hole 500 may be formed through the dielectric layer 300 and the step 200 by, for example, a dry etching process. It is understood that the dummy channel structure formed by the dummy channel hole 500 may serve as a support to prevent the overall structure from collapsing after the sacrificial layer 120 is subsequently removed or after the contact hole 600 is formed.

In an exemplary embodiment of the present application, forming the dummy trench hole 500 penetrating the dielectric layer 300 and the step 200 may include: first, as shown in fig. 4, a patterned etching mask layer 700 is formed on the top surface of the dielectric layer 300; then, the dielectric layer 300 and the step 200 are etched using the patterned etch mask layer 700 as a mask to form a dummy channel hole 500. Specifically, the dielectric layer 300 and the step 200 may be etched using the patterned etch mask layer 700 as a mask to form a dummy trench hole 500 through the dielectric layer 300 and the step 200.

Step S4

The top select gate cutouts 400 and the dummy channel holes 500 may be filled with an insulating material to form a top select gate structure 800 and a dummy channel structure 900, respectively. Illustratively, as shown in fig. 10A and 10B, the top select gate cutouts 400 and the dummy channel holes 500 may be filled with an insulating material to form a top select gate structure 800 (fig. 10B) and a dummy channel structure 900, respectively. Illustratively, the insulating material may comprise silicon oxide, silicon oxynitride, silicon nitride, TEOS, or any suitable insulating material such as silicon oxide doped with fluorine, carbon, nitrogen, and/or hydrogen. It is understood that the plurality of top select gate structures 800 may have a spacing therebetween. The top select gate structure 800 may divide a block storage area in a three-dimensional memory into a finger storage area F.

In an exemplary embodiment of the present application, a contact hole 600 (fig. 6) penetrating the dielectric layer 300 and extending to the step 200 may also be formed. Illustratively, the plurality of contact holes 600 may be first formed in the stepped region through a photolithography and etching process. Then, the contact hole 600 may be filled with a conductive material such as a tungsten alloy to form a contact structure. The contact structure can be electrically connected with a subsequently formed gate, so that gate current is led out. Specifically, the contact structure is in contact with the subsequently formed gate so that an electrical signal can be supplied to or transmitted from the subsequently formed gate.

In an exemplary embodiment of the present application, a schematic top view of top select gate cut 400, dummy channel hole 500, and contact hole 600 is shown in FIG. 6. Illustratively, the dummy channel hole 500 may include a first dummy channel hole 510, and a projection of the first dummy channel hole 510 on the lamination plane (X-Y plane) has an overlap area 511 with a projection of the top select gate slit 400 on the lamination plane (X-Y plane).

Illustratively, the first virtual channel hole 510 may include a primary supporting virtual channel hole 510' and a secondary supporting virtual channel hole 510 ″. The main supporting virtual channel hole 510' may be located near the contact hole 600, compared to the auxiliary supporting virtual channel hole 510 ″ being located farther away from the contact hole 600. The dummy channel structure formed by the main supporting dummy channel holes 510' and the auxiliary supporting dummy channel holes 510 ″ may play a role of supporting to prevent the overall structure from collapsing after the contact holes 600 are formed. Illustratively, the main support virtual channel hole 510' and the auxiliary support virtual channel hole 510 ″ may have substantially the same structure in the second direction D2 (i.e., parallel to the Y direction) perpendicular to the extending direction X of the top select gate slit 400, and the maximum opening size in the first direction D1 parallel to the extending direction X of the top select gate slit 400 may have a certain difference. For example, the maximum opening dimension 513 of the primary support virtual channel hole 510 'in the first direction D1 may be approximately 270 angstroms and the maximum opening dimension 513' of the secondary support virtual channel hole 510 "in the first direction D1 may be approximately 180 angstroms. In other words, the maximum opening dimension 513 of the primary support virtual channel hole 510 'disposed proximate to the contact hole 600 may be greater than the maximum opening dimension 513' of the secondary support virtual channel hole 510 ″ disposed distal to the contact hole 600. Thus, the dummy channel structure formed by the main supporting dummy channel holes 510' has a better supporting effect, and collapse or deformation of the structure near the contact hole 600 can be better reduced when the contact hole 600 is formed.

An enlarged schematic view of the main support virtual channel holes 510' is shown in fig. 7. An extension length 512 of an overlapping region 511 of the main support virtual channel hole 510 'and the top select gate slit 400 in a first direction D1 parallel to an extension direction of the top select gate slit 400 may be less than a maximum opening dimension 513 of the main support virtual channel hole 510' in the first direction D1. Similarly, the extension length of the overlapping region of the auxiliary support virtual channel hole 510 ″ and the top select gate slit 400 in the first direction D1 parallel to the extension direction of the top select gate slit 400 may be less than the maximum opening size 513' of the auxiliary support virtual channel hole 510 ″ in the first direction D1.

In a conventional process, during a process of forming the first virtual channel hole 510 after forming the top select gate cutout 400, there is generally an overlapping area of the projections of the top select gate cutout 400 and the first virtual channel hole 510 on the lamination plane (X-Y plane). During the process of forming the first virtual channel hole 510 and gradually increasing the cross-sectional size and the extension length thereof, the etching material (e.g., etching gas) may over-etch the first virtual channel hole 510 along a direction parallel to the extension direction of the top select gate slit 400 (e.g., the first direction D1 shown in fig. 8) through the top select gate slit 400, so that the finally formed first virtual channel hole 510 has a sharp corner along the first direction D1 (refer to fig. 8), thereby affecting the pattern profile of the first virtual channel hole 510. In addition, the spacing distance of the adjacent first virtual channel holes 510 in the first direction D1 is also decreased. However, in the present application, by setting the first dimension 512 to be smaller than the maximum opening dimension 513 during the process of forming the first virtual channel hole 510 after forming the top select gate cut 400, it is possible to prevent the overlap region 511 from being laterally expanded or even over-etched due to two etching processes.

In an exemplary embodiment of the present application, as shown in fig. 7, an extension length 514 of the overlap region 511 in a second direction D2 perpendicular to an extension direction of the top select gate cutout 400 may be approximately equal to a width of the top select gate cutout 400. In an actual process, the first dummy channel hole 510 has less risk of generating over-etching in the second direction D2. Accordingly, the present application sets the extension length 514 of the overlap region 511 in the second direction D2 to be approximately equal to the width of the top select gate notch 400, so that the first dummy channel structure formed by the first dummy channel hole 510 can be better supported to prevent the overall structure from collapsing after the sacrificial layer 120 is subsequently removed or the contact hole 600 is formed.

In an exemplary embodiment of the present application, the dummy channel hole 500 may further include a second dummy channel hole 520 (fig. 6). The second dummy channel hole 520 and the first dummy channel hole 510 may be located at least at both sides of the contact hole 600. Illustratively, the second virtual channel hole 520 and the main supporting virtual channel hole 510' may be disposed in a circumferential direction of the contact hole 600. For example, the second virtual channel hole 520 and the main supporting virtual channel hole 510' may collectively surround the contact hole 600. The second virtual channel hole 520 and the main supporting virtual channel hole 510' disposed at least at both sides of each contact hole 600 may have a triangular structure. As shown in fig. 6, two adjacent second virtual channel holes 520 and one main supporting virtual channel hole 510' may together surround the contact hole 600. Each contact hole 600 is surrounded by three virtual channel holes so that the main supporting virtual channel hole 510' and the second virtual channel hole 520 can play a supporting role and prevent the electric wiring in the vicinity of the contact hole 600 from being bent when an external force is applied beyond a permissible range. In other embodiments, each contact hole 600 may be surrounded by four or more virtual channel holes, depending on the desired layout to be created on the surface of the semiconductor chip. In an example of three virtual channel holes, the contact hole 600 may have a rectangular or square shape, while the main supporting virtual channel hole 510' may have a rectangular shape, and the remaining two second virtual channel holes 520 may have an irregular shape. As shown in fig. 6. The three virtual channel holes 510', 510 ", and 520 may be disposed at three vertices of a triangle, respectively, and the two irregularly shaped second virtual channel holes 520 may have a" splayed "structure. Illustratively, the second virtual channel hole 520 may have an irregular L-shape.

In an exemplary embodiment of the present application, the dummy channel hole 500 may further include a third dummy channel hole 530 (fig. 6). The third dummy channel hole 530 may be located at the step region and spaced apart from the top select gate cut 400. In an actual process, in order to avoid the risk of over-etching of the virtual channel hole 500 due to the overlapping area of the projections of the virtual channel hole 500 and the top select gate notch 400 on the lamination surface (X-Y plane) in the step region, when the virtual channel hole is set, the virtual channel hole and the top select gate notch have a certain distance as much as possible, for example, the third virtual channel hole 530 and the top select gate notch 400 have a certain distance. There will inevitably be dummy channel holes (e.g., first dummy channel hole 510) in the step of the step region, which have an overlapping region with the top select gate cut 400. Therefore, in order to avoid the risk of over-etching of the first virtual channel hole 510, the present application makes the above-mentioned setting on the formation of the overlapping regions of the main supporting virtual channel hole 510' and the auxiliary supporting virtual channel hole 510 ″ of the first virtual channel hole 510 with the top select gate slit 400, respectively.

Illustratively, forming the patterned etch mask layer 700 on the top surface of the dielectric layer 300 may include: forming an etching mask layer 700 on the top surface of the dielectric layer 300; and forming a first dummy via pattern 710 and a second dummy via pattern 720 (fig. 9) in the etch mask layer 700 to form the patterned etch mask layer 700. Illustratively, etching the dielectric layer 300 and the step 200 using the patterned etch mask layer 700 as a mask may include: the dielectric layer 300 and the stepped step 200 are etched through the first dummy trench hole pattern 710 and the second dummy trench hole pattern 720. An extension length of the predetermined overlap region 711 of the first dummy channel hole pattern 710 and the top select gate slit 400 in the first direction D1 may be less than a maximum size of the first dummy channel hole pattern 710 in the first direction D1, and an extension length of the predetermined overlap region 711 in the second direction D2 perpendicular to the top select gate slit 400 may be approximately equal to a width of the top select gate slit. Illustratively, a third dummy trench hole pattern 730 and a contact hole pattern 740 may also be formed in the etch mask layer 700, i.e., the patterned etch mask layer 700 may further include the third dummy trench hole pattern 730 and the contact hole pattern 740. It should be understood that the number of the virtual channel holes and the contact holes is not particularly limited in the present application, and the number of the virtual channel holes and the contact holes may be adjusted as needed, depending on the volume size of the three-dimensional memory.

In an exemplary embodiment of the present application, a gate replacement process may also be performed. Specifically, first, the sacrificial layer 120 may be removed using a dry or wet process to form a sacrificial gap; a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, may then be used to fill the sacrificial gap with a conductive material to form the gate layer 130 (fig. 11). Gate layer 130 may be used as part of a turn-on circuit that transmits signals to the memory cells.

Another aspect of the present application provides a three-dimensional memory. Fig. 11 is a schematic structural diagram of a three-dimensional memory according to another exemplary embodiment of the present application.

As shown in fig. 11, the three-dimensional memory may include a stacked structure 100', a dielectric layer 300, a top select gate structure (not shown), and a dummy channel structure 900.

The stacked structure 100' may include a plurality of stacked layers. Illustratively, a stacked structure 100' including a plurality of stacked layers may be formed at one side of a semiconductor layer (not shown). The semiconductor layer may include polysilicon. The stacked-layer structure 100' may include insulating layers 110 and gate layers 130 alternately stacked. The stacked structure 100' may have a stepped step 200 therein. Illustratively, the plurality of step steps 200 may be located at an edge region or a middle region of the stack structure 100'. Illustratively, each of the stair steps 200 may be formed of a plurality of stacked layers (i.e., a plurality of alternately stacked insulating layers 110 and gate layers 130). Of course, in another exemplary embodiment, each step-step 200 may also be formed of one stacked layer (i.e., the adjacent insulating layer 110 and the gate layer 130). It should be understood that the specific thickness of each step 200 depends on the requirement of the number of word lines that each step 200 needs to control in the actual process. Exemplarily, a region of the stacked structure 100' corresponding to the plurality of step steps 200 is referred to as a step region, which may be used to arrange a word line connection structure. The region of the stacked structure 100' corresponding to the plurality of channel structures is referred to as a core region (not shown), which may be used to form an array memory cell string.

The dielectric layer 300 may cover the step 200. Illustratively, the dielectric layer 300 covering the step 200 may be formed using Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof.

Referring to fig. 10B, a top select gate structure 800 may be located in the dielectric layer 300 and perpendicular to the lamination plane (X-Y plane) of the laminated structure 100'. The dummy channel structure 900 may penetrate the dielectric layer 300 and the step 200. The dummy channel structure 900 may include an insulating material. The dummy channel structure 900 may include a first dummy channel structure (not shown), and at least a portion of the first dummy channel structure may overlap the top select gate structure 800. It is understood that the first dummy channel structure may be formed by filling an insulating material into the first dummy channel hole 510 (fig. 6). An extension dimension of a portion of the first dummy channel structure overlapping the top select gate structure 800 (hereinafter, referred to as an "overlapping region") in a first direction parallel to the top select gate structure may be less than a maximum extension length of the first dummy channel structure in the first direction. In an exemplary embodiment of the present application, an extension length of the overlap region in a first direction perpendicular to the top select gate structure 800 may be equal to a width of the top select gate structure 800.

In an exemplary embodiment of the present application, the three-dimensional memory may further include a contact structure penetrating the dielectric layer 300 and extending to the step 200. Illustratively, the contact structure may be formed by filling a conductive material such as a tungsten alloy in the contact hole 600. The contact structure may form an electrical connection with a subsequently formed gate (located in gate layer 130) to draw out gate current. Specifically, the contact structure is in contact with the subsequently formed gate so that an electrical signal can be supplied to or transmitted from the subsequently formed gate.

In an exemplary embodiment of the present application, the first dummy channel structure may include a main supporting dummy channel structure and a secondary supporting dummy channel structure. It is to be understood that the main support virtual channel structure and the secondary support virtual channel structure may be formed by filling the main support virtual channel hole 510' and the secondary support virtual channel hole 510 "(fig. 6) with an insulating material, respectively. The main supporting dummy trench structure may be located near the contact structure, compared to the auxiliary supporting dummy trench structure, which is located further away from the contact structure. The main supporting virtual channel structure and the auxiliary supporting virtual channel structure can both play a supporting role so as to prevent the collapse of the whole structure. Illustratively, the main and auxiliary support dummy channel structures may have substantially the same structure in the second direction D2 perpendicular to the top select gate structure 800, and may have a difference in the maximum opening size in the first direction D1 parallel to the top select gate structure 800. For example, the maximum opening dimension of the primary support dummy channel structure parallel to the first direction D1 may be about 270 angstroms, and the maximum opening dimension of the secondary support dummy channel structure parallel to the first direction D1 may be about 180 angstroms. In other words, the maximum opening dimension 513 of the primary support dummy channel structure disposed proximate to the contact structure may be larger than the maximum opening dimension of the secondary support dummy channel structure disposed distal to the contact structure. Therefore, the main support virtual channel structure has better support effect, and the collapse or deformation of the structure near the contact structure can be better reduced in the process of forming the contact structure. It is understood that top select gate structure 800 can be formed by filling top select gate cutouts 400 (fig. 6) with an insulating material.

In an exemplary embodiment of the present application, the dummy channel structure 900 may further include a second dummy channel structure (not shown). The second dummy channel structure and the first dummy channel structure may be at least positioned at both sides of the contact structure. It is understood that the second dummy channel structure may be formed by filling the second dummy channel hole 520 (fig. 6) with an insulating material. For example, the second dummy channel structure and the main support dummy channel structure may be disposed in a circumferential direction of the contact structure. For example, the second dummy channel structure and the main support dummy channel structure may collectively surround the contact structure. The second dummy channel structures and the main support dummy channel structures disposed in the circumferential direction of each contact structure may have a triangular structure. Two adjacent second dummy channel structures and one main support dummy channel structure may together surround the contact structure. Each contact structure is surrounded by three dummy channel structures so that the main supporting dummy channel structure and the second dummy channel structure can both support and prevent electrical wiring in the vicinity of the contact structure from being bent during the formation of the contact structure when an external force exceeding a permissible range is applied. In other embodiments, each contact structure may be surrounded by four or more dummy channel structures, depending on the intended layout to be created on the surface of the semiconductor chip. In an example of three dummy channel structures, the contact structure may have a rectangular or square shape, while the main support dummy channel structure may have a rectangular shape, and the remaining two second dummy channel structures may have an irregular shape. The three virtual channel structures may be respectively disposed at three vertices of a triangle, and the two irregular-shaped second virtual channel structures may be in a "figure-of-eight" configuration. Illustratively, the second dummy channel structure may have an irregular L-shape.

In an exemplary embodiment of the present application, the dummy channel structure 900 may further include a third dummy channel structure (not shown). The third virtual channel structure is closer to the channel structure in the core region relative to the first virtual channel structure, and the third virtual channel structure and the top selection structure are arranged in a staggered mode. It is understood that the third dummy channel structure may be formed by filling the third dummy channel hole 530 (fig. 6) with an insulating material.

In an exemplary embodiment of the present application, as shown in fig. 11, the stacked structure 100' may be divided into a stepped region including a stepped step, and a core region adjacent to the stepped region. The three-dimensional memory may also include a top select gate structure (not shown) located in the core region. Illustratively, the plurality of top select gate structures may have a spacing therebetween. The top select gate structure may divide a block storage area in the three-dimensional memory into a finger storage area F.

Since the contents and structures involved in describing the fabrication method 1000 above may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described herein again.

Although exemplary methods and structures for fabricating a three-dimensional memory are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. In addition, the illustrated layers and materials thereof are merely exemplary.

FIG. 12 is a schematic diagram of a memory system 2000 according to an embodiment of the present application.

As shown in fig. 12, at least one embodiment of the present application further provides a storage system 2000. The memory system 2000 may include a memory 2100 and a controller 2200. The memory 2100 may be the same as described for any of the embodiments above and will not be described in detail herein. The storage system 2000 may be a two-dimensional storage system or a three-dimensional storage system, and the three-dimensional storage system is described as an example below.

The three-dimensional storage system 2000 may include a three-dimensional memory 2100, a controller 2200, and a host 2300. The three-dimensional memory 2100 may be the same as the three-dimensional memory described in any of the above embodiments, and is not described in detail in this application. The controller 2200 may control the three-dimensional memory 2100 through a channel CH, and the three-dimensional memory 2100 may perform an operation based on the control of the controller 2200 in response to a request from the host 2300. The three-dimensional memory 2100 may receive a command CMD and an address ADDR from the controller 2300 through a channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 2100 may perform an internal operation corresponding to a command on a region selected by an address.

In some embodiments, the three-dimensional storage system may be implemented as a memory device such as a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a multi-media card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) type memory device, a PCI express (PCI-E) type memory device, a Compact Flash (CF) card, a smart media card, or a memory stick, and so forth.

Fig. 13 is a schematic structural diagram of an electronic device 3000 according to an embodiment of the present application.

As shown in fig. 13, at least one embodiment of the present application further provides an electronic device 3000. The electronic device 3000 includes a memory 3100. The memory 3100 may be the same as the memory described in any of the embodiments above, and will not be described in detail herein. The electronic device 3000 may be a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, or other devices with a storage function. Thus, other modules of the electronic device 3000, such as a controller, may be determined based on the particular device type of the electronic device 3000. The other modules may control the three-dimensional memory 3100 through, for example, a channel, and the three-dimensional memory 3100 may receive a command CMD and an address ADDR from the other modules through, for example, a channel, and access a region selected from the memory cell array in response to the address. This is not limited in this application.

The application provides a peripheral circuit, a memory, a storage system and an electronic device, and the metal interconnection structure provided by the application is arranged, so that the peripheral circuit, the memory, the storage system and the electronic device have the same beneficial effects as the metal interconnection structure, and the details are not repeated herein.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (16)

1. A preparation method of a three-dimensional memory comprises the following steps:

forming a laminated structure including a plurality of stacked layers, and forming a plurality of step steps in the laminated structure;

forming a dielectric layer covering the step, and forming a top selection gate notch which is vertical to the lamination surface of the lamination structure in the dielectric layer;

forming a virtual channel hole penetrating through the dielectric layer and the step; and

filling the top select gate cut and the virtual channel hole with an insulating material to form a top select gate structure and a virtual channel structure, respectively,

wherein the virtual channel hole comprises a first virtual channel hole, a projection of the first virtual channel hole on the lamination surface and a projection of the top select gate cut on the lamination surface have an overlapping region, and an extension length of the overlapping region in a first direction parallel to the top select gate cut is smaller than a maximum opening size of the first virtual channel hole in the first direction parallel to the first direction.

2. The method of manufacturing of claim 1, wherein an extension length of the overlap region in a second direction perpendicular to the top select gate cutout is equal to a width of the top select gate cutout.

3. The method of manufacturing of claim 1, wherein the method further comprises:

and forming a contact hole which penetrates through the dielectric layer and extends to the step.

4. The method of manufacturing of claim 3, wherein the virtual channel hole further comprises: the second virtual channel hole, forming a virtual channel hole penetrating through the dielectric layer and the step, includes:

the second virtual channel hole and the first virtual channel hole are formed along at least two sides of the contact hole.

5. The manufacturing method of claim 4, wherein the second virtual channel hole and the first virtual channel hole formed at least at both sides of each of the contact holes have a triangular structure.

6. The method of claim 4, wherein forming a dummy trench hole through the dielectric layer and the step comprises:

forming a patterned etching mask layer on the top surface of the dielectric layer; and

and etching the dielectric layer and the step by taking the patterned etching mask layer as a mask to form the first virtual channel hole and the second virtual channel hole.

7. The production method according to claim 6, wherein,

forming a patterned etch mask layer on the top surface of the dielectric layer includes: forming an etch mask layer on the top surface of the dielectric layer, and forming a first dummy trench hole pattern and a second dummy trench hole pattern in the etch mask layer to form the patterned etch mask layer, and

etching the dielectric layer and the step by using the patterned etching mask layer as a mask comprises the following steps: etching the dielectric layer and the step through the first dummy via hole pattern and the second dummy via hole pattern,

wherein an extension length of a predetermined overlap region of the first dummy channel hole pattern and the top select gate slit in the first direction is less than a maximum size of the first dummy channel hole pattern in the first direction, and an extension length of the predetermined overlap region in a second direction perpendicular to the top select gate slit is equal to a width of the top select gate slit.

8. The production method according to any one of claims 1 to 7, wherein the laminated structure is divided into a step region including the stepped step, and a core region adjacent to the step region, the method further comprising:

forming the top select gate cutout in the core region perpendicular to a lamination plane of the laminated structure.

9. A three-dimensional memory, comprising:

a laminated structure including a plurality of stacked layers, the laminated structure having a stepped step formed therein;

the dielectric layer covers the step steps;

the top selection gate structure is positioned in the dielectric layer and is vertical to the laminated surface of the laminated structure; and

and the virtual channel structure penetrates through the dielectric layer and the step and comprises a first virtual channel structure, at least one part of the first virtual channel structure is overlapped with the top selection gate structure, and the extension length of the at least one part in a first direction parallel to the top selection gate structure is smaller than the maximum extension length of the first virtual channel structure in the first direction.

10. The three-dimensional memory of claim 9, wherein an extension length of the at least a portion in a second direction perpendicular to the top select gate structure is equal to a width of the top select gate structure.

11. The three-dimensional memory of claim 9, wherein the three-dimensional memory further comprises:

and the contact structure penetrates through the dielectric layer and extends to the step.

12. The three-dimensional memory of claim 11, wherein the dummy channel structure further comprises: a second dummy channel structure, the second dummy channel structure and the first dummy channel structure being located at least at both sides of the contact structure.

13. The three-dimensional memory of claim 12, wherein at least the second dummy channel structures and the first dummy channel structures on both sides of each of the contact structures are triangular structures.

14. The three-dimensional memory of any one of claims 9-13, wherein the stacked structure is divided into a stair step region comprising the stair step, and a core region adjacent to the stair step region, the three-dimensional memory further comprising:

the top select gate structure is located in the core region and perpendicular to the lamination surface of the lamination structure.

15. A storage system comprising a controller and the three-dimensional memory of any one of claims 9-14, the controller coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.

16. An electronic device, comprising: the storage system of claim 15.

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