KR20100109745A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
KR20100109745A
KR20100109745A KR1020090028159A KR20090028159A KR20100109745A KR 20100109745 A KR20100109745 A KR 20100109745A KR 1020090028159 A KR1020090028159 A KR 1020090028159A KR 20090028159 A KR20090028159 A KR 20090028159A KR 20100109745 A KR20100109745 A KR 20100109745A
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South Korea
Prior art keywords
gate
region
formed
forming
peripheral circuit
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KR1020090028159A
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Korean (ko)
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KR101579587B1 (en
Inventor
김한수
심선일
심재주
임주영
조원석
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삼성전자주식회사
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Priority to KR1020090028159A priority Critical patent/KR101579587B1/en
Priority claimed from US12/752,485 external-priority patent/US8284601B2/en
Publication of KR20100109745A publication Critical patent/KR20100109745A/en
Application granted granted Critical
Publication of KR101579587B1 publication Critical patent/KR101579587B1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • H01L27/11531Simultaneous manufacturing of periphery and memory cells
    • H01L27/11534Simultaneous manufacturing of periphery and memory cells including only one type of peripheral transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11578Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H01L27/1158Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels

Abstract

PURPOSE: The semiconductor device and formation method the semiconductor device with a superior quality the peripheral circuit is formed on the spark region and formation method can be offered. The opening having the high level difference offers the removed semiconductor device and a method of formation thereof and the quality excellent. CONSTITUTION: The semiconductor device and formation method comprises the recess region(106) and the spark region(108) including the floor side and side are formed on the semiconductor substrate. Plateau on the floor side of the recess region and the sidewall part expanded from plateau as the side are included.

Description

Semiconductor device and method of forming the same

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device having a peripheral circuit and a method of forming the same.

Due to the development of the electronics industry, the multifunction, miniaturization, and high capacity of various electronic devices in which semiconductor devices are used are intensifying. Accordingly, large capacity, high integration, and low power consumption of semiconductor devices have been pursued. In order to meet these demands, semiconductor technology has evolved to manufacture semiconductor devices including various structures away from the conventional planar devices.

However, as the structure of the semiconductor device is diversified, the structures of the respective patterns constituting the semiconductor device are diversified and complicated. In addition, it is inevitable to form an opening having a high step height in order to connect various and complicated patterns present in the semiconductor device and / or to wire peripheral circuits present in the complex structure. Many problems may arise in the formation of openings having high steps and / or in the filling of such openings. For example, an opening having a high step height may be formed in an unexpected location and / or the step of the opening may not have an expected step height, and / or the opening may not be reliably buried and other defects such as voids may occur. There may be a problem that the reliability is deteriorated. In order to solve this problem, studies are being conducted to remove the opening having a high step.

One object of the present invention is to provide a method of forming a semiconductor device having excellent reliability.

Another object of the present invention is to provide a method of forming a semiconductor device including a peripheral circuit formed on a protruding region.

Another object of the present invention is to provide a method of forming a semiconductor device from which an opening having a high step is removed.

To achieve the above technical problem, the present invention provides a semiconductor device and a method of forming the same. A method of forming a semiconductor device includes forming a recessed region including a bottom surface and a side surface, and a protruding region in a semiconductor substrate; Stacking a plurality of gate conductive films spaced apart from each other, including a flat portion on the bottom surface of the recess region and a sidewall portion extending from the flat portion to the side surface; And forming a peripheral circuit on the protruding region.

The semiconductor substrate includes a base substrate and an insulating film on the base substrate, and forming the recessed area includes etching the insulating film of the recessed area to leave the insulating film of the protruding area.

The method of forming the semiconductor device further includes forming a semiconductor film on the insulating film of the protruding region before forming the peripheral circuit.

The method of forming the semiconductor device may include forming an upper surface of the sidewalls of the gate conductive layers to have the same height as an upper surface of the protruding region.

Forming the gate conductive layers includes alternately stacking inter-gate insulating layers and conductive layers on the recess region.

The method of forming the semiconductor device may include forming first openings exposing a bottom surface of the recess region by patterning the conductive layers and the inter-gate insulating layers; And forming active pillars disposed in the first openings while in direct contact with the bottom surface of the recess region.

The method of forming the semiconductor device includes forming an interlayer insulating film on the conductive films and the inter-gate insulating films on which the active pillars are formed; Patterning the interlayer insulating film to form second openings exposing sidewall portions, active pillars, and peripheral circuits of the gate conductive films; The method may further include filling the second opening to form a plug.

The plug may be formed of a material having a higher conductivity than the gate conductive layer.

The semiconductor device includes a semiconductor substrate including a recess region including a bottom surface and a side surface, and a protrusion region; A plurality of gate conductive layers including a flat portion on the bottom surface of the recess region and a sidewall portion extending from the flat portion to the side surface and stacked apart from each other; Active pillars penetrating the plurality of gate conductive layers; It includes a peripheral circuit formed on the protruding region.

The semiconductor device further includes a plug connected to an upper surface of a sidewall of the plurality of gate conductive layers.

By forming a peripheral circuit in the protruding region, it is possible to provide a semiconductor device having excellent quality and a method of forming the same.

The semiconductor device and the method of forming the semiconductor device having a high step difference removed can be provided to provide a semiconductor device and a method of forming the same having excellent quality.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In addition, since they are in accordance with the preferred embodiment, the reference numerals presented in the order of description are not necessarily limited to the order. In the drawings, the thicknesses of films and regions are exaggerated for clarity. Also, if it is mentioned that the film is on another film or substrate, it may be formed directly on the other film or substrate or a third film may be interposed therebetween. The expression 'and / or' is used herein to include at least one of the components listed before and after.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, the base substrate 100 may include a recessed region 106 and a protruding region 108 including a bottom surface and a side surface. The base substrate 100 may be a semiconductor substrate. The recessed region 106 and the protruding region 108 may be one body of the semiconductor substrate. The recess region 106 may be a cell region in which cells are provided, and the cells may include gate conductive layers 130 and an inter-gate insulating pattern 140 that are alternately stacked. The gate conductive layers 130 may include a flat portion on the bottom surface of the recess region 106 and a sidewall portion extending from the flat portion to the side surface, and may be spaced apart from each other. The semiconductor device may include active pillars 156 penetrating through the gate conductive layers 130 and the insulating pattern 140 between the gates, and the active pillars 156 may be formed on the bottom of the base substrate 100. It may be placed in contact with the face. A gate insulating layer pattern 153 is interposed between the active pillars 156 and sidewalls of the gate conductive layers 130 and between the active pillars 156 and the sidewalls of the gate interlayer insulating pattern 140. A portion of the substrate 100 may be exposed. A drain region D may be disposed in an area of the active pillar 156 positioned on the uppermost gate interlayer insulating pattern 146.

The uppermost gate conductive layer 135 may be used as an upper select gate, and the lowermost gate conductive layer 131 may be used as a lower select gate. Gate conductive layers 132 ˜ 134 between the top gate conductive layer 135 and the bottom gate conductive layer 131 may be used as a control gate. Although three control gates are shown in the figure, more control gates may be included.

The protruding region 108 may be a peripheral circuit region where the peripheral circuit 160 is provided. The peripheral circuit 160 may include a peripheral circuit gate insulating layer 164 and a peripheral circuit gate 166. The peripheral circuit gate 166 may be disposed on the protruding region 108, and the peripheral circuit gate insulating layer 164 may be interposed between the peripheral circuit gate 166 and the semiconductor substrate.

Plugs 181 to 186 connected to the top surfaces of the sidewall portions of the gate conductive layers 130 and plugs 187 to 189 connected to the peripheral circuit 160 may be disposed. The plugs 181 to 189 may be connected to the conductive patterns 191 to 199 formed on the interlayer insulating layer 170.

2 is a cross-sectional view for describing a semiconductor device according to example embodiments of the inventive concept.

Referring to FIG. 2, the semiconductor substrate may include the base substrate 100 and the insulating layer 102 on the base substrate 100. The insulating layer 102 may provide the protruding region 108. The peripheral circuit 161 may be provided on the semiconductor film 162 on the insulating film 102.

3 is a cross-sectional view for describing a semiconductor device according to example embodiments of the inventive concepts.

Referring to FIG. 3, the base substrate 200 may include a recessed region 206 and a protruding region 208 including a bottom surface and a side surface. The base substrate 200 may be a semiconductor substrate. The recessed region 206 and the protruding region 208 may be one body of the semiconductor substrate. The recess region 206 may be a cell region in which cells are provided. The cells may include a plurality of gate conductive layers 250 including a flat portion on the bottom surface and a sidewall portion extending from the flat portion to the side surface, and spaced apart from each other by an inter-gate insulating pattern 220. have. An active pillar 232 may be disposed to contact the bottom surface of the base substrate 200 and penetrate the plurality of gate conductive layers 250. An insulating material 234 may be disposed between the active pillars 232, and a drain region may be disposed in an upper region of the active pillar 232 positioned on the inter-gate insulating pattern 226 of the uppermost layer. . A gate insulating layer 240 may be interposed between the gate conductive layers 250 and the active pillar 232 and between the gate conductive layers 250 and the insulating pattern 220 between the gates. A gap fill insulating layer 244 may be disposed between the plurality of active pillars 232, and may be disposed on the lowermost gate conductive layer 251. The common source line may be disposed on the base substrate 200 of the cell region formed in the recess region 206.

The uppermost gate conductive layer 226 may be used as an upper select gate, and the lowermost gate conductive layer 221 may be used as a lower select gate. Gate conductive layers 222 to 225 between the uppermost gate conductive layer 226 and the lowermost gate conductive layer 221 may be used as control gates. Although four control gates are shown in the figure, more control gates may be included.

The protruding region 208 may be an area of the peripheral circuit 260 in which the peripheral circuit 260 is provided. The peripheral circuit 260 may include a peripheral circuit gate insulating layer 264 and a peripheral circuit gate 266. The peripheral circuit gate 266 may be disposed on the protruding region 208, and the peripheral circuit gate insulating layer 264 may be interposed between the peripheral circuit gate 266 and the semiconductor substrate.

The semiconductor device may further include plugs 280 to 286 connected to the top surfaces of the sidewall portions of the gate conductive layers 250, and plugs 287 to 289 connected to the peripheral circuit 260. The plugs 280 to 289 may be connected to the conductive patterns 290 to 299 formed on the interlayer insulating layer 268.

4 is a cross-sectional view for describing a semiconductor device according to another exemplary embodiment of the present disclosure.

Referring to FIG. 4, the semiconductor substrate may include the base substrate 200 and the insulating layer 202 on the base substrate 200. The insulating layer 202 may provide the protruding region 208. The peripheral circuit 261 may be provided on the semiconductor film 262 on the insulating film 202.

5A through 5H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 5A, a recess region 106 may be formed by etching the base substrate 100. Recess regions 106 and protrusion regions 108 including bottom and side surfaces may be formed. The etching process of the base substrate 100 may be performed by an anisotropic etching method. The base substrate 100 may be a semiconductor substrate. The difference between the bottom surface of the recessed region 106 and the top surface of the protruding region 108 may be 0.5 μm or more. The recess region 106 may be a cell region in which cells are formed, and the protrusion region 108 may be a peripheral circuit region 160 in which the peripheral circuit 160 is formed.

The base substrate 100 may be a semiconductor having a single crystal structure (for example, a P-type silicon wafer). The base substrate 100 may include a region electrically separated by impurity regions of another conductivity type.

Referring to FIG. 5B, inter-gate insulating layers 111 to 116 and conductive layers 121 to 125 may be alternately stacked on the recess region 106. The inter-gate insulating layers 111 ˜ 116 and the conductive layers 121 ˜ 125 may also be formed on the protruding region 108. The conductive layers 121 to 125 may include doped polycrystalline silicon formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer chemical vapor deposition (ALD).

The inter-gate insulating layers 111 to 116 may include a silicon oxide film formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD).

Referring to FIG. 5C, the inter-gate insulating films 111 ˜ 116 and the conductive layers 121 ˜ 125 alternately stacked on the protruding region 108 may be subjected to chemical mechanical polishing (CMP) or etch back processes. Can be removed. Upper surfaces of the sidewall portions of the inter-gate insulating layers 111 to 116 and the conductive layers 121 to 125 may be formed to have the same height as the upper surface of the protruding region 108. As a result, inter-gate insulating patterns 141 to 146: 140 may be formed, and gate conductive layers 131 to 135: 130 may be formed. The gate conductive layers 130 may be stacked to be spaced apart from each other by the inter-gate insulating pattern 140. The gate conductive layers 130 may have a flat portion on the bottom surface of the recess region 106 and a sidewall extending from the flat portion to the side surface. It may include wealth. Upper surfaces of the sidewall portions of the gate conductive layers 130 may be formed to have the same height as the upper surfaces of the protruding regions 108.

Referring to FIG. 5D, a first opening 150 exposing the bottom surface of the recess region 106 may be formed by patterning the gate conductive layers 130 and the insulating pattern 140 between the gates. . When the sidewall of the first opening 150 is formed to be inclined, the width of the channel may vary. To minimize this, patterning for forming the first opening 150 may be performed using an anisotropic etching technique. As a result, the first opening 150 may have vertical sidewalls.

According to an embodiment of the present disclosure, the first opening 150 may be formed by patterning the conductive layers 121 ˜ 126 and the inter-gate insulating layers 111 ˜ 116 before the process of FIG. 5C. have.

Referring to FIG. 5E, the gate insulating layer 152 may be conformally formed on the resultant product in which the first opening 150 is formed. The gate insulating layer 152 may include one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). Can be.

The gate insulating layer 152 may include a thin film for storing information. For example, the gate insulating layer 152 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer that are sequentially stacked. The charge storage layer may include a silicon nitride layer or a silicon oxynitride layer having a charge trap site. The tunnel insulating film may include a silicon oxide film by a thermal oxide film or chemical vapor deposition (CVD), and the blocking insulating film may include at least one of materials having a higher dielectric constant than the tunnel insulating film.

A spacer 154 may be formed in the first opening 150 as an etching mask. The spacer 154 is formed to cover the inner sidewall of the gate insulating layer 152 in the first opening 150 to be formed on the gate insulating layer 152 in a subsequent patterning process of etching the gate insulating layer 152. Can reduce etch damage. For example, the spacer 154 may be one of materials that can be removed while minimizing etching damage to the gate insulating layer 152. For example, when the gate insulating layer 152 in contact with the spacer 154 is a silicon oxide layer, the spacer 154 may be formed of a silicon nitride layer.

Referring to FIG. 5F, the exposed gate insulating layer 152 may be etched using the spacer 154 as an etch mask. Accordingly, a gate insulating layer pattern 153 may be formed at the bottom of the first opening 150 to expose the top surface of the base substrate 100 of the recess region 106. After formation of the gate insulating layer pattern 153, the spacer 154 may be removed.

Subsequently, an active pillar 156 disposed in the first opening 150 may be formed while directly contacting the bottom surface of the recess region 106. The active pillar 156 may be formed of the same material as the base substrate 100. The active pillar 156 and the base substrate 100 may include silicon having a single crystal structure continuously connected without defects of crystals. To this end, the active pillar 156 may be grown from the exposed underlying substrate 100 using one of epitaxial techniques.

Referring to FIG. 5G, a peripheral circuit 160 may be formed on the protruding region 108. First, a peripheral circuit gate insulating layer 164 may be formed on the protruding region 108. The peripheral circuit gate insulating layer 164 may include a silicon oxide layer having a thickness of 40 to 300 angstroms formed through a thermal oxidation process. A peripheral circuit gate 166 may be formed on the peripheral circuit gate insulating layer 164. For example, the peripheral circuit gate 166 may be formed of polycrystalline silicon. On the other hand, since the polycrystalline silicon has a relatively high resistivity compared to the metallic material, a peripheral circuit auxiliary gate (not shown) may be formed on the peripheral circuit gate 166 to reduce the resistance of the peripheral circuit gate 166. have. The peripheral circuit auxiliary gate (not shown) may include any one of silicide layers and metal layers.

Source and drain regions may be formed on both sides of the peripheral circuit gate 166. The source region and the drain region may be regions doped with dopants. Alternatively, the source region and the drain region may be generated by a fringe field generated at the peripheral circuit gate 166 due to the voltage applied to the peripheral circuit gate 166.

As a result, the peripheral circuit 160 including the peripheral circuit gate insulating layer 164 and the peripheral circuit gate 166 may be formed.

An upper select gate line may be formed by patterning the uppermost gate conductive layer 135. Each of the upper selection gate lines may be formed to one-dimensionally connect the active pillars 156.

Referring to FIG. 5H, an interlayer insulating layer 170 may be formed on the base substrate 100. The interlayer insulating layer 170 may also be formed on the peripheral circuit 160 region. Second openings 171 ˜ 179 may be formed by patterning the interlayer insulating layer 170 to expose sidewall portions of the gate conductive layers 130, the active pillars 156, and the peripheral circuit 160. . The drain region D may be formed through the second opening 171 connected to the active pillar 156. The second openings 171 ˜ 179 may not have a high step.

Next, referring to FIG. 1 again, a method of forming a semiconductor device according to an embodiment of the present invention will be described next.

Referring to FIG. 1, a plug conductive layer may be formed on the interlayer insulating layer 170. The plug conductive layer may fill the second openings 171 ˜ 179. The plug conductive layer may include a material having a higher conductivity than the gate conductive layers 130. For example, the plug conductive layer may include tungsten formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). A planarization process may be performed on the interlayer insulating layer 170 as an etch stop layer, thereby forming plugs 181 to 189. Subsequently, a wiring conductive layer may be formed on the interlayer insulating layer 170. The wiring conductive layer may include aluminum formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer chemical vapor deposition (ALD). Conductive patterns 191 to 199 contacting the first and second regions 181 to 189 may be formed.

According to a method of forming a semiconductor device according to an embodiment of the present disclosure, the first and second interconnections may be formed to connect the gate conductive layers 130 and / or the peripheral circuit 160 and the conductive patterns 191 to 199. 2 openings 171 to 179 may be formed. The gate conductive layers 130 may include sidewalls, and the peripheral circuit 160 may be formed on the protruding region 108 so that the second openings 171 ˜ 179 may not have a high step. . For this reason, the position of the opening or the depth of the opening can be easily formed according to the design, and the opening can be buried stably. Thereby, the reliability of the plug which fills the opening part can be improved and the formation method of the semiconductor device excellent in quality can be provided.

6A to 6B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a modification of the embodiment of the present invention.

Referring to FIG. 6A, the semiconductor substrate may include the base substrate 100 and the insulating layer 102. Forming the recess region 106 may include etching the insulating layer 102 of the recess region 106 to leave the insulating layer 102 of the protruding region 108. The insulating layer 102 may include a silicon oxide film formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). Etching the insulating layer 102 may be performed by an anisotropic etching method.

In addition, according to the above-described embodiment, a flat portion on the bottom surface of the recess region 106 and a sidewall portion extending from the flat portion to the side surface and spaced apart from each other by the inter-gate insulating pattern 140. Gate conductive layers 130 may be stacked. An active pillar 156 penetrating the inter-gate insulating pattern 140 and the gate conductive layers 130 may be formed, and the gate insulating pattern 153 may be formed.

Referring to FIG. 6B, a peripheral circuit 161 may be formed on the protruding region 108. The peripheral circuit 161 may include a peripheral circuit gate insulating layer 164 and a peripheral circuit gate 166. The peripheral circuit 161 may be formed on the semiconductor layer 162. For example, the semiconductor film 162 may be formed using a process of bonding the semiconductor film 162 on the insulating film 102 on the protruding region 108. Subsequently, according to the above-described exemplary embodiment, second openings 171 to 179, drain regions D, plugs 181 to 189, and conductive patterns 191 to 199 may be formed. Therefore, it is not necessary to form an opening having a high step, whereby the reliability of the plug can be improved to provide a method of forming a semiconductor device having excellent quality.

7A through 7G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 7A, a recess region 206 may be formed by etching the base substrate 200. A recessed region 206 and a protruding region 208 including bottom and side surfaces may be formed. The etching process of the base substrate 200 may be performed by an anisotropic etching method. The base substrate 200 may be a semiconductor substrate. The difference between the bottom surface of the recessed region 216 and the top surface of the protruding region 218 may be 0.5 μm or more. The recess region 206 may be a cell region in which cells are formed, and the protruding region 208 may be a peripheral circuit region in which a peripheral circuit is provided.

The base substrate 200 may be a semiconductor having a single crystal structure (eg, a P-type silicon wafer). The base substrate 200 may include a region electrically separated by impurity regions of another conductivity type.

Sacrificial layers SC1 to SC6 and inter-gate insulating layers 211 to 216 may be alternately formed on the base substrate 200. The sacrificial layers SC1 to SC6 and the inter-gate insulating layers 211 to 216 may include a flat portion on the bottom surface of the recess region 206 and a sidewall portion extending from the flat portion to the side surface thereof. It may be stacked while being spaced apart. The inter-gate insulating layers 211 to 216 may include at least one of a silicon oxide layer and a silicon nitride layer. The sacrificial layers SC1 ˜ SC6 may be formed of materials that can be selectively etched while minimizing etching of the inter-gate insulating layers 211 ˜ 216.

Referring to FIG. 7B, the inter-gate insulating layers 211 ˜ 216 and the sacrificial layers SC 1 ˜ SC 6 have the same height as the upper surface of the protruding region 208. And the sacrificial layers SC1 ˜ SC6 may be removed using a chemical mechanical polishing (CMP) or etch back process. As a result, inter-gate insulating patterns 221 to 226: 220 may be formed.

A first opening 230 may be formed by patterning the inter-gate insulating pattern 220 and the sacrificial layers SC1 ˜ SC6 to expose the top surface of the base substrate 200. When the side wall of the first opening 230 is formed to be inclined, the width of the channel may vary. In order to minimize this, patterning for forming the first opening 230 may be performed using an anisotropic etching technique. Thus, the first opening 230 may have vertical sidewalls.

Referring to FIG. 7C, an active pillar 232 may be formed to cover the inner wall of the first opening 230. The active column 232 may be formed to conformally cover the inner wall of the first opening 230 using one of chemical vapor deposition (CVD) and atomic layer chemical vapor deposition (ALD). The active column 232 may be formed to have the same conductivity type as the base substrate 200 to which it is in contact, whereby the active column 232 and the base substrate 200 may be electrically connected. For example, the active pillar 232 may include silicon having a single crystal structure continuously connected to the base substrate 200 without defects of crystals. To this end, the active column 232 can be grown from the exposed base substrate 200 using one of epitaxial techniques. The remaining space of the first opening 230 may be filled with an insulating material 234 (eg, silicon oxide film, silicon nitride film, or air).

The inter-gate insulating pattern 220 and the sacrificial layers SC1 ˜ SC6 may be patterned again to form a preliminary gate isolation region 236 exposing an upper surface of the base substrate 200. For example, the preliminary gate isolation region 236 may be formed between adjacent active pillars 232. Accordingly, sidewalls of the inter-gate insulation pattern 220 and the sacrificial layers SC1 ˜ SC6 may be exposed by the preliminary gate isolation region 236. The process of forming the preliminary gate isolation region 236 may be the same as the process of forming the first opening 230.

The sacrificial layers SC1 ˜ SC6 exposed by the preliminary gate isolation region 236 may be removed. Accordingly, gate regions 238 exposing sidewalls of the active pillars 232 may be formed between the inter-gate insulating patterns 220. Removing the sacrificial layers SC1 ˜ SC6 has an etch selectivity compared to the inter-gate insulating pattern 220, the base substrate 200, the active pillar 232, and the insulating material 234. It can be carried out using an etching recipe. In addition, the removing of the sacrificial layers SC1 ˜ SC6 may be a dry or wet method, and an isotropic etching method may be used.

Referring to FIG. 7D, the gate insulating layer 240 may be conformally formed on the resultant product in which the gate regions 238 are formed. The gate insulating layer 240 may include any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). can do.

The gate insulating layer 240 may include a thin film for storing information. For example, the gate insulating layer 240 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer that are sequentially stacked. Since the sidewall of the active pillar 232 is exposed by the gate regions 238, a thermal oxide layer may be directly formed on the exposed surface of the active pillar 232. Therefore, the tunnel insulating film may include a thermal oxide film formed through this method. The charge storage film and the blocking insulating film may be formed using chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALD), which provide excellent step coverage.

Referring to FIG. 7E, a preliminary gate conductive layer 242 may be formed on the gate insulating layer 240 to fill the preliminary gate isolation region 236 and the gate region 238. The preliminary gate conductive layer 242 includes at least one of polycrystalline silicon, silicide layers, and metal layers formed using chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALD), which provides excellent step coverage. can do. Meanwhile, the gate insulating layer 240 is also formed on the top surface of the base substrate 200, and the preliminary gate conductive layer 242 is electrically separated from the base substrate 200. A common source line may be formed on the base substrate 200 of the cell region formed in the recess region 206.

Referring to FIG. 7F, the gate insulating layer 240 and the preliminary gate conductive layer 242 may be removed using a chemical mechanical polishing (CMP) method to have the same height as the upper surface of the protruding region 208. . The gate conductive layers 251 to 256 may be formed by removing the preliminary gate conductive layer 242 formed on the preliminary gate isolation region 236 and forming a gap fill insulating layer 244 on the resultant. Removing the preliminary gate conductive layer 242 formed on the preliminary gate isolation region 236 is etched until the lowest layer 221 of the inter-gate insulating pattern 220 is exposed through a patterning process, but the base substrate is removed. Etching may be performed until the top surfaces of the lowermost layers 251 of the gate conductive layers 250 are exposed so that the 200 is not exposed.

The active pillars 232 may be patterned to form pillars arranged in two dimensions. The lowermost layer 251 of the gate conductive layers 250 may be used as a lower selection gate, and the uppermost layer 256 of the gate conductive layers 250 may be used as an upper selection gate, between the lower and upper portions. The interposed gate conductive layers 251 ˜ 455 may be vertically separated by the inter-gate insulating pattern 220 to be used as electrically independent word line planes. As a result, gate conductive layers 250 including a flat portion on the bottom surface of the recess region 206 and a sidewall portion extending from the flat portion to the side surface and stacked apart from each other may be formed. In addition, upper surfaces of the sidewall portions of the gate conductive layers 250 may be formed to have the same height as the upper surfaces of the protruding regions 208.

The peripheral circuit 260 may be formed on the protruding region 208. First, a peripheral circuit gate insulating layer 264 may be formed on the protruding region 208. The peripheral circuit gate insulating layer 264 may include a silicon oxide film of 40 to 300 angstroms formed through a thermal oxidation process. A peripheral circuit gate 266 may be formed on the peripheral circuit gate insulating layer 264. For example, the peripheral circuit gate 266 may be formed of polycrystalline silicon. On the other hand, since polycrystalline silicon has a relatively high resistivity compared to a metallic material, a peripheral circuit auxiliary gate (not shown) may be formed on the peripheral circuit gate 266 to reduce the resistance of the peripheral circuit gate 266. have. The peripheral circuit auxiliary gate (not shown) may include any one of silicide layers and metal layers.

Source and drain regions may be formed at both sides of the peripheral circuit gate 266. The source region and the drain region may be regions doped with dopants. Alternatively, the source region and the drain region may be generated by a fringe field generated at the peripheral circuit gate 266 due to the voltage applied to the peripheral circuit gate 266.

As a result, the peripheral circuit 260 including the peripheral circuit gate insulating layer 264 and the peripheral circuit gate 266 may be formed.

Referring to FIG. 7G, an interlayer insulating layer 268 may be formed on the base substrate 200. Second openings 270 ˜ 279 may be formed by patterning the interlayer insulating layer 268 to expose sidewalls, active pillars 232, and peripheral circuits 260 of the gate conductive layers 250. The process of patterning the interlayer insulating layer 268 may be performed through an anisotropic etching process. A drain region may be formed on the active pillar 232 through the second opening 270 exposing the active pillar 232.

Next, with reference to FIG. 3 again, the formation method of the semiconductor device which concerns on other Example of this invention is demonstrated.

Referring to FIG. 3, a plug conductive layer may be formed on the interlayer insulating layer 268. The plug conductive layer may fill the second openings 270 ˜ 279. The plug conductive layer may include a material having a higher conductivity than the gate conductive layers 250. For example, the plug conductive layer may include tungsten formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer chemical vapor deposition (ALD). A planarization process may be performed on the interlayer insulating layer 268 as an etch stop layer, thereby forming plugs 280 to 289. Subsequently, a wiring conductive layer may be formed on the interlayer insulating layer 268. The wiring conductive layer may include aluminum formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer chemical vapor deposition (ALD). The conductive patterns 209 to 299 contacting the fields 280 to 289 may be formed.

The second openings 270 to 279 may be formed to connect the gate conductive layers 250 and / or the peripheral circuit 260 and the conductive patterns 290 to 299. The gate conductive layers 250 may include sidewalls, and peripheral circuits 260 may be formed on the protruding regions 208 such that the second openings 270 ˜ 279 may not have a high step. For this reason, the position of the opening or the depth of the opening can be easily formed according to the design, and the opening can be buried stably. Thereby, the reliability of the plug which fills the opening part can be improved and the formation method of the semiconductor device excellent in quality can be provided.

8A through 8B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a modification of another embodiment of the present invention.

Referring to FIG. 8A, the semiconductor substrate may include the base substrate 200 and the insulating layer 202. Forming the recessed region 206 may include etching the insulating layer 202 of the recessed region 206 to leave the insulating layer 202 of the protruding region 208. The insulating layer 202 may include a silicon oxide film formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). Etching the insulating layer 202 may be performed by an anisotropic etching method.

According to the above-described embodiment, an inter-gate insulating pattern 220 including a flat portion on the bottom surface of the recess region 206 and a sidewall portion extending from the flat portion to the side surface and stacked spaced apart from each other is formed. The active pillar 232 and the insulating material 234 in the active pillar 232 may be formed. The gate conductive layers 250 may be stacked to be spaced apart from each other by the inter-gate insulating pattern 220, and include a flat portion on the bottom surface of the recess region 206 and a sidewall portion extending from the flat portion to the side surface. ) May be formed. In addition, a gate insulating layer 240 may be interposed between the gate conductive layers 250, the active pillars 232, and the insulating patterns 220 between the gate conductive layers 250 and the gate, and the gate A gap fill insulating layer 244 may be formed to separate the conductive layers 250.

Referring to FIG. 8B, a peripheral circuit 261 may be formed on the protruding region 208. The peripheral circuit 261 may include a peripheral circuit gate insulating layer 264 and a peripheral circuit gate 266. The peripheral circuit 261 may be formed on the semiconductor film 262. For example, the semiconductor film 262 may be formed using a process of bonding the semiconductor film 262 on the insulating film 202. Subsequently, according to the above-described exemplary embodiment, second openings 270 to 279, plugs 281 to 289, and conductive patterns 291 to 299 may be formed. Therefore, it is not necessary to form an opening having a high step, whereby the reliability of the plug can be improved to provide a semiconductor device having excellent quality.

 9 is a block diagram illustrating a memory system including a semiconductor device according to example embodiments.

Referring to FIG. 9, the memory system 1000 according to the present invention may include a memory device 1100, a memory controller 1100, a central processing unit 1500 electrically connected to a system bus 1250, a user interface 1600, A power supply 1700. The memory device 1100 may include at least one of the semiconductor devices disclosed in the above-described embodiments.

Data provided through the user interface 1600 or processed by the CPU 1500 is stored in the memory device 1100 through the memory controller 1100. The memory device 1100 may be configured as a semiconductor disk device (SSD), in which case the write speed of the memory system 1000 will be significantly faster. The semiconductor device according to the exemplary embodiment of the present invention may be applied to the above-described memory device 1100, the memory controller 1100, the CPU 1500, and the like.

Although not shown in the drawings, the memory system 1000 according to the present invention may further be provided with an application chipset, a camera image processor, a mobile DRAM, and the like. Self-explanatory to those who have learned.

In addition, the memory system 1000 may include a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, and a memory card. card), or any device capable of transmitting and / or receiving information in a wireless environment.

1 is a cross-sectional view illustrating a semiconductor device and a method of forming the same according to an embodiment of the present disclosure.

2 is a cross-sectional view for describing a semiconductor device according to example embodiments of the inventive concept.

3 is a cross-sectional view for describing a semiconductor device and a method of forming the semiconductor device according to example embodiments of the inventive concept.

4 is a cross-sectional view for describing a semiconductor device according to another exemplary embodiment of the present disclosure.

5A through 5H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

6A to 6B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a modification of the embodiment of the present invention.

7A through 7G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the present invention.

8A to 8B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a modification of another embodiment of the present invention.

 9 is a block diagram illustrating a memory system including a semiconductor device according to example embodiments.

Claims (10)

  1. Forming a recessed region including a bottom surface and a side surface and a protrusion region in the semiconductor substrate;
    Stacking a plurality of gate conductive films spaced apart from each other, including a flat portion on the bottom surface of the recess region and a sidewall portion extending from the flat portion to the side surface; And
    Forming a peripheral circuit on the protruding region.
  2. The method of claim 1,
    The semiconductor substrate comprises a base substrate and an insulating film on the base substrate,
    Forming the recessed region includes etching the insulating film of the recessed region and leaving the insulating film of the protruding region.
  3. 3. The method of claim 2,
    And forming a semiconductor film on the insulating film in the protruding region before forming the peripheral circuit.
  4. The method of claim 1,
    And forming upper surfaces of sidewalls of the gate conductive layers to have the same height as upper surfaces of the protruding regions.
  5. The method of claim 1,
    Forming the gate conductive layers,
    And alternately stacking inter-gate insulating films and conductive films on the recess region.
  6. The method of claim 5,
    Patterning the conductive layers and the inter-gate insulating layers to form first openings exposing a bottom surface of the recess region; And
    And forming active pillars disposed in the first openings while in direct contact with a bottom surface of the recess region.
  7. The method of claim 6,
    Forming an interlayer insulating film on the conductive films and the inter-gate insulating films on which the active pillars are formed;
    Patterning the interlayer insulating film to form second openings exposing sidewall portions, active pillars, and peripheral circuits of the gate conductive films;
    And embedding the second opening to form a plug.
  8. The method of claim 7, wherein
    And the plug is formed of a material having a higher conductivity than the gate conductive layer.
  9. A semiconductor substrate including a recess region including a bottom surface and a side surface, and a protrusion region;
    A plurality of gate conductive layers including a flat portion on the bottom surface of the recess region and a sidewall portion extending from the flat portion to the side surface and stacked apart from each other;
    Active pillars penetrating the plurality of gate conductive layers;
    And a peripheral circuit formed on the protruding region.
  10. The method of claim 9,
    And a plug connected to upper surfaces of sidewalls of the plurality of gate conductive layers.
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US12/752,485 US8284601B2 (en) 2009-04-01 2010-04-01 Semiconductor memory device comprising three-dimensional memory cell array
US13/594,102 US8787082B2 (en) 2009-04-01 2012-08-24 Semiconductor memory device comprising three-dimensional memory cell array

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