CN114812878A - High-sensitivity piezoresistive sensitive unit and manufacturing method thereof - Google Patents

High-sensitivity piezoresistive sensitive unit and manufacturing method thereof Download PDF

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CN114812878A
CN114812878A CN202210357554.1A CN202210357554A CN114812878A CN 114812878 A CN114812878 A CN 114812878A CN 202210357554 A CN202210357554 A CN 202210357554A CN 114812878 A CN114812878 A CN 114812878A
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ultra
ldd
shallow junction
well
epitaxial layer
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CN114812878B (en
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王任鑫
张文栋
刘国昌
谭皓宇
李皓璇
乔庆宇
张国军
杨玉华
何常德
崔建功
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North University of China
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/18—Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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Abstract

The invention belongs to the technical field of sensors, and relates to a sensitive unit and preparation thereof, in particular to a high-sensitivity sensitive unit and a manufacturing method thereof. The method of the invention adopts an ultra-shallow junction and drain injection mode in a CMOS process to carry out low-energy ion injection in a piezoresistive region, so that an LDD ultra-shallow junction silicon nano film is generated; the sensitivity of the sensor can be greatly improved by utilizing the giant piezoresistive effect sensitive mechanism of the silicon nano-film.

Description

High-sensitivity piezoresistive sensitive unit and manufacturing method thereof
Technical Field
The invention belongs to the technical field of sensors, relates to a sensitive unit and preparation thereof, and particularly relates to a high-sensitivity piezoresistive sensitive unit and a manufacturing method thereof.
Background
Piezoresistive sensors based on piezoresistive effect are widely applied to various fields such as aerospace, aviation, navigation, petrochemical engineering, power machinery, biomedical engineering, meteorological measurement, geological measurement, seismic measurement and the like due to the advantages of good low-frequency characteristics, high resolution, high frequency response and the like.
In general, a sensitive unit of a piezoresistive sensor is a square resistor formed by a conventional ion implantation or diffusion method through an MEMS process, and the working mechanism of the square resistor is lattice deformation caused by strain, so that the change of mobility of multiple molecules is caused to generate the change of resistivity. However, the variation of the multi-mobility is limited, the characteristic size of the MEMS process is in the micrometer scale, and the uniformity and the frequency response of the produced sensitive unit are poor, so the sensitive unit prepared by the MEMS process has the disadvantage of low sensitivity. The working mechanism of the piezoresistive sensor based on the giant piezoresistive effect is that strain causes the change of surface potential, and then the change of multi-quantum concentration causes the change of resistivity. The change in the concentration of majority carriers can be orders of magnitude higher than the change in the mobility of majority carriers, so piezoresistive sensors based on the giant piezoresistive effect have a very high sensitivity. Therefore, how to prepare a sensitive unit based on giant piezoresistive effect is a problem to be overcome at present.
Disclosure of Invention
The invention provides a high-sensitivity piezoresistive sensitive unit and a manufacturing method thereof, aiming at solving the problem of low sensitivity of the traditional piezoresistive sensor.
The technical means for solving the technical problems of the invention is as follows: a high-sensitivity piezoresistive sensitive unit comprises a semiconductor substrate, an N well and at least one LDD (laser diode doped) ultra-shallow junction, wherein an epitaxial layer extends upwards from the semiconductor substrate, light P-type impurity doping is carried out on the epitaxial layer, the N well is positioned on the epitaxial layer, the LDD ultra-shallow junction is positioned on the N well, P + active regions are arranged at two ends of the LDD ultra-shallow junction, an oxide layer covers the surface of the epitaxial layer, a window for exposing the P + active regions is formed in the oxide layer, and the P + active regions exposed at the window are connected with metal leads through an alloy layer. The covering oxide layer is used for protecting the surface epitaxial layer from being polluted, preventing the excessive damage of the silicon wafer caused by the implantation process, and is used as an oxide shielding layer to help control the implantation depth of impurities in the implantation process.
Due to the existence of surface potential, intrinsic fermi energy levels at the upper and lower surfaces of the LDD ultra-shallow junction are bent to form space charge regions. The distance between the upper surface and the lower surface of the LDD ultra-shallow junction silicon nano film is smaller than the width of a space charge region generated by the upper surface and the lower surface, namely the space charge region penetrates through the whole nano film, at the moment, the sensitive unit is in a completely depleted state, the sensitive unit generates a giant piezoresistive effect, namely, the surface potential is changed due to strain, and further the resistivity is changed due to the change of multi-seed concentration. Compared with the conventional piezoresistive effect, the change of the concentration of the majority carriers can be higher by several orders of magnitude than the change of the mobility of the majority carriers, so that the sensitive unit has higher sensitivity.
The invention also provides the following technical problems: a manufacturing method of a high-sensitivity piezoresistive sensitive unit comprises the following steps:
s1, growing an epitaxial layer on the semiconductor substrate upwards and carrying out light P-type impurity doping on the epitaxial layer;
s2, growing an oxide layer on the surface of the epitaxial layer;
s3, arranging a first mask for manufacturing the N well on the oxide layer, wherein the uncovered region of the first mask is the region where the N well is located, and injecting N-type impurities in the uncovered region of the epitaxial layer at high energy to form the N well; then, carrying out photoresist removing treatment, cleaning and carrying out high-temperature annealing;
s4, arranging a second mask for manufacturing LDD ultra-shallow junction on the oxide layer, wherein the uncovered region of the second mask is located in the N well, and implanting BF by lightly doped drain implantation 2 Forming LDD ultra-shallow junctions by the impurities; then, carrying out photoresist removing treatment;
s5, continuously arranging a third mask for manufacturing a P + active region on the oxide layer, wherein uncovered regions of the third mask are positioned at two ends of the LDD ultra-shallow junction, injecting P-type impurities into the uncovered regions to form the P + active region, then carrying out photoresist removing treatment, and carrying out rapid annealing treatment after cleaning;
s6, continuously arranging a fourth mask for manufacturing a p + active region window on the oxide layer, wherein the uncovered region of the fourth mask is the region where the p + active region is located, and forming a window for exposing the p + active region by utilizing anisotropic etching of the oxide layer;
s7, performing photoresist removing treatment, and performing magnetron sputtering titanium;
s8, after sputtering treatment, cleaning and then carrying out rapid thermal annealing treatment, wherein in the annealing process, an alloy layer is formed by titanium and a semiconductor of a p + active region; then, titanium outside the window of the p + active region is cleaned and corroded by a chemical method;
s9, performing magnetron sputtering of the aluminum-copper alloy on the oxide layer;
s10, after sputtering treatment, arranging a fifth mask plate for manufacturing the metal lead on the surface of the aluminum-copper alloy, wherein the coverage area of the fifth mask plate is the area where the metal lead is located; carrying out aluminum copper alloy etching treatment on the uncovered area to form a metal lead after the treatment; finally obtaining the high-sensitivity sensitive unit.
According to the manufacturing method, when the piezoresistive sensitive unit is prepared, the conventional high-energy ion implantation is not adopted to form the square resistor, the low-energy ion implantation is carried out on the N well by adopting a CMOS (complementary metal oxide semiconductor) process through a light-doped drain implantation method, so that the LDD ultra-shallow junction silicon nano film is generated, and the sensitivity of the sensor can be greatly improved by utilizing a giant piezoresistive effect sensitive mechanism of the silicon nano film.
Preferably, in S3, the N-well is prepared in a high-energy ion implanter, the N-type impurity is a phosphorus impurity, the implantation energy is 200 KeV, the annealing temperature is 950 ℃, and the annealing time is 25-30 min. This is to make the impurities sufficiently advance in the trap tensile work.
Preferably, in S4, the LDD ultra-shallow junction is prepared in a low-energy ion implanter, and the implantation energy is 5 to 10 KeV. This is to make the LDD ultra shallow junction depth smaller than the N-well.
Preferably, in S5, the preparation of the P + active region is carried out in a medium-energy ion implanter, the P-type impurity is a boron impurity, and the implantation energy is 100-120 KeV; the annealing temperature is 1000-1200 ℃ and the annealing time is 4-5 s. And the junction depth of the silicon nano film is maintained while repairing the crystal lattice damage by using intermediate energy ion implantation and performing rapid thermal annealing treatment in the p + active region. This is to repair the lattice damage while maintaining the junction depth of the silicon nano-film.
Preferably, the thickness of the sputtered titanium in S7 is 200A, the return temperature in S8 is 600-800 ℃, and the time is 10S; the chemical process is to use NH 4 OH and H 2 O 2 Reacting with metallic titanium; the thickness of the aluminum-copper alloy sputtered in S9 is 5000-6000A, and aluminum accounts for 96-99.5% and copper accounts for 0.5-4% in the aluminum-copper alloy. The stability of aluminum can be improved by adding copper to the aluminum.
The invention has the beneficial effects that: in the invention, a P-type LDD ultra-shallow junction silicon nano film is formed on an N well by a CMOS process through a light doping drain injection method; the method has the advantages that the method can carry out ion implantation and rapid thermal annealing treatment in a p + active region, so that the junction depth of the silicon nano film is maintained while the lattice damage is repaired; compared with the prior art, the LDD ultra-shallow junction silicon nano-film is formed, and the sensitivity of the sensor can be greatly improved by utilizing the giant piezoresistive effect sensitive mechanism of the silicon nano-film.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic view of a device structure after an epitaxial layer is grown and lightly doped according to the present invention;
FIG. 2 is a schematic diagram of the device structure after the oxide layer is grown according to the present invention;
FIG. 3 is a schematic diagram of a device structure after high-energy ion implantation to form an N-well and annealing treatment;
FIG. 4 is a schematic view of the device structure after LDD ultra-shallow junction nano-films are formed by lightly doped drain implantation;
FIG. 5 is a schematic diagram of the device structure after the p + active region is formed and the rapid annealing process is performed;
FIG. 6 is a schematic view of a device structure after sputtering metallic titanium and rapid annealing treatment to form an alloy and patterning
FIG. 7 is a schematic diagram of the structure of the device with the sensing unit finally formed after sputtering the Al-Cu alloy and etching to form the metal lead.
FIG. 8 is a schematic diagram of a top view of a high-sensitivity piezoresistive sensing unit according to the present invention (with the oxide layer and the metal wire removed).
FIG. 9 is a schematic diagram of a top view of a high-sensitivity piezoresistive sensing unit according to the present invention (with the oxide layer removed and the metal wire preserved).
FIG. 10 is a schematic flow chart of a method for manufacturing a high-sensitivity piezoresistive sensitive cell according to the present invention.
In the figure: 1. a semiconductor substrate; 2. an epitaxial layer; 3. an oxide layer; 4. an N well; 5. LDD ultra shallow junctions; 6. a p + active region; 7. an alloy layer; 8. and a metal lead.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the term "disposed" is to be understood broadly, and the specific meaning of the above term in the present invention may be specifically understood by those of ordinary skill in the art.
The invention provides a manufacturing method of a high-sensitivity piezoresistive sensitive unit, which comprises the following steps as shown in figures 1-10:
s1, selecting P-type monocrystalline silicon with the crystal direction of <100> and the resistivity of 1-20 omega-cm as a semiconductor substrate 1, growing an epitaxial layer 2 of 5-6 um upwards on the semiconductor substrate 1, and carrying out light P-type impurity doping on the epitaxial layer 2; the P-type impurity is boron impurity, and can also be other P-type impurities meeting the conditions;
s2, placing the epitaxial layer 2 in a high-temperature furnace at 1000 ℃, and oxidizing and growing an oxide layer 3 with approximately 150A on the surface of the epitaxial layer; the purpose is as follows: the surface epitaxial layer 2 is protected from being contaminated, the excessive damage to the silicon wafer in the injection process is prevented, and the oxide shielding layer is used for controlling the injection depth of impurities in the injection process;
s3, arranging a first mask plate for manufacturing the N well 4 on the oxide layer 3, wherein the uncovered area of the first mask plate is the area where the N well 4 is located, spinning photoresist on a silicon wafer and photoetching to protect all the areas except the area where the N well 4 is located from ion implantation, and in a high-energy ion implanter, injecting N-type impurities into the uncovered area of the epitaxial layer 2 at high energy to form the N well 4 with the depth of about 1um, wherein the N-type impurities are phosphorus impurities or other N-type impurities meeting the conditions, and the injection energy is 200 KeV; then, carrying out photoresist removing treatment in an oxygen-based plasma reactor, and carrying out high-temperature annealing after cleaning, wherein the annealing temperature is 950 ℃, and the time is 25-30 min, and the purpose is as follows: impurities are moved into the silicon, damage caused by injection is repaired, and a lattice structure is repaired;
s4, arranging a second mask plate for manufacturing LDD ultra-shallow junction 5 on the oxide layer 3, wherein the uncovered region of the second mask plate is positioned in the N well 4, spin-coating photoresist on the silicon wafer and photoetchingThe regions except the LDD ultra-shallow junction 5 are all protected from ion implantation, and BF is implanted into the uncovered region by lightly doped drain implantation in a medium-energy ion implanter 2 Forming an LDD ultra-shallow junction 5 with the depth of 200A by using impurities, wherein the implantation energy is 5-10 KeV; then carrying out photoresist removing treatment in an oxygen-based plasma reactor;
s5, continuously arranging a third mask plate for manufacturing a P + active region 6 on the oxide layer 3, wherein uncovered regions of the third mask plate are positioned at two ends of the LDD ultra-shallow junction 5, spin-coating photoresist and photoetching, protecting all regions except the P + active region 6 from ion implantation, implanting P-type impurities into the uncovered regions in a medium-energy ion implanter to form the P + active region 6 with the depth of 500A, wherein the implantation energy is 100-120 KeV, the P-type impurities are boron impurities or other P-type impurities meeting the conditions, then performing photoresist removing treatment in an oxygen-based plasma reactor, and performing high-temperature annealing in a rapid annealing furnace after cleaning, wherein the annealing temperature is 1000-1200 ℃ and the time is 4-5S;
s6, continuously providing a fourth mask for making a window of the p + active region 6 on the oxide layer 3, where an uncovered region of the fourth mask is a region where the p + active region 6 is located, spin-coating a photoresist and performing photolithography, protecting all regions except the p + active region 6 from ion implantation, etching 150 a of silicon dioxide in a plasma etcher, i.e., forming a window exposing the p + active region 6 by anisotropically etching the oxide layer 3;
s7, placing the film into an oxygen-based plasma reactor for photoresist removal, and then placing the film into a magnetron sputtering instrument for magnetron sputtering metal titanium of 200A;
s8, after sputtering treatment, cleaning, and then placing into a rapid annealing furnace for annealing treatment, wherein the annealing temperature is 600-800 ℃, the annealing time is 8-10S, and in the annealing process, the titanium and the semiconductor of the p + active region 6 form an alloy layer 7; then through NH 4 OH and H 2 O 2 Titanium outside a window of the p + active region 6 is cleaned and corroded by a wet method of titanium reaction;
s9, performing magnetron sputtering on the oxide layer 3 in a magnetron sputtering instrument to form a copper alloy with aluminum being 5000-6000A; the aluminum content in the copper alloy is 96-99.5%, and the copper content is 0.5-4%;
s10, after sputtering, arranging a fifth mask for manufacturing the metal lead 8 on the surface of the aluminum-copper alloy, wherein the coverage area of the fifth mask is the area where the metal lead 8 is located, spin-coating photoresist and photoetching to protect the area where the metal lead 8 is located from metal etching; placing the aluminum-copper alloy into a plasma etching machine to carry out aluminum-copper alloy etching treatment on the uncovered area, and forming a metal lead 8 after the treatment; finally obtaining the high-sensitivity sensitive unit.
The manufacturing method of the invention adopts the ultra-shallow junction leakage injection mode in the CMOS process to carry out low-energy ion injection in the piezoresistive region, so that the LDD ultra-shallow junction 5 silicon nanometer film is generated, and the giant piezoresistive effect sensitive mechanism of the silicon nanometer film is utilized, so that the sensitivity of the sensor can be greatly improved.
The piezoresistive sensitive unit with high sensitivity can be obtained by the method, as shown in fig. 1-9, and comprises a semiconductor substrate 1, an N well 4 and at least one LDD ultra-shallow junction 5, wherein the semiconductor substrate 1 adopts a crystal orientation<100>The semiconductor device is characterized in that the semiconductor device is made of P-type monocrystalline silicon with the resistivity of 1-20 omega-cm, an epitaxial layer 2 with the thickness of 5um extends upwards from a semiconductor substrate 1, the epitaxial layer 2 is doped with light boron impurities, an N well 4 is positioned on the epitaxial layer 2, the N well 4 is formed by injecting phosphorus impurities into the epitaxial layer 2, the depth of the N well 4 is 1um, an LDD ultra-shallow junction 5 is positioned on the N well 4, and the LDD ultra-shallow junction 5 is formed by injecting BF (boron) into the N well 4 2 The depth of the LDD ultra-shallow junction 5 is 200 a, both ends of the LDD ultra-shallow junction 5 are provided with p + active regions 6, the p + active regions 6 are formed by implanting boron impurities into the LDD ultra-shallow junction 5, the depth of the p + active regions 6 is 500 a, the surface of the epitaxial layer 2 is covered with an oxide layer 3 having a thickness of 150 a, a window exposing the p + active regions 6 is opened on the oxide layer 3, and the p + active regions 6 exposed at the window are connected with aluminum-copper alloy metal leads 8 having a thickness of 5000 a through an alloy layer 7 having a thickness of 200 a.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. The high-sensitivity piezoresistive sensitive unit is characterized by comprising a semiconductor substrate (1), an N well (4) and at least one LDD (lightly doped drain) ultra-shallow junction (5), wherein the semiconductor substrate (1) extends upwards to form an epitaxial layer (2), the epitaxial layer (2) is doped with light P-type impurities, the N well (4) is positioned on the epitaxial layer (2), the LDD ultra-shallow junction (5) is positioned on the N well (4), P + active regions (6) are arranged at two ends of the LDD ultra-shallow junction (5), an oxide layer (3) covers the surface of the epitaxial layer (2), a window exposing the P + active regions (6) is formed in the oxide layer (3), and the P + active regions (6) exposed at the window are connected with metal leads (8) through alloy layers (7).
2. The piezoresistive sensing unit according to claim 1, characterized in that the semiconductor substrate (1) is made of P-type single crystal silicon with crystal orientation <100> and resistivity of 1-20 Ω -cm.
3. The piezoresistive sensitive unit according to claim 1, wherein the thickness of the epitaxial layer (2) is 5-6 um, and the P-type impurity in the epitaxial layer (2) is boron impurity; the N well (4) is formed by implanting phosphorus impurities into the epitaxial layer (2), and the depth of the N well (4) is 1 um.
4. A highly sensitive piezoresistive sensitive cell according to claim 1, characterized in that the LDD ultra shallow junction (5) is formed by BF implantation into the N-well (4) 2 Impurity is formed, and the depth of the LDD ultra-shallow junction (5) is 200A.
5. A high sensitivity piezoresistive sensitive cell according to claim 1, characterized in that the p + active region (6) is formed by implanting boron impurities into the LDD ultra shallow junction (5), the p + active region (6) having a depth of 500 a.
6. A manufacturing method of a high-sensitivity piezoresistive sensitive unit is characterized by comprising the following steps:
s1, growing an epitaxial layer (2) upwards on the semiconductor substrate (1) and carrying out light P-type impurity doping on the epitaxial layer (2); s2, growing an oxide layer (3) on the surface of the epitaxial layer (2);
s3, arranging a first mask plate for manufacturing the N well (4) on the oxide layer (3), wherein the uncovered area of the first mask plate is the area where the N well (4) is located, and injecting N-type impurities in the uncovered area of the epitaxial layer (2) at high energy to form the N well (4); then, carrying out photoresist removing treatment, cleaning and carrying out high-temperature annealing;
s4, arranging a second mask plate for manufacturing LDD ultra-shallow junction (5) on the oxide layer (3), wherein the uncovered region of the second mask plate is positioned in the N well (4), and implanting BF in the uncovered region by using a lightly doped drain implantation mode 2 The impurity forms an LDD ultra-shallow junction (5); then, carrying out photoresist removing treatment;
s5, continuously arranging a third mask for manufacturing a P + active region (6) on the oxide layer (3), wherein uncovered regions of the third mask are positioned at two ends of the LDD ultra-shallow junction (5), injecting a P-type impurity into the uncovered regions to form the P + active region (6), then carrying out photoresist removing treatment, and carrying out rapid thermal annealing treatment after cleaning;
s6, continuously arranging a fourth mask for manufacturing a window of the p + active region (6) on the oxide layer (3), wherein the uncovered region of the fourth mask is the region where the p + active region (6) is located, and forming a window for exposing the p + active region (6) by utilizing anisotropic etching of the oxide layer (3);
s7, performing photoresist removing treatment, and performing magnetron sputtering titanium;
s8, after sputtering treatment, cleaning and then carrying out rapid thermal annealing treatment, wherein in the annealing process, the titanium and the semiconductor of the p + active region (6) form an alloy layer (7); then, titanium outside the window of the p + active region (6) is cleaned and corroded by a chemical method;
s9, performing magnetron sputtering of the aluminum-copper alloy on the oxide layer (3);
s10, after sputtering treatment, arranging a fifth mask plate for manufacturing the metal lead (8) on the surface of the aluminum-copper alloy, wherein the coverage area of the fifth mask plate is the area where the metal lead (8) is located; carrying out aluminum copper alloy etching treatment on the uncovered area to form a metal lead (8) after the treatment; finally, the high-sensitivity sensitive sheet is obtained.
7. The method of claim 6, wherein the N-well (4) is prepared in a high energy ion implanter in S3, the N-type impurity is phosphorus impurity, the implantation energy is 200 KeV, the annealing temperature is 950 ℃, and the annealing time is 25-30 min.
8. The method of claim 6, wherein in S4, the preparation of the LDD ultra-shallow junction (5) is performed in a low energy ion implanter with an implantation energy of 5-10 KeV, and the LDD ultra-shallow junction (5) is formed with a depth of 200A.
9. The manufacturing method of piezoresistive sensitive cell according to claim 6, wherein in S5, the preparation of the P + active region (6) is performed in a medium-energy ion implanter, the P-type impurity is boron impurity, and the implantation energy is 100-120 KeV; the annealing temperature is 1000-1200 ℃ and the time is 4-5 s.
10. The method of fabricating a high sensitivity piezoresistive sensing element according to any of claims 6-9, characterized in that the thickness of sputtered titanium in S7 is 200 a, the return temperature in S8 is 700-800 ℃ and the time is 10S; the chemical process is to use NH 4 OH and H 2 O 2 Reacting with metallic titanium; the thickness of the sputtered aluminum-copper alloy in S9 is 5000 angs, and aluminum accounts for 96-99.5% and copper accounts for 0.5-4% in the aluminum-copper alloy.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4417819A1 (en) * 1993-05-22 1994-12-01 Hyundai Electronics Ind Method for producing a CMOS transistor
JPH10270569A (en) * 1997-03-26 1998-10-09 Sony Corp Semiconductor device and manufacture thereof
US5960319A (en) * 1995-10-04 1999-09-28 Sharp Kabushiki Kaisha Fabrication method for a semiconductor device
US6122975A (en) * 1997-11-25 2000-09-26 Institue Of Microelectronics CMOS compatible integrated pressure sensor
US20030107096A1 (en) * 2001-12-12 2003-06-12 Kurtz Anthony D. Combined absolute differential transducer
CN101719482A (en) * 2009-11-25 2010-06-02 中国电子科技集团公司第二十四研究所 Manufacturing method of monolithic integrated pressure sensor
JP2010182953A (en) * 2009-02-06 2010-08-19 Seiko Instruments Inc Semiconductor device
CN102693915A (en) * 2011-03-22 2012-09-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method for MOS transistor
CN103500757A (en) * 2013-10-21 2014-01-08 苏州智瑞佳电子技术有限公司 Semiconductor device with schottky source LDMOS (Laterally Diffused Metal Oxide Semiconductor) and manufacturing method
US20200211914A1 (en) * 2018-12-31 2020-07-02 Micron Technology, Inc. Method and apparatus for on-chip stress detection

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4417819A1 (en) * 1993-05-22 1994-12-01 Hyundai Electronics Ind Method for producing a CMOS transistor
US5960319A (en) * 1995-10-04 1999-09-28 Sharp Kabushiki Kaisha Fabrication method for a semiconductor device
JPH10270569A (en) * 1997-03-26 1998-10-09 Sony Corp Semiconductor device and manufacture thereof
US6122975A (en) * 1997-11-25 2000-09-26 Institue Of Microelectronics CMOS compatible integrated pressure sensor
US20030107096A1 (en) * 2001-12-12 2003-06-12 Kurtz Anthony D. Combined absolute differential transducer
JP2010182953A (en) * 2009-02-06 2010-08-19 Seiko Instruments Inc Semiconductor device
CN101719482A (en) * 2009-11-25 2010-06-02 中国电子科技集团公司第二十四研究所 Manufacturing method of monolithic integrated pressure sensor
CN102693915A (en) * 2011-03-22 2012-09-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method for MOS transistor
CN103500757A (en) * 2013-10-21 2014-01-08 苏州智瑞佳电子技术有限公司 Semiconductor device with schottky source LDMOS (Laterally Diffused Metal Oxide Semiconductor) and manufacturing method
US20200211914A1 (en) * 2018-12-31 2020-07-02 Micron Technology, Inc. Method and apparatus for on-chip stress detection

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ARTHUR T. BRADLEY 等: "Piezoresistive Characteristics of Short-Channel MOSFETs on (100) Silicon", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》, vol. 48, no. 9, pages 2009 - 2015, XP011017761 *
宋金龙: "多参量微纳集成传感器", 《微纳电子技术》, vol. 56, no. 2, pages 119 - 125 *

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