CN114792740A - Preparation method of semiconductor substrate layer and preparation method of solar cell - Google Patents
Preparation method of semiconductor substrate layer and preparation method of solar cell Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 148
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
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- 238000006243 chemical reaction Methods 0.000 claims description 24
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- 239000011259 mixed solution Substances 0.000 claims description 15
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- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 11
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 10
- 238000005553 drilling Methods 0.000 claims description 10
- 229910017604 nitric acid Inorganic materials 0.000 claims description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/08—Etching
- C30B33/10—Etching in solutions or melts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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Abstract
The invention relates to the technical field of solar cells, and particularly provides a semiconductor substrate layer and a preparation method of a solar cell. The preparation method of the semiconductor substrate layer comprises the following steps: providing an initial semiconductor substrate layer; carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution; and after the first texturing treatment is carried out, carrying out second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process. According to the invention, on the basis of carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution, the surface of the initial semiconductor substrate layer is subjected to second texturing treatment by adopting a metal catalytic chemical etching process, so that the inverted pyramid textured surface with lower reflectivity can be prepared by adjusting process parameters on the basis of the pyramid of the alkaline textured surface and combining the characteristic of metal catalytic etching preferred etching.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a semiconductor substrate layer and a preparation method of a solar cell.
Background
Solar cells, which are devices that convert solar radiation energy directly or indirectly into electrical energy through a photoelectric effect or a photochemical effect, have been rapidly developed in recent years. The heterojunction cell is an important solar cell type, and the photoelectric conversion efficiency of the heterojunction cell is improved by changing the performance of a PN junction. In addition, the heterojunction cell has the characteristics of good temperature coefficient, double-sided power generation, low process temperature, high photoelectric conversion efficiency and the like, and is a solar cell technology with great market competitiveness.
Texturing is an important process for forming a good substrate from a silicon wafer, and forms an excellent and efficient silicon substrate, which can improve the photoelectric conversion efficiency of a solar cell. The solar cell structure is characterized in that the silicon substrate is a part of a PN junction interface, and incident light can be reflected and refracted for multiple times on the surface by forming a good textured structure, so that the optical path is prolonged, and photon-generated carriers are increased. Although the conversion efficiency of the existing heterojunction cell is high, due to the fact that parasitic light absorption of amorphous silicon is large and the reflectivity of the textured surface is high (about 10% -12%), the current density of the heterojunction cell is lower than that of other high-efficiency cells, and therefore the improvement of the current density of the heterojunction cell is a very important and feasible scheme for improving the conversion efficiency of the heterojunction cell.
How to reduce the reflectivity of a silicon substrate by optimizing a textured surface so as to improve the current density and the conversion efficiency of a heterojunction cell is always the direction of continuous exploration in the field of solar cells.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect of high reflectivity of the silicon substrate of the conventional solar cell, and further provide a preparation method of the semiconductor substrate layer and a preparation method of the solar cell.
The invention provides a preparation method of a semiconductor substrate layer, which comprises the following steps: providing an initial semiconductor substrate layer; carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution; and after the first texturing treatment is carried out, carrying out second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process.
Optionally, the alkaline solution used in the first wool making treatment includes a sodium hydroxide solution or a potassium hydroxide solution.
Optionally, the mass concentration of the alkaline solution is 1-10%.
Optionally, the first texturing treatment is performed at a temperature of 40-80 ℃ for 5-120 minutes.
Optionally, the metal catalytic chemical etching process includes a workpiece plating step, a hole drilling step, a removal step, and a hole expanding step, which are performed in sequence by using a noble metal as an etchant.
Optionally, the plating process includes: and placing the initial semiconductor substrate layer subjected to the first texturing treatment in a mixed solution of a silver-containing solution and a hydrofluoric acid solution, and dispersedly depositing silver particles on the surface of the initial semiconductor substrate layer.
Optionally, the mass concentration of the hydrofluoric acid solution in the workpiece plating step is 0.5% -30%, the mass concentration of silver in the silver-containing solution in the workpiece plating step is 0.0001% -5%, and the volume ratio of the hydrofluoric acid solution to the silver-containing solution in the workpiece plating step is 100-1000.
Optionally, the reaction temperature of the plating step is 5-80 ℃, and the reaction time of the plating step is 10-1000 seconds.
Optionally, the hole drilling step includes: and placing the initial semiconductor substrate layer after the workpiece plating step into a mixed solution of hydrofluoric acid solution and hydrogen peroxide solution, and forming a hole suede on the surface of the initial semiconductor substrate layer.
Optionally, the mass concentration of the hydrofluoric acid solution in the hole digging step is 1% to 50%, the mass concentration of the hydrogen peroxide solution in the hole digging step is 1% to 50%, and the volume ratio of the hydrofluoric acid solution to the hydrogen peroxide solution in the hole digging step is 0.1 to 20.
Optionally, the reaction temperature of the hole digging step is 10-60 ℃, and the reaction time of the hole digging step is 10-1000 seconds.
Optionally, the removing step includes: and placing the initial semiconductor substrate layer after the hole digging step into a mixed solution of hydrogen peroxide solution and ammonia water, and removing silver particles remained on the surface of the initial semiconductor substrate layer.
Optionally, the mass concentration of the hydrogen peroxide solution in the removing step is 1% to 25%, the mass concentration of the ammonia water in the removing step is 1% to 30%, and the volume ratio of the hydrogen peroxide solution to the ammonia water in the removing step is 0.1 to 10.
Optionally, the reaction temperature of the removing step is 5 to 60 ℃, and the reaction time of the removing step is 10 to 1000 seconds.
Optionally, the reaming process includes: and placing the initial semiconductor substrate layer after the step of removing in a mixed solution of hydrofluoric acid solution and nitric acid solution, expanding holes formed on the initial semiconductor substrate layer and forming an inverted pyramid textured surface.
Optionally, the mass concentration of the hydrofluoric acid solution in the hole expanding step is 5% to 40%, the mass concentration of the nitric acid solution in the hole expanding step is 5% to 60%, and the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the hole expanding step is 0.1 to 10.
Optionally, the reaction temperature in the hole expanding step is 5 to 60 ℃, and the reaction time in the hole expanding step is 10 to 1000 seconds.
Optionally, before the step of performing the first texturing treatment on the surface of the initial semiconductor substrate layer by using an alkaline solution, the method further includes: and removing the damaged layer on the surface of the initial semiconductor substrate layer.
Optionally, after the step of performing the second texturing processing on the surface of the initial semiconductor substrate layer by using a metal-catalyzed chemical etching process, the method further includes: and cleaning the surface of the initial semiconductor substrate layer.
The invention also provides a preparation method of the solar cell, which comprises the following steps: and forming a semiconductor substrate layer, wherein the semiconductor substrate layer is formed by adopting the preparation method of the semiconductor substrate layer.
Optionally, the method further includes: forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on one side surface of the first intrinsic passivation layer, which is far away from the semiconductor substrate layer; and forming a second doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic passivation layer.
The technical scheme of the invention has the following advantages:
the preparation method of the semiconductor substrate layer comprises the following steps: providing an initial semiconductor substrate layer; carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution; and after the first texturing treatment is carried out, carrying out second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process. If the reflectivity of the textured surface formed on the semiconductor substrate layer by directly adopting the metal catalytic chemical etching process is high, light is not favorably transmitted into the solar cell, and the current density of the solar cell is reduced. According to the invention, on the basis of carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution, the surface of the initial semiconductor substrate layer is subjected to second texturing treatment by adopting a metal catalytic chemical etching process, so that the inverted pyramid textured surface with lower reflectivity can be prepared by adjusting process parameters on the basis of the pyramid of the alkaline textured surface and combining the characteristic of preferential etching on the (100) surface by metal catalytic chemical etching.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart of a method for preparing a semiconductor substrate layer in an embodiment of the invention;
FIG. 2 is an electron micrograph of a surface topography of an initial semiconductor substrate layer after a first texturing process in an embodiment of the present invention;
fig. 3 is an electron microscope photograph of the surface topography of the initial semiconductor substrate layer after sequentially performing the first texturing process and the second texturing process in the embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
Furthermore, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The embodiment provides a preparation method of a semiconductor substrate layer, as shown in fig. 1, including the following steps:
step S1: providing an initial semiconductor substrate layer;
step S2: carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution;
step S3: and after the first texturing treatment is carried out, carrying out second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process.
If a conventional method is adopted, a metal catalytic chemical etching process is directly adopted to form a suede on a semiconductor substrate layer, the reflectivity of the suede is high, and light cannot enter the solar cell easily, so that the current density of the solar cell is reduced. According to the invention, on the basis of carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution, a metal catalytic chemical etching process is adopted to carry out second texturing treatment on the surface of the initial semiconductor substrate layer, and the surface microstructure of the semiconductor silicon wafer is chemically or electrochemically etched by means of the assistance of metal particles, so that a smooth inverted pyramid textured surface with lower reflectivity can be formed on the surface of the initial semiconductor substrate layer, the reflectivity of the textured surface is effectively reduced (the surface reflectivity can be at least reduced to below 10%), and further the current density of the solar cell is improved.
The material of the initial semiconductor substrate layer comprises monocrystalline silicon. In other embodiments, the material of the initial semiconductor substrate layer is other semiconductor materials, such as polysilicon, germanium or silicon germanium.
In this embodiment, the surface of the initial semiconductor substrate layer has a damaged area, which is caused during the cutting of the silicon rod feedstock to form the initial semiconductor substrate layer. Therefore, preferably, before the step of performing the first etching treatment on the surface of the initial semiconductor substrate layer by using the alkaline solution, the method further includes: and removing the damaged layer on the surface of the initial semiconductor substrate layer. The cutting process for forming the initial semiconductor substrate layer can damage the surface, and the etching effect can be influenced if the damaged layer is not removed, so that the damaged layer on the surface of the initial semiconductor substrate layer is preferably removed before etching.
And after removing the damaged layer on the surface of the initial semiconductor substrate layer, carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution. In this embodiment, the alkaline solution used in the first texturing process includes a sodium hydroxide solution or a potassium hydroxide solution. In one embodiment, the alkaline solution has a mass concentration of 1% to 10%, such as 1%, 2%, 5%, or 10%. In one embodiment, the first texturing process is performed at a temperature of 40 degrees celsius to 80 degrees celsius, such as 40 degrees celsius, 50 degrees celsius, 60 degrees celsius, 70 degrees celsius, or 80 degrees celsius, and a processing time of 5 minutes to 120 minutes, such as 5 minutes, 10 minutes, 30 minutes, 60 minutes, 80 minutes, 100 minutes, or 120 minutes. The first texturing process may form a textured surface with an anti-reflection function on the surface of the initial semiconductor substrate layer, but the reflectivity is high, about 12%.
And after the step of the first texturing treatment, cleaning the residual corrosive liquid on the texturing surface, and carrying out second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process. In this embodiment, the metal-catalyzed chemical etching process includes a step of plating a workpiece, a step of drilling a hole, a step of removing the workpiece, and a step of expanding the hole in sequence by using a noble metal as an etchant. A specific metal-catalyzed chemical etching process is described in detail below with silver as an example of a noble metal.
In this embodiment, the workpiece plating process includes: and placing the initial semiconductor substrate layer subjected to the first texturing treatment in a mixed solution of a silver-containing solution and a hydrofluoric acid solution, and dispersedly depositing silver particles on the surface of the initial semiconductor substrate layer. In one embodiment, the hydrofluoric acid solution in the plating step has a mass concentration of 0.5% to 30%, such as 0.5%, 1%, 5%, 10%, 20% or 30%, the silver-containing solution in the plating step has a mass concentration of 0.0001% to 5%, such as 0.0001%, 0.001%, 0.005%, 0.01%, 0.05%, 0.1%, 0.5%, 1% or 5%, and the volume ratio of the hydrofluoric acid solution to the silver-containing solution in the plating step is 100-1000, such as 100, 200, 400, 600, 800 or 1000; preferably, the reaction temperature of the plating step is 5 to 80 degrees celsius, such as 5, 10, 20, 40, 60 or 80 degrees celsius, and the reaction time of the plating step is 10 to 1000 seconds, such as 10, 50, 100, 200, 400, 600, 800 or 1000 seconds.
In this embodiment, the hole drilling step includes: and placing the initial semiconductor substrate layer after the workpiece plating step into a mixed solution of hydrofluoric acid solution and hydrogen peroxide solution, and forming a hole suede on the surface of the initial semiconductor substrate layer. And in the hole digging step, the silicon of the initial semiconductor substrate is electrochemically etched under the deposited silver particles by using a mixed solution of a hydrofluoric acid solution and a hydrogen peroxide solution, and the silver particles move downwards by using self gravity to form holes at original positions before descending. In one embodiment, the hydrofluoric acid solution in the hole-drilling step has a mass concentration of 1% to 50%, such as 1%, 5%, 10%, 20%, 30%, 40% or 50%, and the hydrogen peroxide solution in the hole-drilling step has a mass concentration of 1% to 50%, such as 1%, 5%, 10%, 20%, 30%, 40% or 50%, and the volume ratio of the hydrofluoric acid solution to the hydrogen peroxide solution in the hole-drilling step is 0.1 to 20, such as 0.1, 0.5, 1, 5, 10 or 20; preferably, the reaction temperature of the hole-drilling step is 10 degrees celsius to 60 degrees celsius, such as 10 degrees celsius, 20 degrees celsius, 30 degrees celsius, 40 degrees celsius, 50 degrees celsius, or 60 degrees celsius, and the reaction time of the hole-drilling step is 10 seconds to 1000 seconds, such as 10 seconds, 50 seconds, 100 seconds, 200 seconds, 400 seconds, 600 seconds, 800 seconds, or 1000 seconds.
In this embodiment, the removing step includes: and placing the initial semiconductor substrate layer after the hole digging step into a mixed solution of hydrogen peroxide solution and ammonia water, and removing silver particles remained on the surface of the initial semiconductor substrate layer, namely removing all silver particles after the holes are formed. The silver particles can be dissolved in a mixed solution of hydrogen peroxide solution and ammonia water to form silver-ammonia complex ions, so that the silver-ammonia complex ions can be removed; and the mixed solution of the hydrogen peroxide solution and the ammonia water cannot corrode the initial semiconductor substrate, and cannot affect the formed holes. In one embodiment, the mass concentration of the hydrogen peroxide solution in the removing step is 1% to 25%, such as 1%, 5%, 10%, 15%, 20% or 25%, the mass concentration of the ammonia water in the removing step is 1% to 30%, such as 1%, 5%, 10%, 15%, 20%, 25% or 30%, and the volume ratio of the hydrogen peroxide solution to the ammonia water in the removing step is 0.1 to 10, such as 0.1, 0.5, 1, 5 or 10; preferably, the reaction temperature of the removing step is 5 degrees celsius to 60 degrees celsius, such as 5 degrees celsius, 10 degrees celsius, 20 degrees celsius, 30 degrees celsius, 40 degrees celsius, 50 degrees celsius, or 60 degrees celsius, and the reaction time of the removing step is 10 seconds to 1000 seconds, such as 10 seconds, 50 seconds, 100 seconds, 200 seconds, 400 seconds, 600 seconds, 800 seconds, or 1000 seconds.
In this embodiment, the reaming process includes: and placing the initial semiconductor substrate layer after the step of removing in a mixed solution of hydrofluoric acid solution and nitric acid solution, and expanding the holes formed on the initial semiconductor substrate layer and forming the inverted pyramid suede by reasonably controlling the process parameters of the reaming solution. By adjusting parameters of the hole expanding process (such as solution ratios of hydrofluoric acid solution and nitric acid solution, reaction time and reaction temperature), the size of the pile face hole in the initial semiconductor substrate layer can be adjusted. In one embodiment, the hydrofluoric acid solution in the hole expanding step has a mass concentration of 5% to 40%, such as 5%, 10%, 20%, 30%, or 40%, the nitric acid solution in the hole expanding step has a mass concentration of 5% to 60%, such as 5%, 10%, 20%, 30%, 40%, 50%, or 60%, and the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the hole expanding step is 0.1 to 10, such as 0.1, 0.5, 1, 5, or 10; preferably, the reaction temperature of the reaming step is 5-60 degrees celsius, such as 5, 10, 20, 30, 40, 50 or 60 degrees celsius, and the reaction time of the reaming step is 10-1000 seconds, such as 10, 50, 100, 200, 400, 600, 800 or 1000 seconds.
It should be understood here that other noble metals, such as copper (Cu) or gold (Au), may be used in addition to the silver particles exemplified above, except for differences in the process parameters for forming the pores and the effect of the formation, and also in terms of the cost of the noble metal and the ease of subsequent cleaning.
On the basis of forming a suede with an antireflection function after the first texturing treatment, the second texturing treatment is carried out by adopting a metal catalytic chemical etching process, so that a honeycomb inverted pyramid structure suede can be prepared, secondary reflection of light and reflection above secondary can be facilitated, the reflectivity is reduced to about 8%, the solar cell is prepared by adopting the semiconductor substrate layer, the short-circuit current can be improved, and the photoelectric conversion efficiency of the cell can be improved.
The pyramid texture surface formed after the first texturing treatment is shown in fig. 2, and the cellular inverted pyramid texture surface formed after the second texturing treatment is shown in fig. 3. Silver particles in the second texturing treatment are preferentially deposited at the bottom of the pyramid, hole digging after deposition is mainly carried out by means of electrochemical reaction (namely reaction is promoted by electrons and other processes in the reaction process), hole digging is carried out on the surface by means of mixed liquid of hydrofluoric acid solution and hydrogen peroxide solution, meanwhile, the silver particles sink by means of self gravity, and holes are formed in the original positions of the silver particles before the silver particles do not descend. And finally forming a honeycomb inverted pyramid structured suede due to different hole digging speeds in different crystal face directions.
In this embodiment, after the step of performing the second texturing process on the surface of the initial semiconductor substrate layer by using the metal catalytic chemical etching process, the method further includes: and cleaning the surface of the initial semiconductor substrate layer. Organic matters, metals and residual ions on the initial semiconductor substrate layer can be removed through cleaning.
Example 2
The embodiment provides a method for preparing a solar cell, which comprises the following steps: and forming a semiconductor substrate layer, wherein the semiconductor substrate layer is formed by adopting the preparation method of the semiconductor substrate layer. A textured structure is formed on the surface of the semiconductor substrate layer, the textured structure is in a micron-scale, and only a very thin part is formed in the layered structure of the solar cell. In general, the thickness dimension of the solar cell is 10000 times to 100000 times the thickness dimension of the textured structure.
Optionally, the method further includes: forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on one side surface of the first intrinsic passivation layer, which is far away from the semiconductor substrate layer; and forming a second doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic passivation layer.
To confirm the effects of the present example, electrical performance tests were performed on the cells of the control group and the test group using different texturing methods.
Providing a control group cell piece, wherein the forming process of the control group cell piece comprises the following steps: providing an initial semiconductor substrate layer; carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by using an alkaline solution to obtain a semiconductor substrate layer; forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the first intrinsic passivation layer; forming a second doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic passivation layer; forming a first transparent conductive oxide layer on the surface of one side, away from the semiconductor substrate layer, of the first doped semiconductor layer; forming a second transparent conductive oxide layer on the surface of one side, away from the semiconductor substrate layer, of the second doped semiconductor layer; forming a first gate electrode on the surface of one side, away from the semiconductor substrate layer, of the first transparent conductive oxide layer; and forming a second gate electrode on the surface of one side, away from the semiconductor substrate layer, of the second transparent conductive oxide layer.
Providing a test battery piece, wherein the forming process of the test battery piece comprises the following steps: providing an initial semiconductor substrate layer; carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution; after the first texturing treatment is carried out, carrying out second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process to obtain a semiconductor substrate layer; forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the first intrinsic passivation layer; forming a second doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic passivation layer; forming a first transparent conductive oxide layer on the surface of one side, away from the semiconductor substrate layer, of the first doped semiconductor layer; forming a second transparent conductive oxide layer on the surface of one side, away from the semiconductor substrate layer, of the second doped semiconductor layer; forming a first gate electrode on the surface of one side, away from the semiconductor substrate layer, of the first transparent conductive oxide layer; and forming a second gate electrode on the surface of one side, away from the semiconductor substrate layer, of the second transparent conductive oxide layer.
Respectively recording the open-circuit voltage V of the comparison battery piece and the test battery piece OC Short circuit current density J SC Fill factor FF and photoelectric conversion efficiency Eta, the specific parameter variations are shown in table 1 below.
Table 1 electrical performance parameters of control and test battery cells
| V OC (mV) | J SC (A/cm 2 ) | FF(％) | Eta(％) | |
| Control group battery piece | 746 | 10.43 | 84.8 | 24.07 |
| Testing battery pack | 744 | 10.65 | 84.7 | 24.47 |
As can be seen from the comparison of the electrical performance parameters of the control group cell and the test group cell in Table 1, the short-circuit current density J of the control group cell SC Less than the short-circuit current density J of the battery cell SC And the photoelectric conversion efficiency Eta of the comparison group battery piece is smaller than that Eta of the test group battery piece. The preparation of the test group battery piece is different from that of the comparison group battery piece in that the test group battery piece is subjected to second texturing after the first texturing. According to the data, the surface of the initial semiconductor substrate layer is subjected to the second texturing treatment by adopting the metal catalytic chemical etching process on the basis of the first texturing treatment, so that the battery piece can obtain better electrical performance, and the semiconductor substrate layer of the battery piece has lower reflectivity.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications derived therefrom are intended to be within the scope of the invention.
Claims (10)
1. A method for preparing a semiconductor substrate layer is characterized by comprising the following steps:
providing an initial semiconductor substrate layer;
carrying out first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution;
and after the first texturing treatment is carried out, carrying out second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process.
2. The method for preparing the semiconductor substrate layer according to claim 1, wherein the alkaline solution used in the first texturing process comprises a sodium hydroxide solution or a potassium hydroxide solution;
preferably, the mass concentration of the alkaline solution is 1-10%;
preferably, the temperature adopted by the first texturing treatment is 40-80 ℃, and the treatment time is 5-120 minutes.
3. The method for preparing the semiconductor substrate layer according to claim 1, wherein the metal-catalyzed chemical etching process comprises a plating step, a hole digging step, a removing step and a hole expanding step which are sequentially performed by using a noble metal as an etchant.
4. The method of making a semiconductor substrate layer of claim 3, wherein the plating process step comprises: placing the initial semiconductor substrate layer subjected to the first texturing treatment in a mixed solution of a silver-containing solution and a hydrofluoric acid solution, and dispersedly depositing silver particles on the surface of the initial semiconductor substrate layer;
preferably, the mass concentration of the hydrofluoric acid solution in the workpiece plating step is 0.5% -30%, the mass concentration of silver in the silver-containing solution in the workpiece plating step is 0.0001% -5%, and the volume ratio of the hydrofluoric acid solution to the silver-containing solution in the workpiece plating step is 100-;
preferably, the reaction temperature of the plating work step is 5-80 ℃, and the reaction time of the plating work step is 10-1000 seconds.
5. A method of forming a semiconductor substrate layer as defined in claim 3, wherein the hole-drilling step comprises: placing the initial semiconductor substrate layer after the workpiece plating step into a mixed solution of hydrofluoric acid solution and hydrogen peroxide solution, and forming a hole suede on the surface of the initial semiconductor substrate layer;
preferably, the mass concentration of the hydrofluoric acid solution in the hole-digging step is 1% -50%, the mass concentration of the hydrogen peroxide solution in the hole-digging step is 1% -50%, and the volume ratio of the hydrofluoric acid solution to the hydrogen peroxide solution in the hole-digging step is 0.1-20;
preferably, the reaction temperature of the hole digging step is 10-60 ℃, and the reaction time of the hole digging step is 10-1000 seconds.
6. A method of making a semiconductor substrate layer as recited in claim 3, wherein the removing step comprises: placing the initial semiconductor substrate layer after the hole digging step into a mixed solution of hydrogen peroxide solution and ammonia water, and removing silver particles remained on the surface of the initial semiconductor substrate layer;
preferably, the mass concentration of the hydrogen peroxide solution in the removing step is 1-25%, the mass concentration of the ammonia water in the removing step is 1-30%, and the volume ratio of the hydrogen peroxide solution to the ammonia water in the removing step is 0.1-10;
preferably, the reaction temperature in the removing step is 5-60 ℃, and the reaction time in the removing step is 10-1000 seconds.
7. A method of making a semiconductor substrate layer as recited in claim 3, wherein the step of reaming comprises: placing the initial semiconductor substrate layer after the step of removing in a mixed solution of hydrofluoric acid solution and nitric acid solution, expanding holes formed in the initial semiconductor substrate layer and forming an inverted pyramid suede;
preferably, the mass concentration of the hydrofluoric acid solution in the hole expanding step is 5-40%, the mass concentration of the nitric acid solution in the hole expanding step is 5-60%, and the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the hole expanding step is 0.1-10;
preferably, the reaction temperature of the reaming step is 5-60 ℃, and the reaction time of the reaming step is 10-1000 seconds.
8. The method for preparing a semiconductor substrate layer according to claim 1, wherein before the step of performing the first texturing process on the surface of the initial semiconductor substrate layer by using an alkaline solution, the method further comprises: and removing the damaged layer on the surface of the initial semiconductor substrate layer.
9. A method of making a semiconductor substrate layer as recited in any one of claims 1-8, wherein after the step of performing a second texturing process on the surface of the initial semiconductor substrate layer using a metal-catalyzed chemical etching process, further comprising: and cleaning the surface of the initial semiconductor substrate layer.
10. A method for manufacturing a solar cell, comprising:
forming a semiconductor substrate layer, wherein the semiconductor substrate layer is formed by adopting the preparation method of the semiconductor substrate layer according to any one of claims 1 to 9;
further comprising at least: forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the first intrinsic passivation layer; and forming a second doped semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic passivation layer.
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