CN114792740B - Preparation method of semiconductor substrate layer and preparation method of solar cell - Google Patents
Preparation method of semiconductor substrate layer and preparation method of solar cell Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/08—Etching
- C30B33/10—Etching in solutions or melts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
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- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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Abstract
The invention relates to the technical field of solar cells, and particularly provides a semiconductor substrate layer and a preparation method of a solar cell. The preparation method of the semiconductor substrate layer comprises the following steps: providing an initial semiconductor substrate layer; performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution; and after the first texturing treatment, performing a second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process. According to the invention, on the basis of performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution, performing second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process, and on the basis of the pyramid of the alkaline texturing surface, the inverted pyramid texturing surface with lower reflectivity can be prepared by combining the characteristic of preferential etching of metal catalytic etching and adjusting process parameters.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a semiconductor substrate layer and a preparation method of a solar cell.
Background
Solar cells have evolved rapidly in recent years, being a device that converts solar radiation energy directly or indirectly into electrical energy through the photoelectric or photochemical effect. Heterojunction cells are an important solar cell type, and the photoelectric conversion efficiency of the heterojunction cells is improved by changing the performance of PN junctions. In addition, the heterojunction battery has the characteristics of good temperature coefficient, capability of generating electricity on two sides, low process temperature, high photoelectric conversion efficiency and the like, and is a solar battery technology with very high market competitiveness.
The texturing is an important process for forming a good substrate by a silicon wafer, and the excellent and efficient silicon substrate is formed, so that the photoelectric conversion efficiency of the solar cell can be improved. In the solar cell structure, the silicon substrate is a part of a PN junction interface, so that incident light can be reflected and refracted on the surface for multiple times by forming a good suede structure, the optical path is prolonged, and photo-generated carriers are increased. At present, though the heterojunction battery has high conversion efficiency, the parasitic light absorption of amorphous silicon is larger, and the reflectivity of the suede per se is also higher (about 10% -12%), so that the current density of the heterojunction battery is lower than that of other high-efficiency batteries, and therefore, the improvement of the current density of the heterojunction battery is a very important and feasible scheme for improving the conversion efficiency of the heterojunction battery.
How to reduce the reflectivity of the silicon substrate through optimizing the suede, so that the current density and the conversion efficiency of the heterojunction battery are improved, and the method is always the direction of continuous exploration in the field of solar batteries.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect of higher reflectivity of the silicon substrate of the existing solar cell, and further provide a preparation method of the semiconductor substrate layer and a preparation method of the solar cell.
The invention provides a preparation method of a semiconductor substrate layer, which comprises the following steps: providing an initial semiconductor substrate layer; performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution; and after the first texturing treatment, performing a second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process.
Optionally, the alkaline solution used in the first texturing treatment includes sodium hydroxide solution or potassium hydroxide solution.
Optionally, the mass concentration of the alkaline solution is 1% -10%.
Optionally, the temperature adopted in the first texturing treatment is 40-80 ℃ and the treatment time is 5-120 minutes.
Optionally, the metal catalytic chemical etching process comprises a plating process step, a hole digging process step, a removing process step and a hole enlarging process step which are sequentially performed by adopting noble metal as an etchant.
Optionally, the plating step includes: and placing the initial semiconductor substrate layer after the first texturing treatment in a mixed solution of a silver-containing solution and a hydrofluoric acid solution, and dispersing and depositing silver particles on the surface of the initial semiconductor substrate layer.
Optionally, the mass concentration of the hydrofluoric acid solution in the plating process step is 0.5% -30%, the mass concentration of silver in the silver-containing solution in the plating process step is 0.0001% -5%, and the volume ratio of the hydrofluoric acid solution to the silver-containing solution in the plating process step is 100-1000.
Optionally, the reaction temperature of the plating process step is 5-80 ℃, and the reaction time of the plating process step is 10-1000 seconds.
Optionally, the hole digging step includes: and placing the initial semiconductor substrate layer after the plating step in a mixed solution of hydrofluoric acid solution and hydrogen peroxide solution, and forming hole suede on the surface of the initial semiconductor substrate layer.
Optionally, the mass concentration of the hydrofluoric acid solution in the hole digging step is 1% -50%, the mass concentration of the hydrogen peroxide solution in the hole digging step is 1% -50%, and the volume ratio of the hydrofluoric acid solution to the hydrogen peroxide solution in the hole digging step is 0.1-20.
Optionally, the reaction temperature of the hole digging step is 10-60 ℃, and the reaction time of the hole digging step is 10-1000 seconds.
Optionally, the removing step includes: and placing the initial semiconductor substrate layer after the hole digging step in a mixed solution of hydrogen peroxide solution and ammonia water, and removing silver particles remained on the surface of the initial semiconductor substrate layer.
Optionally, the mass concentration of the hydrogen peroxide solution in the removing step is 1% -25%, the mass concentration of the ammonia water in the removing step is 1% -30%, and the volume ratio of the hydrogen peroxide solution to the ammonia water in the removing step is 0.1-10.
Optionally, the reaction temperature of the removing step is 5-60 ℃, and the reaction time of the removing step is 10-1000 seconds.
Optionally, the reaming step includes: and placing the initial semiconductor substrate layer after the step of removing in a mixed solution of hydrofluoric acid solution and nitric acid solution, expanding holes formed on the initial semiconductor substrate layer and forming inverted pyramid suede.
Optionally, the mass concentration of the hydrofluoric acid solution in the reaming step is 5% -40%, the mass concentration of the nitric acid solution in the reaming step is 5% -60%, and the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the reaming step is 0.1-10.
Optionally, the reaction temperature of the reaming step is 5-60 ℃, and the reaction time of the reaming step is 10-1000 seconds.
Optionally, before the step of performing the first texturing treatment on the surface of the initial semiconductor substrate layer with an alkaline solution, the method further includes: and removing the damaged layer on the surface of the initial semiconductor substrate layer.
Optionally, after the step of performing the second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process, the method further includes: and cleaning the surface of the initial semiconductor substrate layer.
The invention also provides a preparation method of the solar cell, which comprises the following steps: and forming a semiconductor substrate layer, wherein the semiconductor substrate layer is formed by adopting the preparation method of the semiconductor substrate layer.
Optionally, the method further comprises: forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side of the first intrinsic passivation layer, which faces away from the semiconductor substrate layer; and forming a second doped semiconductor layer on the surface of one side of the second intrinsic passivation layer, which faces away from the semiconductor substrate layer.
The technical scheme of the invention has the following advantages:
the preparation method of the semiconductor substrate layer comprises the following steps: providing an initial semiconductor substrate layer; performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution; and after the first texturing treatment, performing a second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process. If the suede reflectivity formed by directly adopting a metal catalytic chemical etching process on the semiconductor substrate layer is relatively high, light rays are not easy to enter the solar cell, and the current density of the solar cell is reduced. According to the invention, the surface of the initial semiconductor substrate layer is subjected to the second texturing treatment by adopting the metal catalytic chemical etching process on the basis of the first texturing treatment by adopting the alkaline solution, so that the inverted pyramid textured surface with lower reflectivity can be prepared by combining the characteristic of preferential etching of the metal catalytic chemical etching on the (100) surface on the basis of the pyramid of the alkaline textured surface and adjusting the process parameters.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for fabricating a semiconductor substrate layer according to an embodiment of the present invention;
FIG. 2 is an electron micrograph of the surface morphology of an initial semiconductor substrate layer after a first texturing process in accordance with an embodiment of the present invention;
fig. 3 is an sem photograph of the surface morphology of an initial semiconductor substrate layer after sequentially performing a first texturing process and a second texturing process in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
The embodiment provides a method for preparing a semiconductor substrate layer, as shown in fig. 1, comprising the following steps:
step S1: providing an initial semiconductor substrate layer;
step S2: performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution;
step S3: and after the first texturing treatment, performing a second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process.
If a conventional method is adopted, a metal catalytic chemical etching process is directly adopted on the semiconductor substrate layer to form a suede, the reflectivity of the suede is high, light is not easy to enter the solar cell, and the current density of the solar cell is reduced. According to the invention, on the basis of performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting an alkaline solution, performing second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process, and performing chemical or electrochemical etching on the surface microstructure of the semiconductor silicon wafer by means of metal particles, so that a rounded inverted pyramid textured surface with lower reflectivity can be formed on the surface of the initial semiconductor substrate layer, the reflectivity of the textured surface is effectively reduced (at least the surface reflectivity can be reduced to below 10%), and the current density of the solar cell is further improved.
The material of the initial semiconductor substrate layer comprises monocrystalline silicon. In other embodiments, the material of the initial semiconductor substrate layer is other semiconductor materials, such as polysilicon, germanium, or silicon germanium.
In this embodiment, the surface of the initial semiconductor substrate layer has a damaged region that is caused during the process of cutting the silicon rod stock to form the initial semiconductor substrate layer. It is therefore preferred that before the step of subjecting the surface of the initial semiconductor substrate layer to the first texturing treatment with an alkaline solution, the method further comprises: and removing the damaged layer on the surface of the initial semiconductor substrate layer. The dicing process for forming the initial semiconductor substrate layer may damage the surface, and if the damaged layer is not removed, the effect of texturing is affected, so that the damaged layer on the surface of the initial semiconductor substrate layer is preferably removed before texturing.
And after removing the damaged layer on the surface of the initial semiconductor substrate layer, performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution. In this embodiment, the alkaline solution used in the first texturing process includes a sodium hydroxide solution or a potassium hydroxide solution. In one embodiment, the alkaline solution has a mass concentration of 1% -10%, such as 1%, 2%, 5% or 10%. In one embodiment, the first texturing process employs a temperature of 40 degrees celsius-80 degrees celsius, such as 40 degrees celsius, 50 degrees celsius, 60 degrees celsius, 70 degrees celsius, or 80 degrees celsius, and a processing time of 5 minutes-120 minutes, such as 5 minutes, 10 minutes, 30 minutes, 60 minutes, 80 minutes, 100 minutes, or 120 minutes. The first texturing process may form a textured surface having an anti-reflection function on the surface of the initial semiconductor substrate layer, but has a high reflectivity of about 12%.
After the step of the first texturing treatment, cleaning away the residual corrosive liquid on the textured surface, and carrying out a second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process. In this embodiment, the metal-catalyzed chemical etching process includes a plating step, a hole digging step, a removing step and a hole enlarging step performed sequentially by using noble metal as an etchant. Specific metal-catalyzed chemical etching processes are described in detail below using silver as an example of a noble metal.
In this embodiment, the plating step includes: and placing the initial semiconductor substrate layer after the first texturing treatment in a mixed solution of a silver-containing solution and a hydrofluoric acid solution, and dispersing and depositing silver particles on the surface of the initial semiconductor substrate layer. In one embodiment, the hydrofluoric acid solution in the plating step has a mass concentration of 0.5% -30%, such as 0.5%, 1%, 5%, 10%, 20% or 30%, the silver in the silver-containing solution in the plating step has a mass concentration of 0.0001% -5%, such as 0.0001%, 0.001%, 0.005%, 0.01%, 0.05%, 0.1%, 0.5%, 1% or 5%, and the volume ratio of the hydrofluoric acid solution to the silver-containing solution in the plating step is 100-1000, such as 100, 200, 400, 600, 800 or 1000; preferably, the reaction temperature of the plating step is 5 degrees celsius to 80 degrees celsius, for example 5 degrees celsius, 10 degrees celsius, 20 degrees celsius, 40 degrees celsius, 60 degrees celsius or 80 degrees celsius, and the reaction time of the plating step is 10 seconds to 1000 seconds, for example 10 seconds, 50 seconds, 100 seconds, 200 seconds, 400 seconds, 600 seconds, 800 seconds or 1000 seconds.
In this embodiment, the hole digging step includes: and placing the initial semiconductor substrate layer after the plating step in a mixed solution of hydrofluoric acid solution and hydrogen peroxide solution, and forming hole suede on the surface of the initial semiconductor substrate layer. And in the hole digging step, the mixed solution of the hydrofluoric acid solution and the hydrogen peroxide solution is utilized to carry out electrochemical corrosion on the silicon of the initial semiconductor substrate under the condition that silver particles are deposited, and the silver particles downwards move by self gravity to form holes at the original position before the silver particles are not lowered. In one embodiment, the hydrofluoric acid solution in the hole digging step has a mass concentration of 1% -50%, such as 1%, 5%, 10%, 20%, 30%, 40% or 50%, the hydrogen peroxide solution in the hole digging step has a mass concentration of 1% -50%, such as 1%, 5%, 10%, 20%, 30%, 40% or 50%, and the volume ratio of the hydrofluoric acid solution and the hydrogen peroxide solution in the hole digging step is 0.1-20, such as 0.1, 0.5, 1, 5, 10 or 20; preferably, the reaction temperature of the hole digging step is 10 degrees celsius-60 degrees celsius, for example 10 degrees celsius, 20 degrees celsius, 30 degrees celsius, 40 degrees celsius, 50 degrees celsius or 60 degrees celsius, and the reaction time of the hole digging step is 10 seconds-1000 seconds, for example 10 seconds, 50 seconds, 100 seconds, 200 seconds, 400 seconds, 600 seconds, 800 seconds or 1000 seconds.
In this embodiment, the removing step includes: and placing the initial semiconductor substrate layer after the hole digging step in a mixed solution of hydrogen peroxide solution and ammonia water, and removing silver particles remained on the surface of the initial semiconductor substrate layer, namely removing all silver particles after holes are formed. Silver particles can be dissolved in a mixed solution of hydrogen peroxide solution and ammonia water to form silver ammine ions, so that silver ammine ions are removed; and, the mixed solution of hydrogen peroxide solution and ammonia water will not corrode the initial semiconductor substrate, and will not affect the formed holes. In one embodiment, the mass concentration of the hydrogen peroxide solution in the removal step is 1% -25%, such as 1%, 5%, 10%, 15%, 20% or 25%, the mass concentration of the aqueous ammonia in the removal step is 1% -30%, such as 1%, 5%, 10%, 15%, 20%, 25% or 30%, and the volume ratio of the hydrogen peroxide solution to the aqueous ammonia in the removal step is 0.1-10, such as 0.1, 0.5, 1, 5 or 10; preferably, the reaction temperature of the removing step is 5 degrees celsius-60 degrees celsius, for example 5 degrees celsius, 10 degrees celsius, 20 degrees celsius, 30 degrees celsius, 40 degrees celsius, 50 degrees celsius or 60 degrees celsius, and the reaction time of the removing step is 10 seconds-1000 seconds, for example 10 seconds, 50 seconds, 100 seconds, 200 seconds, 400 seconds, 600 seconds, 800 seconds or 1000 seconds.
In this embodiment, the reaming step includes: and placing the initial semiconductor substrate layer after the step of removing in a mixed solution of hydrofluoric acid solution and nitric acid solution, and expanding holes formed on the initial semiconductor substrate layer and forming inverted pyramid suede by reasonably controlling technological parameters of a reaming solution. The adjustment of the size of the pile holes on the initial semiconductor substrate layer can be achieved by adjusting the reaming process parameters (e.g., solution ratio of hydrofluoric acid solution, nitric acid solution, and reaction time and reaction temperature). In one embodiment, the mass concentration of the hydrofluoric acid solution in the reaming process step is 5% -40%, such as 5%, 10%, 20%, 30% or 40%, the mass concentration of the nitric acid solution in the reaming process step is 5% -60%, such as 5%, 10%, 20%, 30%, 40%, 50% or 60%, and the volume ratio of the hydrofluoric acid solution and the nitric acid solution in the reaming process step is 0.1-10, such as 0.1, 0.5, 1, 5 or 10; preferably, the reaction temperature of the reaming step is 5 degrees celsius-60 degrees celsius, for example 5 degrees celsius, 10 degrees celsius, 20 degrees celsius, 30 degrees celsius, 40 degrees celsius, 50 degrees celsius or 60 degrees celsius, and the reaction time of the reaming step is 10 seconds-1000 seconds, for example 10 seconds, 50 seconds, 100 seconds, 200 seconds, 400 seconds, 600 seconds, 800 seconds or 1000 seconds.
It should be understood here that other noble metals, such as copper (Cu) or gold (Au), may be used in addition to the silver particles exemplified above, except that there may be differences in the process parameters and effects of forming the holes, and further, the cost of the noble metal and the ease of subsequent cleaning may be related.
On the basis of forming the suede with the anti-reflection function after the first suede treatment, the second suede treatment is performed by adopting a metal catalytic chemical etching process, so that the suede with the honeycomb inverted pyramid structure can be prepared, the secondary reflection and more than secondary reflection of light rays are facilitated, the reflectivity is reduced to about 8%, and the solar cell is prepared by adopting the semiconductor substrate layer, so that the short-circuit current is facilitated to be improved, and the photoelectric conversion efficiency of the cell is improved.
The pyramid texture surface formed after the first texturing treatment is shown in fig. 2, and the honeycomb inverted pyramid structure texture surface formed after the second texturing treatment is shown in fig. 3. Silver particles in the second texturing treatment are preferentially deposited at the bottoms of the pyramids, the hole digging after deposition is mainly carried out by means of electrochemical reaction (namely, the reaction is promoted by an electronic process in the reaction process, and the like), the hole digging is carried out on the surfaces by utilizing mixed solution of hydrofluoric acid solution and hydrogen peroxide solution, meanwhile, the silver particles sink by means of self gravity, and holes are formed in situ before the silver particles do not drop. Due to different hole digging speeds in different crystal face directions, the honeycomb-shaped suede with the inverted pyramid structure is finally formed.
In this embodiment, after the step of performing the second texturing treatment on the surface of the initial semiconductor substrate layer by using the metal catalytic chemical etching process, the method further includes: and cleaning the surface of the initial semiconductor substrate layer. The organic matters, metals and residual ions on the initial semiconductor substrate layer can be removed by cleaning.
Example 2
The embodiment provides a method for manufacturing a solar cell, which comprises the following steps: and forming a semiconductor substrate layer, wherein the semiconductor substrate layer is formed by adopting the preparation method of the semiconductor substrate layer. A textured structure is formed on the surface of the semiconductor substrate layer, which is in the order of micrometers, and is only a very thin portion of the layered structure of the solar cell. In general, the thickness dimension of the solar cell is 10000 to 100000 times the thickness dimension of the suede structure.
Optionally, the method further comprises: forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side of the first intrinsic passivation layer, which faces away from the semiconductor substrate layer; and forming a second doped semiconductor layer on the surface of one side of the second intrinsic passivation layer, which faces away from the semiconductor substrate layer.
To demonstrate the effect of this example, electrical performance tests were performed on the cells of the control and test groups using different texturing methods.
Providing a control group of battery pieces, wherein the formation process of the control group of battery pieces comprises the following steps: providing an initial semiconductor substrate layer; performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution to obtain a semiconductor substrate layer; forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side of the first intrinsic passivation layer, which is away from the semiconductor substrate layer; forming a second doped semiconductor layer on the surface of one side of the second intrinsic passivation layer, which is away from the semiconductor substrate layer; forming a first transparent conductive oxide layer on the surface of one side of the first doped semiconductor layer, which is far away from the semiconductor substrate layer; forming a second transparent conductive oxide layer on the surface of one side of the second doped semiconductor layer, which is far away from the semiconductor substrate layer; forming a first gate electrode on the surface of one side of the first transparent conductive oxide layer, which is away from the semiconductor substrate layer; and forming a second gate electrode on the surface of one side of the second transparent conductive oxide layer, which faces away from the semiconductor substrate layer.
Providing a test group battery piece, wherein the forming process of the test group battery piece comprises the following steps: providing an initial semiconductor substrate layer; performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution; after the first texturing treatment, performing a second texturing treatment on the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process to obtain a semiconductor substrate layer; forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side of the first intrinsic passivation layer, which is away from the semiconductor substrate layer; forming a second doped semiconductor layer on the surface of one side of the second intrinsic passivation layer, which is away from the semiconductor substrate layer; forming a first transparent conductive oxide layer on the surface of one side of the first doped semiconductor layer, which is far away from the semiconductor substrate layer; forming a second transparent conductive oxide layer on the surface of one side of the second doped semiconductor layer, which is far away from the semiconductor substrate layer; forming a first gate electrode on the surface of one side of the first transparent conductive oxide layer, which is away from the semiconductor substrate layer; and forming a second gate electrode on the surface of one side of the second transparent conductive oxide layer, which faces away from the semiconductor substrate layer.
The open circuit voltage V of the control group battery piece and the test group battery piece are recorded respectively OC Short-circuit current density J SC The fill factor FF and the photoelectric conversion efficiency Eta, and the specific parameter variations are shown in table 1 below.
Table 1 electrical performance parameters of control and test cells
| V OC (mV) | J SC (A/cm 2 ) | FF(％) | Eta(％) | |
| Control group battery piece | 746 | 10.43 | 84.8 | 24.07 |
| Test group battery piece | 744 | 10.65 | 84.7 | 24.47 |
As can be seen from the comparison of the electrical performance parameters of the control battery cells and the test battery cells in Table 1, the short-circuit current density J of the control battery cells SC Short circuit current density J less than test group battery plate SC The photoelectric conversion efficiency Eta of the control group battery cells is smaller than the photoelectric conversion efficiency Eta of the test group battery cells. The test group battery piece is different from the control group battery piece in preparation condition that the test group battery piece is subjected to second texturing treatment after the first texturing treatment. According to the data, the fact that the surface of the initial semiconductor substrate layer is subjected to the second texturing treatment by adopting the metal catalytic chemical etching process on the basis of the first texturing treatment is described, the battery piece can obtain better electrical performance, and the semiconductor substrate layer of the battery piece is proved to have lower reflectivity to a certain extent.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (12)
1. A method of fabricating a semiconductor substrate layer, comprising:
providing an initial semiconductor substrate layer;
removing the damaged layer on the surface of the initial semiconductor substrate layer;
after removing a damaged layer on the surface of an initial semiconductor substrate layer, performing first texturing treatment on the surface of the initial semiconductor substrate layer by adopting alkaline solution; the alkaline solution adopted by the first texturing treatment comprises sodium hydroxide solution or potassium hydroxide solution; the mass concentration of the alkaline solution is 1% -10%; the temperature adopted in the first texturing treatment is 40-80 ℃ and the treatment time is 5-120 minutes
After the first texturing treatment, performing second texturing treatment on a (100) crystal face of the surface of the initial semiconductor substrate layer by adopting a metal catalytic chemical etching process to form a honeycomb inverted pyramid structure textured surface;
the metal catalysis chemical etching process comprises a plating work step, a hole digging work step, a removing work step and a hole enlarging work step which are sequentially carried out by adopting noble metal as an etching agent; the hole digging process comprises the following steps: placing the initial semiconductor substrate layer after the plating step in a mixed solution of hydrofluoric acid solution and hydrogen peroxide solution, and forming hole suede on the surface of the initial semiconductor substrate layer; the mass concentration of the hydrofluoric acid solution in the hole digging step is 1% -50%, the mass concentration of the hydrogen peroxide solution in the hole digging step is 1% -50%, and the volume ratio of the hydrofluoric acid solution to the hydrogen peroxide solution in the hole digging step is 0.1-20; the reaction temperature of the hole digging step is 10-60 ℃, and the reaction time of the hole digging step is 10-1000 seconds.
2. The method of manufacturing a semiconductor substrate layer according to claim 1, wherein the plating step comprises: and placing the initial semiconductor substrate layer after the first texturing treatment in a mixed solution of a silver-containing solution and a hydrofluoric acid solution, and dispersing and depositing silver particles on the surface of the initial semiconductor substrate layer.
3. The method for producing a semiconductor substrate layer according to claim 2, wherein,
the mass concentration of the hydrofluoric acid solution in the plating process step is 0.5-30%, the mass concentration of silver in the silver-containing solution in the plating process step is 0.0001-5%, and the volume ratio of the hydrofluoric acid solution to the silver-containing solution in the plating process step is 100-1000.
4. The method for producing a semiconductor substrate layer according to claim 2, wherein,
the reaction temperature of the plating process step is 5-80 ℃, and the reaction time of the plating process step is 10-1000 seconds.
5. The method of manufacturing a semiconductor substrate layer according to claim 1, wherein the removing step comprises: and placing the initial semiconductor substrate layer after the hole digging step in a mixed solution of hydrogen peroxide solution and ammonia water, and removing silver particles remained on the surface of the initial semiconductor substrate layer.
6. The method for manufacturing a semiconductor substrate layer according to claim 5, wherein,
the mass concentration of the hydrogen peroxide solution in the removing step is 1-25%, the mass concentration of the ammonia water in the removing step is 1-30%, and the volume ratio of the hydrogen peroxide solution to the ammonia water in the removing step is 0.1-10.
7. The method for manufacturing a semiconductor substrate layer according to claim 5, wherein,
the reaction temperature of the removing step is 5-60 ℃, and the reaction time of the removing step is 10-1000 seconds.
8. The method of manufacturing a semiconductor substrate layer according to claim 1, wherein the reaming step comprises: and placing the initial semiconductor substrate layer after the step of removing in a mixed solution of hydrofluoric acid solution and nitric acid solution, expanding holes formed on the initial semiconductor substrate layer and forming inverted pyramid suede.
9. The method for manufacturing a semiconductor substrate layer according to claim 8, wherein,
the mass concentration of the hydrofluoric acid solution in the reaming process step is 5-40%, the mass concentration of the nitric acid solution in the reaming process step is 5-60%, and the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the reaming process step is 0.1-10.
10. The method for manufacturing a semiconductor substrate layer according to claim 8, wherein,
the reaction temperature of the reaming process step is 5-60 ℃, and the reaction time of the reaming process step is 10-1000 seconds.
11. The method of any of claims 1-10, further comprising, after the step of performing a second texturing process on the surface of the initial semiconductor substrate layer using a metal-catalyzed chemical etching process: and cleaning the surface of the initial semiconductor substrate layer.
12. A method of manufacturing a solar cell, comprising:
forming a semiconductor substrate layer formed using the method for manufacturing a semiconductor substrate layer according to any one of claims 1 to 11;
also at least comprises: forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; forming a first doped semiconductor layer on the surface of one side of the first intrinsic passivation layer, which faces away from the semiconductor substrate layer; and forming a second doped semiconductor layer on the surface of one side of the second intrinsic passivation layer, which faces away from the semiconductor substrate layer.
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