CN114785455A

CN114785455A - Rate de-matching method, device, chip, equipment and storage medium

Info

Publication number: CN114785455A
Application number: CN202210351642.0A
Authority: CN
Inventors: 许日升; 卢会群
Original assignee: Guangzhou Huiruisitong Technology Co Ltd
Current assignee: Guangzhou Huiruisitong Technology Co Ltd
Priority date: 2022-04-02
Filing date: 2022-04-02
Publication date: 2022-07-22

Abstract

The disclosure relates to a rate de-matching method, a rate de-matching device, a rate de-matching chip, a rate de-matching device and a storage medium, and relates to the field of wireless communication. The de-rate matching method comprises the following steps: acquiring first code block data; sending the first code block data to a de-interleaving unit, and acquiring de-interleaved second code block data output by the de-interleaving unit; sending the second code block data to a decoding bit selection unit, wherein the decoding bit selection unit comprises a code block data segmentation subunit, a code block data merging subunit and a code block data filling subunit; in the code block data segmentation subunit, the code block data merging subunit and the code block data filling subunit, performing parallel pipeline processing on the second code block data to obtain third code block data after bit decoding selection; storing the third chunk data into a circular buffer. The present disclosure is directed to solving the problem of long time for de-rate matching processing.

Description

Rate de-matching method, device, chip, equipment and storage medium

Technical Field

The present disclosure relates to the field of wireless communications, and in particular, to a method, an apparatus, a chip, a device, and a storage medium for rate de-matching.

Background

The coding scheme on the PUSCH (physical uplink shared channel, uplink shared channel) of the 5G NR (new radio, global 5G standard) is LDPC (low density parity check code) coding.

Rate matching (Rate matching) refers to that bits on a transport channel are retransmitted (requested) or punctured (punctured) to match the carrying capacity of a physical channel, and the bit Rate required by the transport format is achieved when the channel is mapped.

Rate matching in 5G NR involves two processes: bit selection and interleaving. In communication transmission, error codes can occur due to interference of noise, a small number of error codes can be corrected by error correction, and when a large number of continuous error codes exceed the error correction capability, data cannot be recovered. Interleaving is performed by scattering transmission data, so that the phenomenon that a sudden large number of errors cannot recover data is avoided, and the concentrated sudden errors are scattered after de-interleaving. Bit selection is generally a method of increasing or decreasing the amount of data transmitted by encoded data after encoding for rate matching. The bit selection is to match the encoded data with the allocated time-frequency resources.

De-rate matching is the inverse of rate matching. De-rate matching in 5G NR involves two processes: deinterleaving and bit selection. First, deinterleaving is performed, and then, bit selection is performed. De-interleaving is the inverse of interleaving and is used to spread out the concentrated burst errors. Bit selection is the inverse of bit selection and is used to match the encoded data to the allocated time-frequency resources. The length of the circular buffer is Ncb, the length of data after decoding bit selection coding is E, when E is smaller than Ncb, the data is transmitted by adopting a puncturing or truncation mode, and when E is larger than Ncb, the data is transmitted by adopting a repetition mode.

Disclosure of Invention

In the related art, bit decoding selection is realized in one module, the next code block data b can be processed only after the code block data a is subjected to bit decoding selection, the stream level is low, the processing efficiency in the bit decoding selection process is low, and the time length of rate decoding matching processing is long.

The disclosure provides a method, a device, a chip, equipment and a storage medium for rate de-matching, which are used for solving the problem of long time for rate de-matching processing.

In a first aspect, an embodiment of the present disclosure provides a method for rate de-matching, including:

acquiring first code block data;

sending the first code block data to a de-interleaving unit, and acquiring de-interleaved second code block data output by the de-interleaving unit;

sending the second code block data to a decoding bit selection unit, wherein the decoding bit selection unit comprises a code block data segmentation subunit, a code block data merging subunit and a code block data filling subunit;

in the code block data segmentation subunit, the code block data merging subunit and the code block data filling subunit, performing parallel pipeline processing on the second code block data to obtain third code block data after bit decoding selection;

storing the third chunk data into a circular buffer.

Optionally, the performing, in the code block data segmentation subunit, the code block data merging subunit, and the code block data padding subunit, parallel pipeline processing on the second code block data to obtain third code block data after bit decoding selection includes:

sending the second code block data to the code block data segmentation subunit, and in the code block data segmentation subunit, segmenting the second code block data according to the length of Ncb 'to obtain segmented fourth code block data, wherein the length of the fourth code block data is Ncb'; wherein, the Ncb' length is calculated according to the base map mode and the cyclic factor;

sending the fourth code block data to the code block data merging subunit, merging the fourth code block data in the code block data merging subunit to obtain merged fifth code block data, wherein the length of the fifth code block data is Ncb';

and sending the fifth code block data to the code block data filling subunit, and inserting a saturation value and zero into the fifth code block data in the code block data filling subunit to obtain the filled third code block data.

Optionally, the segmenting, in the code block data segmenting subunit, the second code block data according to the length Ncb' to obtain segmented fourth code block data includes:

acquiring the length of the second code block data;

if the length of the second code block data is smaller than Ncb', zero padding is performed at the tail of the second code block data to obtain one fourth code block data after zero padding;

if the length of the second code block data is equal to Ncb', taking the second code block data as the fourth code block data;

and if the length of the second code block data is greater than Ncb ', segmenting the second code block data according to Ncb ', and performing zero padding on a part, which is less than Ncb ', at the tail of the second code block data to obtain at least two pieces of fourth code block data.

Optionally, the merging, in the code block data merging subunit, the fourth code block data to obtain merged fifth code block data includes:

if the number of the fourth code block data is one, the fourth code block data is used as the fifth code block data;

and if the number of the fourth code block data is at least two, accumulating the fourth code block data according to the numerical value of the corresponding position to obtain one accumulated fifth code block data.

Optionally, the inserting, in the code block data padding subunit, a saturation value and zero into the fifth code block data to obtain the padded third code block data includes:

acquiring a first start position k0 and an interpolation position kd of the fifth code block data, wherein k0 is a start position at which the fifth code block data is read, and kd is a position at which a saturation value is inserted in the fifth code block data;

reading from the first start position k0 to the end of the fifth code block data, and then reading from the head of the fifth code block data to the first start position k0, to obtain a sixth code block data after reading, wherein the sixth code block data has a length Ncb';

and writing a first preset number of the saturation values in the interpolation position kd of the sixth code block data, and writing a second preset number of zeros in front of a second initial position of the sixth code block data to obtain the third code block data.

Optionally, the sending the first code block data to a deinterleaving unit to obtain deinterleaved second code block data output by the deinterleaving unit includes:

storing the first code block data into a buffer of the de-interleaving unit in columns, wherein the number of rows of the buffer is n times of a modulation coefficient, and n is an integer greater than 1;

and reading the first code block data from the buffer according to a preset rule and lines to obtain the second code block data after de-interleaving.

Optionally, the reading the first code block data from the buffer according to a preset rule by rows to obtain the second code block data after deinterleaving includes:

reading data in each column from the buffer according to lines, and when the data in any column is read from the buffer at the jth time, sequentially reading data on the jth, 1 × q + j, … …, (N/q-1) × q + j bits in the column to obtain the second code block data after de-interleaving; wherein q is the modulation coefficient, j is an integer [1, q ], and N is the number of rows of the buffer.

Optionally, identification bits are set between the subunits at each clock cycle of transmitting code block data, where the identification bits are used to mark the number of valid data in the code block data transmitted at the clock cycle, and the code block data includes at least one of the second code block data, the fourth code block data, the fifth code block data, and the third code block data.

In a second aspect, an embodiment of the present disclosure provides a de-rate matching apparatus, including:

an obtaining module, configured to obtain first code block data;

the first processing module is used for sending the first code block data to a de-interleaving unit and acquiring the de-interleaved second code block data output by the de-interleaving unit;

a sending module, configured to send the second code block data to a bit decoding selection unit, where the bit decoding selection unit includes a code block data segmentation subunit, a code block data merging subunit, and a code block data padding subunit;

a second processing module, configured to perform parallel pipeline processing on the second code block data in the code block data segmentation subunit, the code block data merging subunit, and the code block data padding subunit to obtain third code block data after bit decoding selection;

and the storage module is used for storing the third code block data into a ring buffer.

In a third aspect, an embodiment of the present disclosure provides a chip, including: a memory and a processor; the memory is used for storing a computer program; the processor is configured to implement the method of de-rate matching according to the first aspect when the computer program is executed.

In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including: the system comprises a processor, a memory and a communication bus, wherein the processor and the memory are communicated with each other through the communication bus;

the memory for storing a computer program;

the processor is configured to execute the program stored in the memory to implement the method for rate de-matching according to the first aspect.

In a fifth aspect, the present disclosure provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the method for rate de-matching according to the first aspect.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages: the embodiment of the disclosure provides a method, a device, a chip, a device and a storage medium for de-rate matching, wherein the method comprises the following steps: the method comprises the steps of obtaining first code block data, sending the first code block data to a de-interleaving unit, obtaining second code block data output by the de-interleaving unit after de-interleaving, and sending the second code block data to a de-bit selection unit, wherein the de-bit selection unit comprises a code block data segmentation subunit, a code block data merging subunit and a code block data filling subunit, and in the code block data segmentation subunit, the code block data merging subunit and the code block data filling subunit, the second code block data are subjected to parallel pipeline processing, third code block data after bit de-selection are obtained, and the third code block data are stored in an annular buffer.

The method comprises the steps that a decoding bit selection unit is divided into three subunits, namely a code block data segmentation subunit, a code block data merging subunit and a code block data filling subunit, parallel pipeline type data processing is achieved among the three subunits, when decoding bit selection is conducted, because the three subunits in the decoding bit selection unit process data in parallel, the second code block data after de-interleaving does not need to wait for the execution of the previous code block data to complete the whole decoding bit selection process, the decoding bit selection process can be executed, the steps in the code block data segmentation subunit can be executed only by waiting for the execution of the previous code block data in the code block data segmentation subunit, the processing efficiency of the decoding bit selection process is improved, the processing time delay is reduced, the processing duration of decoding rate matching is further reduced, and the processing efficiency of decoding rate matching is improved. For example, the existing bit decoding selection is implemented in one module, and it is required to wait for the code block data a to be processed after the bit decoding selection is completed before processing the next code block data b, and the pipelining degree is low, whereas in the present disclosure, after the code block data a is executed in the code block data segmentation subunit, when the code block data a is executed in the code block data merging subunit, the code block data b may be executed in the code block data segmentation subunit, and it is not required to wait for the code block data a to be executed in the whole bit decoding selection unit.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.

Fig. 1 is a schematic flowchart of a method for processing uplink data according to an embodiment of the present disclosure;

FIG. 2 is a flow chart illustrating a method for de-rate matching according to an embodiment of the present disclosure;

FIG. 3 is a schematic flow chart illustrating the method of step 204 of FIG. 2 according to one embodiment of the present disclosure;

FIG. 4 is a schematic flowchart of the method of step 301 of FIG. 3 in one embodiment of the present disclosure;

FIG. 5 is a schematic flow chart illustrating the method of step 302 of FIG. 3 according to an embodiment of the present disclosure;

FIG. 6 is a schematic flow chart illustrating the method of step 303 of FIG. 3 in an exemplary embodiment of the present disclosure;

FIG. 7 is a flowchart illustrating the method of step 202 of FIG. 2 according to one embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a de-rate matching apparatus according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of an electronic device in an embodiment of the disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

In the embodiments of the present disclosure, a de-rate matching method is provided, which may be applied to a Field-Programmable Gate Array (FPGA), and certainly, may also be applied to other hardware devices, for example, an Application Specific Integrated Circuit (ASIC). In the embodiment of the present disclosure, the method is applied to an FPGA as an example.

The embodiment of the present disclosure can be applied to uplink or downlink data processing, please refer to fig. 1, which is a schematic flow chart of a method for processing uplink data. In step 101, MIMO (multiple input multiple output) is solved. And step 102, demodulating. And step 103, descrambling. And step 104, performing de-cascading. And step 105, rate matching is solved. Step 106, HARQ (Hybrid Automatic Repeat Request). And step 107, decoding.

The specific steps of the de-rate matching method proposed by the present disclosure will be described in detail below. Please refer to fig. 2, which is a schematic flow chart of the method for rate de-matching in the embodiment of the present disclosure, wherein the flow chart of the method for rate de-matching provided in the present disclosure mainly includes:

step 201, first code block data is acquired.

Wherein the acquiring of the first code block data is acquiring of the first code block data transmitted by the deserializing unit.

After demodulation, each bit corresponds to a log-likelihood ratio (LLR), which is called soft information. In addition, soft information is typically quantized using 6 bits.

The processing unit of the data before the de-concatenation is a symbol, and the processing unit of the data after the de-concatenation is a code block. And the de-concatenation unit sends the de-concatenated first code block data to the de-interleaving unit.

Step 202, sending the first code block data to a de-interleaving unit, and acquiring the de-interleaved second code block data output by the de-interleaving unit.

And step 203, sending the second code block data to a decoding bit selection unit, wherein the decoding bit selection unit comprises a code block data segmentation subunit, a code block data merging subunit and a code block data filling subunit.

And 204, performing parallel pipeline processing on the second code block data in the code block data segmentation subunit, the code block data merging subunit and the code block data filling subunit to obtain third code block data after bit decoding selection.

Step 205, store the third chunk data into the circular buffer.

The embodiment of the disclosure divides the decoding bit selection unit into three subunits of a code block data segmentation subunit, a code block data merging subunit and a code block data filling subunit, each beat of processing amount in each subunit is a plurality of subunits, namely parallel processing, parallel stream type data processing is realized among the three subunits, when decoding bit selection is performed, because the three subunits in the decoding bit selection unit are used for processing data in parallel stream type, the second code block data after de-interleaving can perform the decoding bit selection process without waiting for the previous code block data to complete the whole decoding bit selection process, only the previous code block data is required to complete the code block data in the code block data segmentation subunit, the steps in the code block data segmentation subunit can be performed, the processing efficiency of the decoding bit selection process is improved, the processing time delay is reduced, and the processing duration of decoding rate matching is further reduced, and the processing efficiency of rate de-matching is improved. For example, the existing bit decoding selection is implemented in one module, and it is required to wait for the code block data a to be processed after the bit decoding selection is completed before processing the next code block data b, and the pipelining degree is low, whereas in the present disclosure, after the code block data a is executed in the code block data segmentation subunit, when the code block data a is executed in the code block data merging subunit, the code block data b may be executed in the code block data segmentation subunit, and it is not required to wait for the code block data a to be executed in the whole bit decoding selection unit.

Please refer to fig. 3, which is a flowchart illustrating the method of step 204 in fig. 2. In one embodiment, step 204 comprises:

step 301, sending the second code block data to a code block data segmentation subunit, and in the code block data segmentation subunit, segmenting the second code block data according to the length Ncb 'to obtain segmented fourth code block data, where the length of the fourth code block data is Ncb'.

Wherein, the Ncb' length is calculated according to the base map mode and the circulation factor. When the base pattern BGN is 1, Ncb ═ 66 × zc; when the base pattern BGN is 2, Ncb' 50 × zc is a circulation factor.

Step 302, sending the fourth code block data to a code block data merging subunit, merging the fourth code block data in the code block data merging subunit to obtain merged fifth code block data, where the length of the fifth code block data is Ncb'.

Step 303, sending the fifth code block data to the code block data padding subunit, and inserting a saturation value and zero into the fifth code block data in the code block data padding subunit to obtain padded third code block data.

In this embodiment, the code block data dividing subunit divides the second code block data according to the Ncb' length, the code block data merging subunit merges the divided fourth code block data, and the code block data padding subunit interpolates and zero-fills the merged fifth code block data, thereby completing the step of bit-decoding selection of the second code block data.

Please refer to fig. 4, which is a flowchart illustrating the method of step 301 in fig. 3. In one embodiment, step 301 comprises:

step 401, obtaining the length of the second code block data.

Step 402, if the length of the second code block data is smaller than Ncb', performing zero padding at the tail of the second code block data to obtain a fourth code block data after zero padding.

In step 403, if the length of the second code block data is equal to Ncb', the second code block data is regarded as fourth code block data.

Step 404, if the length of the second code block data is greater than Ncb ', the second code block data is segmented according to Ncb ', and zero padding is performed on the portion of the second code block data at the tail part, which is less than Ncb ', to obtain at least two fourth code block data.

In the present embodiment, when the second block data is divided, it is necessary to determine the relationship between the length of the second block data and Ncb'. To clearly illustrate step 404, the following will be exemplified: assuming that the length of the second code block data is greater than Ncb ', when the second code block data is segmented according to Ncb ', Ncb1, Ncb2 and Ncb3 are obtained, wherein the lengths of Ncb1 and Ncb2 are equal to Ncb ', and the length of Ncb3 is smaller than Ncb ', the tail of Ncb3 is zero-padded until the length of Ncb3 after zero-padding is equal to Ncb ', and finally the second code block data is segmented and outputs 3 fourth code block data, namely Ncb1, Ncb2 and Ncb3 after zero-padding.

Please refer to fig. 5, which is a flowchart illustrating the method of step 302 in fig. 3. In one embodiment, step 302 includes:

in step 501, the number of fourth code block data is obtained.

Step 502, if the number of the fourth code block data is one, the fourth code block data is regarded as fifth code block data.

Step 503, if the number of the fourth code block data is at least two, accumulating the fourth code block data according to the numerical value of the corresponding position to obtain an accumulated fifth code block data.

For example, Ncb' has a length of 4 bits, the number of the fourth code block data is two, which are Ncb1 and Ncb2, Ncb1 is 1, 2, 3, and 4, Ncb2 is 5, 6, 7, and 0, and Ncb1 and Ncb2 are accumulated according to the values of the corresponding positions, so that the fifth code block data is 1+5, 2+6, 3+7, and 4+0, that is, the fifth code block data is 6, 8, 10, and 4, and the length of the fifth code block data is still 4 bits.

Please refer to fig. 6, which is a flowchart illustrating the method of step 303 in fig. 3. In one embodiment, step 303 comprises:

step 601, a first start position k0 and an interpolation position kd of the fifth code block data are obtained, where k0 is the start position of reading the fifth code block data, and kd is the position of inserting a saturation value in the fifth code block data.

k0 and kd may be any position in the fifth code block data.

Step 602, reads from the first start position k0 to the end of the fifth code block data, and reads from the head of the fifth code block data to the first start position k0 to obtain the sixth code block data after reading, wherein the length of the sixth code block data is Ncb'.

For example, the data order of the fifth code block data is head-k 0-end, and the data order of the sixth code block data is k 0-end-head-k 0.

Step 603, writing a first preset number of saturation values in the interpolation position kd of the sixth code block data, and writing a second preset number of zeros in front of a second start position of the sixth code block data to obtain third code block data.

The second start position of the sixth code block data is the header position of the sixth code block data. The saturation value is 1F (LLR value 6 bits). The second predetermined number is 2zc, where zc represents a circulation factor. The first preset number is f, which is calculated according to the length K 'of each first code block data after CRC is added and the cyclic factor zc, specifically, f is K-K'. When the base map pattern BGN is 1, K22 × zc; when the base pattern BGN is 2, K is 10 × zc. K 'is the length of each first code block data after CRC (Cyclic Redundancy Check) is added, i.e., the length of the ring buffer Ncb ═ Ncb' +2zc + f.

In a specific embodiment, identification bits are arranged between the subunits at each clock cycle of the transmission of the code block data, wherein the identification bits are used for marking the number of valid data in the transmission of the code block data at the clock cycle, and the code block data includes at least one of second code block data, fourth code block data, fifth code block data and third code block data.

In each process of rate de-matching, namely, in the process of transmitting data to a rear-stage unit by a front-stage unit, an identification bit is set to identify effective data, so that the subsequent processing process is facilitated, and accurate splicing of the data is not needed.

It should be noted that, in this embodiment, the deinterleaving unit may be a unit that implements the deinterleaving step through a software algorithm, or may also be a unit that implements the deinterleaving step through a hardware device such as an FPGA. When the software algorithm is adopted to realize the de-interleaving step, the line number of the buffer of the de-interleaving unit is set as a modulation coefficient, data is read out according to lines after being stored according to columns, but the data needs to be processed line by line, the data processing efficiency is low, and the processing time length is long. Referring to fig. 7, which is a schematic flowchart of the method in step 202 in fig. 2, a method for implementing a deinterleaving step by using a hardware device according to an embodiment of the present disclosure is provided. In one embodiment, step 202 comprises:

step 701, storing the first code block data into a buffer of a de-interleaving unit according to columns, wherein the number of rows of the buffer is n times of a modulation coefficient, and n is an integer greater than 1.

In the process of storing the first code block data into the buffer of the de-interleaving unit in columns, when the data is stored into the mth column of the buffer, the m-1 column of the buffer is ensured to store full data, and m is an integer greater than 1.

The number of lines of the buffer refers to the bit width of the buffer.

Currently, known modulation factors are 1, 2, 4, 6. For example, when the modulation factor is 4, the number of rows of the buffer may be set to 8.

In one embodiment, the number of rows of the buffer is set to a common multiple of the respective modulation coefficients. For example, if the modulation factors are 1, 2, 4, and 6, respectively, and the least common multiple of the modulation factors is 12, the number of rows of the buffer may be set to 12, or an integer multiple of 12. The number of rows of the buffer is set to be a common multiple of each modulation coefficient, and when the modulation coefficient is set to be any one of the modulation coefficients, the number of rows of the buffer does not need to be modified, and the number of rows of the buffer is inevitably an integral multiple of the modulation coefficient.

Storing the first code block data into a buffer of a de-interleaving unit according to columns, splicing the first code block data according to the line number of the buffer to form a plurality of data sequences with the length being the line number of the buffer, storing each data sequence into the buffer of the de-interleaving unit according to columns, or directly storing the first code block data into the buffer of the de-interleaving unit according to columns, and when the data is stored into the mth column of the buffer, ensuring that the m-1 column of the buffer stores full data.

Step 702, reading the first code block data from the buffer according to a preset rule by rows to obtain the second code block data after de-interleaving.

For example, the modulation factor is 4, the first code block data is a1b1c1d1a2b2c2d2a3b3c3d3a4b4c4d4, and in the conventional software deinterleaving, the number of rows in the buffer is set to be the modulation factor 4, and the rows are stored in the buffer of the deinterleaving unit in columns, and the storage method is as follows:

a1a2a3a4

b1b2b3b4

c1c2c2c4

d1d2d3d4

in the conventional software deinterleaving, reading is performed line by line, that is, reading a1a2a3a4b1b2b3b4c1c2c3c4d1d2d3d4 sequentially, and the obtained deinterleaved code block data is: a1a2a3a4b1b2b3b4c1c2c3c4d1d2d3d 4. Software de-interleaving requires processing data row by row, and only one data in one column can be read in the same clock cycle, for example, only a1 in the first column can be read in the first clock cycle, only a2 in the second column can be read in the second clock cycle, only a3 in the third column can be read in the third clock cycle, only a4 in the fourth column can be read in the fourth clock cycle, and 4 clock cycles are required for reading a1a2a3a 4.

In the present disclosure, the number of rows of the buffer is set to be n times of the modulation factor, and if the number of rows is set to be 12, the rows are stored in the buffer of the deinterleaving unit in the following manner:

a1a4

b1b4

c1c4

d1d4

a2

b2

c2

d2

a3

b3

c3

d3

in this disclosure, the data is read line by line according to a preset rule, and the obtained second deinterleaved code block data is a1a2a3a4b1b2b3b4c1c2c3c4d1d2d3d 4. With the method of the present disclosure, when reading, multiple data can be read in one column in the same clock cycle, for example, a first clock cycle can read a1, a2 and a3 in the first column at the same time, a second clock cycle reads a4 in the second column, and reads a1a2a3a4, which requires 2 clock cycles. The data processing capacity of the same clock cycle is improved, the number of log-likelihood ratios (LLRs) which can be read simultaneously is increased, the de-interleaving processing efficiency is improved, the de-interleaving processing time length is shortened, and the de-rate matching processing time length is further shortened.

In a specific embodiment, reading first code block data line by line from a buffer according to a preset rule to obtain second code block data after deinterleaving, includes: reading data in each column from the buffer according to rows, and when reading data in any column from the buffer for the jth time, sequentially reading data on the jth, 1 × q + j, … …, (N/q-1) × q + j bits in the column to obtain second code block data after de-interleaving; wherein q is the modulation coefficient, j is the [1, q ], and j is an integer, and N is the number of rows in the buffer.

For example, the modulation coefficient q is 4, the first code block data is a1b1c1d1a2b2c2d2a3b3c3d3a4b4c4d4, N is 3, the number of rows of the buffer is N ═ q ═ 3 ═ 4 ═ 12, and the first code block data is stored in the buffer in the following manner:

a1a4

b1b4

c1c4

d1d4

a2

b2

c2

d2

a3

b3

c3

d3

when j is 1, the data on the 1 st, 1 × 4+1 st, 2 × 4+1 st bits in each column are read from the buffer for the first time, that is, the data on the 1 st, 5 th, and 9 th bits in each column are read in sequence, that is, a1, a2, and a3 of the first column are read (a1, a2, and a3 are read at the same time), and a4 of the second column is read.

When j is 2, the data on the 2 nd, 1 × 4+2 nd, 2 × 4+2 nd bits in each column are read from the buffer for the second time, that is, the data on the 2 nd, 6 th, and 10 th bits in each column are read in sequence, that is, b1, b2, and b3 of the first column are read (b1, b2, and b3 are read at the same time), and b4 of the second column is read.

When j is 3, the data on the 3 rd, 1 × 4+3 th and 2 × 4+3 th bits in each column are sequentially read from the buffer for the third time, that is, the data on the 3 rd, 7 th and 11 th bits in each column are sequentially read, that is, c1, c2 and c3 of the first column are read (c1, c2 and c3 are read at the same time), and c4 of the second column is read.

When j is 4, the data on the 4 th, 1 × 4+4 th, 2 × 4+4 th bits in each column, that is, the data on the 4 th, 8 th, and 12 th bits in each column are sequentially read from the buffer for the fourth time, that is, the data on the d1, d2, and d3 in the first column are read (d1, d2, and d3 are read simultaneously), the data on d4 in the second column is read, and the second code block data after deinterleaving is read as a1a2a3a4b1b2b3b4c1c2c 4d1d2d3d4 by row.

The existing de-interleaving is realized by software, hardware is not used, when the software de-interleaving is realized, the line number of a buffer of a de-interleaving unit is set as a modulation coefficient, data is stored according to columns and then read out according to lines, the data needs to be processed line by line, the data processing efficiency is low, and the processing time is long. Compared with the de-interleaving in the prior art which is realized by software, the line number of the buffer of the de-interleaving unit is set as the modulation coefficient, the data is read out according to the row after being stored according to the column, the data needs to be processed line by line, only one data in one column can be read in the same clock period, the first code block data is stored into a buffer of a de-interleaving unit according to the column, after the previous column is ensured to be fully stored with the data, storing data in a subsequent column, the number of rows of the buffer being set to n times the modulation factor, n being an integer greater than 1, each column of the buffer being capable of storing more data, when the first code block data is read from the buffer according to the preset rule by lines, a plurality of data can be read in one column in the same clock cycle, the data processing amount in the same clock cycle is improved, the de-interleaving processing efficiency is improved, the de-interleaving processing time length is shortened, and the de-rate matching processing time length is further shortened.

It should be noted that the deinterleaving unit sets an identification bit at each clock cycle of transmitting the code block data to the bit decoding selecting unit.

Based on the same concept, the embodiment of the present disclosure provides a rate de-matching apparatus, and the specific implementation of the apparatus may refer to the description of the method embodiment, and the repeated parts are not repeated, as shown in fig. 8, the apparatus mainly includes:

an obtaining module 801, configured to obtain first code block data;

a first processing module 802, configured to send the first code block data to a deinterleaving unit, and obtain deinterleaved second code block data output by the deinterleaving unit;

a sending module 803, configured to send the second code block data to a solution bit selection unit, where the solution bit selection unit includes a code block data segmentation subunit, a code block data merging subunit, and a code block data padding subunit;

a second processing module 804, configured to perform parallel pipeline processing on the second code block data in the code block data segmentation subunit, the code block data merging subunit, and the code block data padding subunit to obtain third code block data after bit decoding selection;

a storage module 805, configured to store the third chunk data into a circular buffer.

Optionally, the second processing module includes:

a first processing unit, configured to send the second code block data to the code block data segmentation subunit, where the second code block data is segmented according to a length Ncb 'in the code block data segmentation subunit, and fourth segmented code block data is obtained, where the length of the fourth code block data is Ncb'; wherein, the Ncb' length is calculated according to the base map mode and the cyclic factor;

a second processing unit, configured to send the fourth code block data to the code block data merging subunit, where the code block data merging subunit merges the fourth code block data to obtain merged fifth code block data, where the length of the fifth code block data is Ncb';

and a third processing unit, configured to send the fifth code block data to the code block data padding subunit, where in the code block data padding subunit, a saturation value and zero are inserted into the fifth code block data, and the padded third code block data is obtained.

Optionally, the first processing unit includes:

a first obtaining subunit, configured to obtain a length of the second codeword data;

a first processing subunit, configured to perform zero padding on a tail portion of the second codeblock data if the length of the second codeblock data is smaller than Ncb', to obtain one piece of zero-padded fourth codeblock data;

a second processing subunit, configured to, if the length of the second code block data is equal to Ncb', take the second code block data as the fourth code block data;

and a third processing subunit, configured to, if the length of the second code block data is greater than Ncb ', divide the second code block data according to Ncb', and perform zero padding on a portion of the second code block data at the tail portion where Ncb 'is less than Ncb', to obtain at least two pieces of fourth code block data.

Optionally, the second processing unit comprises:

a fourth processing subunit configured to, if the number of the fourth code block data is one, take the fourth code block data as the fifth code block data;

a fifth processing subunit, configured to, if the number of the fourth code block data is at least two, accumulate the fourth code block data according to a value at a corresponding position, and obtain one accumulated fifth code block data.

Optionally, the third processing unit includes:

a second acquisition subunit configured to acquire a first start position k0 and an interpolation position kd of the fifth code block data, where k0 is a start position at which the fifth code block data is read, and kd is a position at which a saturation value is inserted in the fifth code block data;

a sixth processing subunit, configured to read from the first start position k0 to the end of the fifth code block data, and then read from the head of the fifth code block data to the first start position k0, to obtain a sixth read code block data, where the sixth code block data has a length Ncb';

a seventh processing subunit, configured to write a first preset number of the saturation values into the interpolation position kd of the sixth code block data, and write a second preset number of zeros into the interpolation position kd of the sixth code block data before a second start position of the sixth code block data, so as to obtain the third code block data.

Optionally, the first processing module includes:

the storage unit is used for storing the first code block data into a buffer of the de-interleaving unit in columns, wherein the number of rows of the buffer is n times of a modulation coefficient, and n is an integer greater than 1;

and the reading unit is used for reading the first code block data from the buffer according to a preset rule and lines to obtain the second code block data after de-interleaving.

Optionally, the reading unit is specifically configured to read data in each column from the buffer in rows, and when the data in any column is read from the buffer at the jth time, sequentially read data in the jth, 1 × q + j, … …, (N/q-1) × q + j bits in the column, and obtain the second code block data after deinterleaving; wherein q is the modulation coefficient, j is an integer [1, q ], and N is the number of rows of the buffer.

It should be noted that the specific implementation and technical effects of the embodiment of the present disclosure are consistent with the implementation and technical effects of the rate de-matching method described in the foregoing embodiment, and are not described herein again.

Based on the same concept, the embodiment of the present disclosure further provides a chip, including: a memory and a processor; the memory is used for storing a computer program; the processor is adapted to implement the de-rate matching method as described in the above embodiments when the computer program is executed.

Based on the same concept, an embodiment of the present disclosure further provides an electronic device, as shown in fig. 9, the electronic device mainly includes: a processor 901, a memory 902 and a communication bus 903, wherein the processor 901 and the memory 902 communicate with each other via the communication bus 903. The memory 902 stores a program executable by the processor 901, and the processor 901 executes the program stored in the memory 902 to implement the de-rate matching method as described in the above embodiments.

The communication bus 903 mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus 903 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 9, but that does not indicate only one bus or one type of bus.

The Memory 902 may include a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Alternatively, the memory may be at least one storage device located remotely from the processor 901.

The Processor 901 may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc., and may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

In a specific implementation manner, the electronic device in this embodiment may be an electronic device on a Base station side, such as a macro Base station, a small Base station, a BBU (Base band Unit), and the like, and may also be an electronic device on a terminal side, such as a mobile terminal, a tablet computer, and the like.

In yet another embodiment of the present disclosure, there is also provided a computer-readable storage medium having stored therein a computer program, which when run on a computer, causes the computer to execute the de-rate matching method described in the above embodiment.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the disclosure to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more of the available media. The available media may be magnetic media (e.g., floppy disks, hard disks, tapes, etc.), optical media (e.g., DVDs), or semiconductor media (e.g., solid state drives), among others.

It is noted that, in this document, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of de-rate matching, comprising:

acquiring first code block data;

performing parallel pipeline processing on the second code block data in the code block data segmentation subunit, the code block data merging subunit and the code block data padding subunit to obtain third code block data after bit decoding selection;

storing the third chunk data into a circular buffer.

2. The method of claim 1, wherein the performing parallel pipeline processing on the second block data in the code block data segmentation subunit, the code block data merging subunit, and the code block data stuffing subunit to obtain third block data after bit decoding selection comprises:

and sending the fifth code block data to the code block data padding subunit, and inserting a saturation value and zero into the fifth code block data in the code block data padding subunit to obtain the padded third code block data.

3. The method of claim 2, wherein the dividing the second code block data by Ncb' length in the code block data dividing subunit to obtain fourth divided code block data comprises:

acquiring the length of the second code block data;

4. The method of claim 2, wherein the merging the fourth code block data in the code block data merging subunit to obtain merged fifth code block data comprises:

if the number of the fourth code block data is one, taking the fourth code block data as the fifth code block data;

5. The method of claim 2, wherein the inserting saturation values and zeros in the code block data padding subunit into the fifth code block data to obtain the padded third code block data comprises:

acquiring a first start position k0 and an interpolation position kd of the fifth code block data, wherein k0 is a start position of reading the fifth code block data, and kd is a position of inserting a saturation value in the fifth code block data;

reading from the first start position k0 to the end of the fifth code block data, and then reading from the head of the fifth code block data to the first start position k0, to obtain a read sixth code block data, wherein the sixth code block data has a length Ncb';

writing a first preset number of the saturation values at the interpolation position kd of the sixth code block data, and writing a second preset number of zeros before a second start position of the sixth code block data, to obtain the third code block data.

6. The method of claim 1, wherein the sending the first code block data to a deinterleaving unit to obtain deinterleaved second code block data output by the deinterleaving unit comprises:

7. The method according to claim 6, wherein the reading the first code block data from the buffer by rows according to a preset rule to obtain the second code block data after de-interleaving comprises:

reading data in each column from the buffer according to rows, and when the data in any column is read from the buffer for the jth time, sequentially reading the data on the jth, 1 × q + j, … …, (N/q-1) × q + j bits in the column to obtain the second code block data after de-interleaving; wherein q is the modulation coefficient, j is an integer [1, q ], and N is the number of rows of the buffer.

8. The method of claim 2, wherein a flag is set between each subunit at each clock cycle of transmitting code block data, wherein the flag is used to mark the number of valid data in the code block data transmitted at the clock cycle, and the code block data includes at least one of the second code block data, the fourth code block data, the fifth code block data, and the third code block data.

9. A de-rate matching apparatus, comprising:

an obtaining module configured to obtain first code block data;

the first processing module is used for sending the first code block data to a de-interleaving unit and acquiring de-interleaved second code block data output by the de-interleaving unit;

10. A chip, comprising: a memory and a processor; the memory is used for storing a computer program; the processor is configured to implement the method of de-rate matching according to any one of claims 1 to 8 when the computer program is executed.

11. An electronic device, comprising: the system comprises a processor, a memory and a communication bus, wherein the processor and the memory are communicated with each other through the communication bus;

the memory for storing a computer program;

the processor, configured to execute the program stored in the memory, to implement the de-rate matching method of any one of claims 1 to 8.

12. A computer-readable storage medium storing a computer program, wherein the computer program is configured to implement the method for de-rate matching according to any one of claims 1 to 8 when executed by a processor.