CN114499548B - Decoding method, device and storage medium - Google Patents
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Abstract
The embodiment of the application discloses a decoding method, a decoding device and a storage medium, wherein the method comprises the following steps: carrying out soft demodulation on the received code word to obtain a soft bit sequence; iteratively decoding the soft bit sequence until the decoded code word generated by the decoding for the t time passes the check, and the correlation coefficient of the decoding for the t time is greater than the coefficient threshold value; t is a natural number not less than 1; and the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a decoding method, a decoding device, and a storage medium.
Background
False alarm refers to the situation where the decoded codeword generated by decoding is detected by cyclic redundancy check, but the codeword is not transmitted. The reason for the false alarm is that the code of any transmitted codeword is passed through the cyclic redundancy check, and due to the interference of noise, the decoded codeword may be other codewords than the transmitted codeword. False alarms can cause erroneous codewords to be received, which can have a serious impact on the communication system. Therefore, it is important to effectively reduce the false alarm rate by using a proper method to ensure the transmission quality of the communication system.
Currently, in the decoding process, the hard decision bit flipping number is usually used as a decision index to determine whether a false alarm occurs. If the number of hard decision bit flips is larger than a specific threshold, the decoded codeword is determined to be unreliable, a false alarm occurs, and then iterative decoding needs to be continued to obtain a correct decoded codeword.
However, the hard decision bit flipping number is adopted as a decision criterion, wherein only the sign information of the soft bit is used, it is difficult to accurately determine whether the decoded codeword is correct, which results in a high decoding false alarm rate, and the hard decision bit flipping number requires additional hardware overhead including an inverse encoder, a comparator and a counter, which consumes a long time and consumes a large amount of power.
Disclosure of Invention
The embodiment of the application provides a decoding method, a decoding device and a storage medium, which can not only reduce the decoding false alarm rate, but also reduce the power consumption and the time of false alarm detection.
The technical scheme of the embodiment of the application is realized as follows:
the embodiment of the application provides a decoding method, which comprises the following steps:
carrying out soft demodulation on the received code word to obtain a soft bit sequence;
iteratively decoding the soft bit sequence until a decoded code word generated by the decoding for the t time passes the check, wherein the correlation coefficient of the decoding for the t time is greater than a coefficient threshold value; t is a natural number not less than 1;
and the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding.
In the above method, the iteratively decoding the soft bit sequence until a decoded codeword generated by the tth decoding passes verification, and a correlation coefficient of the tth decoding is greater than a coefficient threshold includes:
during the iterative decoding of the soft bit sequence, checking the decoded code word generated by each decoding, and/or calculating the correlation coefficient of each decoding until the decoded code word generated by the tth decoding passes the check, wherein the correlation coefficient of the tth decoding is greater than the coefficient threshold.
In the above method, the calculating the correlation coefficient for each decoding includes:
and determining the correlation coefficient of each decoding by using the path metric generated by each decoding and the absolute value sum, wherein the absolute value sum is obtained by performing absolute value accumulation on the soft bits in the soft bit sequence.
In the above method, further comprising:
stopping the iterative decoding of the soft bit sequence in case a decoding termination condition is detected to be fulfilled during the iterative decoding of the soft bit sequence.
In the above method, the coding termination condition is: the number of times the soft bit sequence is decoded reaches a maximum number of times.
In the above method, the iteratively decoding the soft bit sequence includes:
when decoding for the r time is executed, forward tracking is carried out on the soft bit sequence based on a state transition rule, and path measurement of each state in state transition is determined; r is a natural number not less than 1 and not more than t;
determining the state with the maximum path metric in the state transition as the optimal state;
and performing state transition reverse tracking by taking the optimal state as a reference, reversely ordering the bits obtained by the reverse tracking, and determining the bits as the decoding code words generated by the r-th decoding.
In the above method, after determining the state with the largest path metric in the state transition as the optimal state, the method further includes:
determining a path metric for the best state as a path metric generated by the r-th coding.
An embodiment of the present application provides a decoding apparatus, including:
the demodulation module is used for carrying out soft demodulation on the received code words to obtain a soft bit sequence;
a decoding module to:
iteratively decoding the soft bit sequence until a decoded code word generated by the decoding for the t time passes the check, wherein the correlation coefficient of the decoding for the t time is greater than a coefficient threshold value; t is a natural number not less than 1;
and the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding.
In the above decoding device, the decoding module is specifically configured to check a decoded codeword generated by each decoding during iterative decoding of the soft bit sequence, and/or calculate a correlation coefficient of each decoding until the decoded codeword generated by the t-th decoding passes the check, and the correlation coefficient of the t-th decoding is greater than the coefficient threshold.
In the above decoding device, the decoding module is specifically configured to determine the correlation coefficient for each decoding by using a path metric and an absolute sum generated by each decoding, where the absolute sum is obtained by performing absolute value accumulation on the soft bits in the soft bit sequence.
In the decoding device, the decoding module is further configured to:
stopping the iterative decoding of the soft bit sequence in case a decoding termination condition is detected to be fulfilled during the iterative decoding of the soft bit sequence.
In the above decoding device, the decoding termination condition is: the number of times the soft bit sequence is decoded reaches a maximum number of times.
In an embodiment of the present application, the decoding module is specifically configured to:
when decoding for the r time is executed, forward tracking is carried out on the soft bit sequence based on a state transition rule, and path measurement of each state in state transition is determined; r is a natural number not less than 1 and not more than t;
determining the state with the maximum path metric in the transfer as the optimal state;
and performing state transition reverse tracking by taking the optimal state as a reference, reversely ordering the bits obtained by the reverse tracking, and determining the bits as the decoding code words generated by the r-th decoding.
In an embodiment of the present application, the decoding module is further configured to determine the path metric of the best state as the path metric generated by the r-th decoding.
An embodiment of the present application provides a decoding apparatus, including: a processor, a memory, and a communication bus;
the communication bus is used for realizing communication connection between the processor and the memory;
the processor is configured to execute one or more programs stored in the memory to implement the decoding method.
An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the decoding method.
The embodiment of the application provides a decoding method, a decoding device and a storage medium, which are used for carrying out soft demodulation on received coded code words to obtain soft bit sequences; iteratively decoding the soft bit sequence until the decoded code word generated by the decoding for the t time passes the check, and the correlation coefficient of the decoding for the t time is greater than the coefficient threshold value; t is a natural number not less than 1; and the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding. The technical scheme provided by the embodiment of the application not only can reduce the decoding false alarm rate, but also can reduce the power consumption and the time length of false alarm detection.
Drawings
FIG. 1 is a schematic diagram of a modern digital communication system in the prior art;
FIG. 2 is a diagram illustrating tail-biting convolutional code encoding in the prior art;
FIG. 3 is a diagram illustrating tail-biting convolutional code state transition in the prior art;
fig. 4 is a first flowchart illustrating a decoding method according to an embodiment of the present application;
fig. 5 is a flowchart illustrating a decoding method according to an embodiment of the present application;
fig. 6 is a flowchart illustrating an exemplary decoding process provided in an embodiment of the present application;
fig. 7 is a first schematic structural diagram of a decoding apparatus according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The following describes in detail the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems by embodiments and with reference to the drawings. The following embodiments may be combined with each other and may not be described in detail in some embodiments for the same or similar concepts or processes.
The technical means described in the embodiments of the present application may be arbitrarily combined without conflict.
Fig. 1 is a schematic diagram of a modern digital communication system in the prior art. As shown in fig. 1, in a modern digital communication system, mainly includes: source, channel encoder, modulator, channel, demodulator, channel decoder, sink and noise sources, each of which is described in detail below.
Information source: for generating a binary bit sequence of the information to be transmitted, i.e. a transmission codeword.
A channel encoder: the method is used for coding the binary bit stream and improving the reliability of information transmission, wherein the coded binary bit sequence is a coded code word. Specifically, during the transmission of the digital signal in the channel, due to the non-ideal digital transmission characteristics of the actual channel and the presence of additive noise, bit errors may occur at the receiving end. To control errors, channel encoders of modern digital communication systems typically combine Automatic repeat Request (ARQ) Error detection techniques with Forward Error Correction (FEC) coding techniques. Among them, the most commonly used FEC coding techniques for channel encoders include: convolutional codes, TURBO codes, Low Density Parity Check (LDPC) codes, polar codes, and the like. Channel coding tends to add redundant information such that the length of the encoded codeword is greater than the transmitted codeword. It should be noted that, the channel encoder may add Cyclic Redundancy Check (CRC) to the transmitted codeword according to a specific algebraic operation criterion, so that, after subsequent decoding, whether decoding is correct may be determined according to whether CRC is accurate.
The modulator: for mapping (carrying) the encoded codeword onto a carrier to improve spectral efficiency. Modulators of modern digital communication systems typically employ IQ modulation techniques, with common modulation orientations including: binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QMA), and the like.
Channel: a channel is an electromagnetic wave propagation medium. The channel of modern digital communication systems is free space.
Noise source: noise sources can be generally classified into external noise and internal noise according to their sources. The external noise includes various electromagnetic wave interferences existing in the nature, and the internal noise refers to various noises generated by the electronic device itself.
A demodulator: the method is used for detecting the code words by using a certain criterion according to the modulation mode of the modulator. Modern digital communication systems usually adopt soft demodulation to obtain a soft bit sequence corresponding to each codeword in a code word, that is, a Log Likelihood Ratio (LLR) of each bit in the code word, and output the soft bit sequence.
And (3) a channel decoder: and the decoding device is used for decoding by using the soft bit sequence obtained by demodulation according to a certain decoding rule and outputting a decoding code word.
The signal sink: i.e. the receiver of the information, for receiving the decoded codeword obtained by decoding.
It will be appreciated that if decoded correctly, the decoded codeword should be identical to the transmitted codeword.
The related encoding and decoding methods in the modern digital communication system of the embodiment of the present application will be described below.
Tail-biting Convolutional Code (TBCC) is a Channel coding scheme of a Long Term Evolution (LTE) scheme mobile communication Physical Downlink Control Channel (PDCCH) and a Physical Broadcast Channel (PBCH). Designing an efficient and accurate tail-biting convolutional code decoding algorithm is vital to ensuring the communication quality. Meanwhile, since the tail-biting convolutional code performs well for short packet transmission, it may also be applied to Machine-type Communication (MTC) in Fifth-Generation (5G) mobile Communication or future mobile Communication.
Tail-biting convolutional codes obtain the code sequence by xoring the current input bit with the previous bit stored in a register. Tail biting convolutional codes are commonly used
Is shown in which
Which indicates the length of the transmitted codeword,
which represents the length of the code word to be encoded,
to encode the degree of storage, the number of register storage bits is indicated. Tail-biting convolutional codes will send the last few bits of a codeword as the initial state stored in a register.
According to the LTE protocol TS 36.212, the code rate of tail-biting convolutional code encoding in 4G is 1/3. Fig. 2 is a diagram illustrating tail-biting convolutional code encoding in the prior art. As shown in fig. 2, when the input bit is
The register state is
Then, the 3 coded bits are:
,
，
wherein, in the step (A),
indicating an exclusive or operation.
It should be noted that the state transition of tail-biting convolutional codes can be represented by a grid diagram, and consider one
The state transition of the convolutional code of (2) is as shown in fig. 3. During state transition, the register is shifted to the right1 bit and fills the input bits into the leftmost bits of the register.
For the channel coding scheme of tail-biting convolutional code, the decoding method is mainly the viterbi method. The viterbi method is a maximum likelihood dynamic programming algorithm that selects the optimal path at each state node, reducing the complexity of the algorithm search by reducing the number of paths retained by the node. For tail-biting convolutional codes, the viterbi method referred to in the embodiments of the present application is different from the viterbi method in the conventional sense. The conventional viterbi method needs to start from a specific state, and the tail-biting convolutional code is unclear of the initial state, so the viterbi method mentioned in the embodiments of the present application starts from all states.
The embodiment of the application provides a decoding method, which is realized by a decoding device, wherein the decoding device can be a channel decoder. Fig. 4 is a first flowchart illustrating a decoding method according to an embodiment of the present application. As shown in fig. 4, in the embodiment of the present application, the decoding method mainly includes the following steps:
s101, carrying out soft demodulation on the received code words to obtain a soft bit sequence.
In the embodiment of the present application, the decoding apparatus may receive the encoded codeword, and thereby perform soft demodulation on the received encoded codeword to obtain a soft bit sequence.
It is understood that in the embodiment of the present application, the decoding apparatus may include the demodulator shown in fig. 1, and the demodulator may have a function of soft demodulation, so that the decoding apparatus can perform soft demodulation on the received encoded code word through the demodulator.
It should be noted that, in the embodiments of the present application,
and the soft bit corresponding to the ith soft bit in the soft bit sequence, namely the ith bit in the coded code word is represented.
S102, iteratively decoding the soft bit sequence until a decoded code word generated by the decoding for the t time passes the check, wherein the correlation coefficient of the decoding for the t time is greater than a coefficient threshold value; t is a natural number not less than 1; and the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding.
In the embodiment of the present application, the decoding apparatus may iteratively decode the soft bit sequence until a decoded codeword generated by the decoding for the t-th time passes verification, and a correlation coefficient of the decoding for the t-th time is greater than a coefficient threshold, where a specific decoding method is a viterbi decoding method.
Specifically, when the decoding device performs the decoding for the r time, the decoding device performs forward tracking processing on the soft bit sequence based on a state transition rule to determine a path metric of each state in the state transition; determining the state with the maximum path metric in the state transition as the optimal state; performing state transition reverse tracking by taking the optimal state as a reference, reversely ordering bits obtained by the reverse tracking, and determining the bits as decoding code words generated by the r-th decoding; r is a natural number not less than 1 and not more than t. In addition, the decoding apparatus determines the path metric of the best state as the path metric generated by the r-th decoding. The decoding process is described in detail below.
Fig. 5 is a flowchart illustrating a decoding method according to an embodiment of the present application. As shown in fig. 5, the following steps are mainly performed:
1) initializing path metrics
All 64 path metrics are initialized to 0, as shown in the following equation (1):
wherein the content of the first and second substances,
the path metric is initialized for path a.
2) Branch metric computation
The branch metric refers to the increment of soft bits that are transferred from the previous state to the next state, and the calculation formula of the branch metric is as follows:
wherein the content of the first and second substances,
denotes the first
State of step from
Transition to a State
In the first
The number of bits on each of the data streams,
is shown as
Step one
The symbols of the LLRs on each data stream,
the sign bit operation is carried out, and the operation rule is as follows:
，
，
，
is shown as
The absolute value of the LLRs on each data stream,
denotes the first
State of step from
Transition to a State
The branch metric of (a) is measured,
representing the xor sign. When the sign of the LLR is consistent with the sign modulated by the code sequence, the branch metric can increase the absolute value of the LLR, and when the sign of the LLR is inconsistent with the sign modulated by the code sequence, the branch metric can not increase.
The branch metric calculation process is further explained by table 1 below:
TABLE 1
Referring to table 1, in the code sequence, when a bit is 0 and LLR is a positive number, or when a bit is 1 and LLR is a negative number, the bit and LLR are considered to be identical in sign. In the formula (2)
In effect, the inverse mapping from symbol to bit.
3) Path metric computation
The path metric is an accumulated value of branch metrics on the path. There is one path metric value per state per step. For a particular state, there are two paths to reach the current state from two previous states. The path metrics of the two previous states are added to the branch metrics on the two paths, respectively, to obtain two candidate path metrics. The maximum path metric is selected from the two candidate path metrics as the path metric of the current state, and the calculation process is as follows:
wherein
Is shown as
State of step
Is measured.
During the path metric calculation, the updated path metrics are stored in the path metrics memory, while the last bit of the previous state of the selected path is stored in the traceback memory. The bits stored in the traceback memory are the path number.
4) Selecting the best state
The state with the largest path metric is selected as the best state from the 64 states.
5) Reverse tracking
Starting from the optimum state, tracing backwards and forwards
A bit. When tracing the first
When it is a bit, will be
The 1 st bit of each state is used as an output bit
The last 5 bits of the state are as
The first 5 bits of each state will back track the memory
One bit as the second bit
The last bit of the state.
6) Reverse sorting
And reversely ordering the bit sequence obtained by the reverse tracking to obtain a decoding code word.
Specifically, in the embodiment of the present application, the iterative decoding of the soft bit sequence by the decoding apparatus until the decoded codeword generated by the t-th decoding passes verification, and the correlation coefficient of the t-th decoding is greater than the coefficient threshold includes: during the iterative decoding of the soft bit sequence, the decoding code word generated by each decoding is checked, and/or the correlation coefficient of each decoding is calculated until the decoding code word generated by the decoding of the t time passes the check, and the correlation coefficient of the decoding of the t time is larger than the coefficient threshold value.
It should be noted that the definition of the correlation coefficient is shown in the following formula (4):
wherein the content of the first and second substances,
for the anti-coded bit corresponding to the ith bit in the coded codeword, N is the length of the coded codeword, which is actually the length of the soft bit sequence. The correlation coefficient is equal to the difference between the sum of the absolute values of the soft bits whose bits are not flipped and the sum of the absolute values of the soft bits whose bits are flipped in the encoded codeword. The correlation coefficient reflects the correlation between the anti-coded bits and the LLRIf the correlation coefficient is larger, the larger the correlation degree between the anti-coding bit and the LLR is, the more accurate the decoding is possible.
It is understood that, in the embodiment of the present application, if the correlation coefficient is directly calculated according to the above formula (4), it is necessary to calculate the correlation coefficient
The secondary accumulation calculation requires a large time delay and calculation overhead.
It should be noted that, in the embodiment of the present application, in the case of code sequence determination, the branch metric thereof can be expressed as a function of the code and the LLR value, and in the above equation (2),
is composed of
And
a function of
Defined as branch metric parameters.
TABLE 2
According to table 2, the logarithm and the exclusive or in equation (2) can be converted into a product and an addition, and the coded bits can be encoded
Replacement with anti-coded bits
The following formula can be obtained:
accordingly, the path metric is the sum of all branch metrics, which is expressed as:
thus, the correlation coefficient may be calculated by the path metric and the LLR value, expressed as:
the sum of the absolute values of the soft bit sequence can be calculated in parallel with decoding, and extra time delay is not occupied.
It is to be understood that, in the embodiment of the present application, as shown in equation (7), the calculation of the correlation coefficient for each decoding involves two parts, namely, the path metric generated by the decoding and the sum of the absolute values of the soft bit sequence, which is obtained by performing the absolute value accumulation on the soft bits in the soft bit sequence. The decoding means generates a decoded codeword and a path metric during iterative decoding of the soft bit sequence for each decoding, and thus the decoding means can determine the correlation coefficient using the generated path metric and the sum of absolute values for each decoding.
It should be noted that, in the embodiment of the present application, as shown in equation (7), the determining, by the decoding apparatus, the correlation coefficient for each decoding by using the sum of the path metric and the absolute value generated by each decoding includes: the difference between twice the path metric generated by each decoding and the sum of the absolute values is determined as the correlation coefficient for each decoding.
It should be noted that, in the embodiment of the present application, the decoding apparatus checks the decoded codeword generated by each decoding, and specifically, cyclic redundancy check may be performed on the decoded codeword generated by each decoding.
It should be noted that, in the embodiment of the present application, if a decoded codeword generated by a certain decoding passes verification, the decoding correctness may be characterized to a certain extent, but as described above, there may be a false alarm condition, and therefore, it is also necessary to determine a correlation coefficient of the decoding, where the greater the correlation coefficient is, the higher the accuracy of the characterization decoding is, and if the correlation coefficient of the decoding is greater than a coefficient threshold value, the higher the accuracy of the characterization decoding is, at this time, the decoding correctness may be determined, so as to stop iterative decoding.
It should be noted that, in the embodiment of the present application, the coefficient threshold may be set according to actual needs and application scenarios, and the embodiment of the present application is not limited.
It should be noted that, in the embodiment of the present application, after each decoding, the decoding device may check the decoded codeword generated by the decoding, and if the check fails, the decoding device may directly perform the next decoding without performing calculation and decision on the correlation coefficient.
It can be understood that, in the embodiment of the present application, a correlation coefficient is used as a decision indicator, and the correlation coefficient is determined by a sum of a path metric generated by decoding and an absolute value of a soft bit sequence, where the path metric relates to sign information of the soft bit sequence, and the sum of the absolute value of the soft bit sequence relates to amplitude information of the soft bit sequence, that is, the sign information and the amplitude information of the soft bit sequence are fully utilized, so that a false alarm decision can be accurately made. In addition, for the calculation of the correlation coefficient, the path metric does not need extra hardware overhead, and the calculation of the sum of the absolute values of the soft bit sequences can be realized in parallel with the decoding, so that the power consumption and the time delay of false alarm detection can be reduced, and the decoding efficiency is improved.
It can be understood that, in the embodiment of the present application, when the decoded codeword generated by the decoding for the t-th time passes verification and the correlation coefficient of the decoding for the t-th time is greater than the coefficient threshold, the decoding apparatus may determine the decoded codeword generated by the decoding for the t-th time as a correct decoding result, so that the decoded codeword generated by the decoding for the t-th time may be applied.
In an embodiment of the present application, the decoding apparatus checks that, during iterative decoding of the soft bit sequence, the iterative decoding of the soft bit sequence may also be stopped in a case where it is detected that a decoding termination condition is satisfied.
It should be noted that, in the embodiment of the present application, if a decoded codeword generated by a certain decoding fails to check, or a correlation coefficient corresponding to the decoding is not greater than a coefficient threshold, a decoding error is actually characterized, and in order to obtain a correct decoding result, it is actually necessary to maintain iterative decoding and continue the next decoding, but decoding termination detection may be performed in advance to determine whether triggering of the next decoding is supported.
It should be noted that, in the embodiment of the present application, the decoding termination condition is: the number of times the soft bit sequence is decoded reaches a maximum number of times. Of course, the decoding termination condition may also be other conditions for limiting the iterative decoding, which are set according to actual requirements or application scenarios, and the embodiments of the present application are not limited.
Fig. 6 is a flowchart illustrating an exemplary decoding process according to an embodiment of the present application. As shown in fig. 6, the decoding apparatus specifically performs the following steps: s201, receiving a soft bit sequence, wherein the soft bit sequence is obtained by soft demodulation of a coded code word; s202, calculating the sum of absolute values of the soft bits, namely performing absolute value accumulation on the soft bits in the soft bit sequence to obtain the sum of absolute values; s203, decoding, specifically, performing iterative decoding by using a soft bit sequence; s204, calculating a correlation coefficient, specifically, determining the correlation coefficient by using the sum of the path metric and the absolute value generated by decoding; s205, cyclic redundancy check, namely, cyclic redundancy check is carried out on the decoded code words generated by decoding; and S206, judging whether the check is passed and the correlation coefficient is greater than the coefficient threshold, wherein if the check is passed and the correlation coefficient is greater than the coefficient threshold, executing the step S207, and ending the whole process, and if the check is not passed or the correlation coefficient is greater than the coefficient threshold, executing the step S208, judging whether a decoding termination condition is met, so that under the condition that the decoding termination condition is not met, next decoding is triggered again, namely, the step S203 is executed again, and under the condition that the decoding termination condition is met, executing the step S207, and ending the whole process.
The embodiment of the application provides a decoding method, which comprises the following steps: performing soft joint on the received code word to obtain a soft bit sequence; iteratively decoding the soft bit sequence until the decoded code word generated by the decoding for the t time passes the check, and the correlation coefficient of the decoding for the t time is greater than the coefficient threshold value; t is a natural number not less than 1; and the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding. In the decoding method provided by the embodiment of the application, the correlation coefficient is used as a decision index, and is determined by the path metric generated by decoding and the sum of the absolute values of the soft bit sequence, wherein the path metric relates to the symbol information of the soft bit sequence, and the sum of the absolute values of the soft bit sequence relates to the amplitude information of the soft bit sequence, that is, the symbol information and the amplitude information of the soft bit sequence are fully utilized, so that the false alarm decision can be accurately performed. In addition, for the calculation of the correlation coefficient, the path metric does not need extra hardware overhead, and the calculation of the sum of the absolute values of the soft bit sequences can be realized in parallel with the decoding, so that the power consumption and the time delay of false alarm detection can be reduced, and the decoding efficiency is improved.
The embodiment of the application provides a decoding device. Fig. 7 is a first schematic structural diagram of a decoding apparatus according to an embodiment of the present application. As shown in fig. 7, in an embodiment of the present application, a decoding apparatus includes:
a demodulation module 301, configured to perform soft demodulation on the received encoded codeword to obtain a soft bit sequence;
a decoding module 302 for:
iteratively decoding the soft bit sequence until the decoded code word generated by the decoding for the t time passes the check, and the correlation coefficient of the decoding for the t time is greater than the coefficient threshold value; t is a natural number not less than 1;
and the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding.
In an embodiment of the present application, the decoding module 302 is specifically configured to check a decoded codeword generated by each decoding during iterative decoding of the soft bit sequence, and/or calculate a correlation coefficient of each decoding until the decoded codeword generated by the tth decoding passes the check, and the correlation coefficient of the tth decoding is greater than the coefficient threshold.
In an embodiment of the present application, the decoding module 302 is specifically configured to determine a correlation coefficient for each decoding by using a path metric generated in each decoding and the sum of absolute values, where the sum of absolute values is obtained by performing absolute value accumulation on soft bits in the soft bit sequence.
In an embodiment of the present application, the decoding module 302 is further configured to:
stopping iterative decoding of the soft bit sequence in case it is detected that a decoding termination condition is fulfilled during iterative decoding of the soft bit sequence.
In an embodiment of the present application, the coding termination condition is: the number of times the soft bit sequence is decoded reaches a maximum number of times.
In an embodiment of the present application, the decoding module 302 is specifically configured to:
when decoding for the r time is executed, forward tracking is carried out on the soft bit sequence based on a state transition rule, and path measurement of each state in state transition is determined;
determining the state with the maximum path metric in the state transition as the optimal state;
and performing state transition reverse tracking by taking the optimal state as a reference, reversely ordering the bits obtained by the reverse tracking, and determining the bits as the decoding code words generated by the r-th decoding.
In an embodiment of the present application, the decoding module 302 is further configured to determine the path metric of the best state as the path metric generated by the r-th decoding.
Fig. 8 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present application. As shown in fig. 8, in an embodiment of the present application, a decoding apparatus includes: a processor 401, a memory 402, and a communication bus 403;
the communication bus 403 is used for implementing communication connection between the processor 401 and the memory 402;
the processor 401 is configured to execute one or more programs stored in the memory 402 to implement the decoding method.
An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the decoding method. The computer-readable storage medium may be a volatile Memory (volatile Memory), such as a Random-Access Memory (RAM); or a non-volatile Memory (non-volatile Memory), such as a Read-Only Memory (ROM), a flash Memory (flash Memory), a Hard Disk (Hard Disk Drive, HDD) or a Solid-State Drive (SSD); or a respective device, such as a mobile phone, a computer, a tablet device, a personal digital assistant, comprising one or any combination of the above memories.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of implementations of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks in the flowchart and/or block diagram block or blocks.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application are included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. A decoding method, comprising:
carrying out soft demodulation on the received code word to obtain a soft bit sequence;
performing Viterbi iterative decoding on the soft bit sequence until a decoded code word generated by the decoding for the t time passes the check, wherein the correlation coefficient of the decoding for the t time is greater than a coefficient threshold value; t is a natural number not less than 1;
wherein, the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding;
the performing viterbi iterative decoding on the soft bit sequence includes:
when decoding for the r time is executed, forward tracking is carried out on the soft bit sequence based on a state transition rule, and path measurement of each state in state transition is determined; r is a natural number not less than 1 and not more than t;
determining the state with the maximum path metric in the state transition as the optimal state;
and performing state transition reverse tracking by taking the optimal state as a reference, reversely ordering the bits obtained by the reverse tracking, and determining the bits as the decoding code words generated by the r-th decoding.
2. The method of claim 1, wherein the performing viterbi iterative decoding on the soft bit sequence until a decoded codeword generated by the t-th decoding passes verification, and a correlation coefficient of the t-th decoding is greater than a coefficient threshold value, comprises:
during the Viterbi iterative decoding of the soft bit sequence, the decoding code word generated by each decoding is checked, and/or the correlation coefficient of each decoding is calculated until the decoding code word generated by the t-th decoding passes the check, and the correlation coefficient of the t-th decoding is larger than the coefficient threshold value.
3. The method of claim 2, wherein the calculating the correlation coefficient for each decoding comprises:
determining a correlation coefficient of each decoding by using a path metric and an absolute value sum generated by each decoding, wherein the absolute value sum is obtained by performing absolute value accumulation on soft bits in the soft bit sequence;
the determining the correlation coefficient of each decoding by using the path metric and the absolute value sum generated by each decoding comprises: and determining the difference between twice of the path metric generated by each decoding and the sum of the absolute values as the correlation coefficient of each decoding.
4. The method of claim 1, further comprising:
and stopping the iterative decoding of the soft bit sequence under the condition that a decoding termination condition is detected to be met during the Viterbi iterative decoding of the soft bit sequence.
5. The method of claim 4, wherein the coding termination condition is: the number of times the soft bit sequence is decoded reaches a maximum number of times.
6. The method according to claim 1, wherein after determining the state with the largest path metric in the state transition as the optimal state, the method further comprises:
determining a path metric for the best state as a path metric generated by the r-th coding.
7. A decoding apparatus, comprising:
the demodulation module is used for carrying out soft demodulation on the received code words to obtain a soft bit sequence;
a decoding module to:
performing Viterbi iterative decoding on the soft bit sequence until a decoded code word generated by the decoding for the t time passes the check, wherein the correlation coefficient of the decoding for the t time is greater than a coefficient threshold value; t is a natural number not less than 1;
wherein, the correlation coefficient of the t-th decoding is used for indicating the degree of correlation between the soft bit sequence and the anti-coding bit of the decoded code word generated by the t-th decoding;
the decoding module is specifically configured to:
when decoding for the r time is executed, forward tracking is carried out on the soft bit sequence based on a state transition rule, and path measurement of each state in state transition is determined; r is a natural number not less than 1 and not more than t;
determining the state with the maximum path metric in the state transition as the optimal state;
and performing state transition reverse tracking by taking the optimal state as a reference, reversely ordering the bits obtained by the reverse tracking, and determining the bits as the decoding code words generated by the r-th decoding.
8. A decoding apparatus, comprising: a processor, a memory, and a communication bus;
the communication bus is used for realizing communication connection between the processor and the memory;
the processor is configured to execute one or more programs stored in the memory to implement the decoding method of any one of claims 1-6.
9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the decoding method according to any one of claims 1 to 6.
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| CN112953569B (en) * | 2021-02-03 | 2023-06-30 | Oppo广东移动通信有限公司 | Decoding method and device, storage medium, electronic equipment and decoder |
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