CN112953569B - Decoding method and device, storage medium, electronic equipment and decoder - Google Patents

Decoding method and device, storage medium, electronic equipment and decoder Download PDF

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CN112953569B
CN112953569B CN202110152508.3A CN202110152508A CN112953569B CN 112953569 B CN112953569 B CN 112953569B CN 202110152508 A CN202110152508 A CN 202110152508A CN 112953569 B CN112953569 B CN 112953569B
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decoding
bit sequence
iteration
turnover
proportion
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CN112953569A (en
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匡肃奉
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The application relates to a decoding method and device, a storage medium, electronic equipment and a decoder, wherein the method comprises the following steps: in the iterative decoding process, verifying the decoding bit sequence of each iteration, and calculating the turnover proportion of the decoding bit sequence in the previous and subsequent iterations; and stopping iteration when the current decoding bit sequence is successfully checked and the turnover proportion is smaller than a preset threshold value. Thus, the false detection probability can be effectively reduced.

Description

Decoding method and device, storage medium, electronic equipment and decoder
Technical Field
The present invention relates to the field of decoding technologies, and in particular, to a decoding method and apparatus, a storage medium, an electronic device, and a decoder.
Background
Low density parity check (Low Density Parity Check, LDPC) codes are widely used in modern digital communication systems as a linear block code whose performance approaches shannon's limit. Belief propagation (Belief Propagation, BP) decoding algorithms are widely used in the decoding of low density parity check codes due to their massively parallel processable nature. The basic idea of belief propagation decoding is that messages are exchanged between variable nodes and check nodes, and specifically, after the variable nodes (check nodes) receive messages of all check nodes (variable nodes) connected with the variable nodes, the messages transmitted to the check nodes (variable nodes) are updated, and the updated messages are transmitted to the check nodes (variable nodes) connected with the variable nodes, so that message transmission is performed iteratively.
In the related art, the iteration termination judgment is performed by combining the low-density parity check code and the cyclic redundancy check code, wherein if the cyclic redundancy check code is correct in verification, the decoding is terminated, and the decoding is considered to be correct, but the decoding can lead to non-negligible false detection probability.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a decoding method and apparatus, a storage medium, an electronic device, and a decoder that can effectively reduce the false detection probability.
A method of decoding, comprising:
in the iterative decoding process, verifying the decoding bit sequence of each iteration, and calculating the turnover proportion of the decoding bit sequence in the previous and subsequent iterations;
and stopping iteration when the current decoding bit sequence is successfully checked and the turnover proportion is smaller than a preset threshold value.
A computer readable storage medium having stored thereon a decoding program which, when executed by a processor, implements a decoding method as described above.
An electronic device comprises a memory, a processor and a decoding program stored in the memory and capable of running on the processor, wherein the decoding method is realized when the processor executes the decoding program.
A decoder comprises a memory, a processor and a decoding program stored in the memory and capable of running on the processor, wherein the processor realizes the decoding method when executing the decoding program.
A decoding device, comprising:
the verification module is used for verifying the decoding bit sequence of each iteration in the iterative decoding process;
the calculation module is used for calculating the turnover proportion of the decoding bit sequence in the iterative decoding process in the two times of iteration;
and the termination module is used for terminating iteration when the current decoding bit sequence is successfully checked and the turnover proportion is smaller than a preset threshold value.
A decoder comprises the decoding device.
According to the decoding method and device, the storage medium, the electronic equipment and the decoder, the decoding bit sequence of each iteration is checked in the iterative decoding process, the turnover proportion of the decoding bit sequence in the previous and subsequent iterations is calculated, and the iteration is terminated when the current decoding bit sequence is successfully checked and the turnover proportion is smaller than the preset threshold value. Thus, the false detection probability can be effectively reduced.
Drawings
FIG. 1 is a schematic diagram of the basic structure of a modern digital communication system;
FIG. 2 is a schematic diagram of a Tanner of a low density parity check code in the related art;
FIG. 3 is a flow chart of a decoding iteration in the related art;
FIG. 4 is a flow chart of a decoding method according to an embodiment of the present invention;
FIG. 5 is a block diagram of an electronic device according to one embodiment of the invention;
FIG. 6 is a block diagram of a decoder according to one embodiment of the present invention;
fig. 7 is a block diagram of a decoding apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It should be noted that, referring to fig. 1, a modern digital communication system may include a source, a channel encoder, a modulator, a channel, a demodulator, a channel decoder, and a sink.
The source is the publisher of the information for generating a binary bit stream of information to be transmitted.
The channel encoder is used for encoding the binary bit stream to improve the ability of the receiving end to identify errors, thereby reducing the error rate to improve the quality of the recovered information. In particular, during transmission of a digital signal on a channel, due to non-ideal digital transmission characteristics of an actual channel and the presence of additive noise, errors may occur at a receiving end, and in order to control errors, an automatic repeat request (Automatic Request, ARQ) error detection technique and a forward error correction (Forward Error Correction, FEC) encoding technique are generally applied to a channel encoder, so as to improve reliability of information transmission, and further reduce an error rate to improve quality of recovered information. The most commonly used forward error correction coding techniques at present are: convolutional codes, TURBO codes, low density parity check codes, polarization codes, and the like.
The modulator is used to map (carry) the encoded binary bit stream onto a carrier to improve spectral efficiency. The modulator generally adopts IQ modulation (specifically, dividing data into two paths, respectively performing carrier modulation, and mutually quadrature two paths of carriers), and corresponding common modulation modes include binary phase shift keying (Binary Phase Shift Keying, BPSK), quadrature phase shift keying (Quadrature Phase Shift Keying, QPSK), quadrature amplitude modulation (Quadrature Amplitude Modulation, QAM), and the like.
A channel is a channel for information transfer, i.e., a medium on which electromagnetic waves propagate, and in a wireless communication system, the channel is free space. When information is transmitted through a channel, noise sources can damage transmitted information, the noise sources can be generally divided into external noise and internal noise according to the sources, wherein the external noise comprises various electromagnetic wave interferences existing in nature, and the internal noise refers to various noises generated by an electronic device.
The demodulator is used for detecting the binary bit sent by the sending end by utilizing a certain criterion according to the modulation mode of the modulator of the sending end. At present, soft demodulation is mainly adopted, so as to obtain soft bits corresponding to the transmission bits, namely log likelihood ratios (Log Likelihood Ratio, LLR) of the transmission bits, which are defined as follows:
Figure BDA0002932480080000041
wherein LLR (v n ) Representing the transmitted bit v n Corresponding soft bits, p r (y n |v n =a) represents the transmission bit v n Receiving symbol y when =a n A e {0,1}; ln (·) represents a log-taking operation.
The channel decoder is used for decoding by using soft bit information obtained by demodulation according to a forward error correction coding technology adopted by the channel encoder of the transmitting end and adopting a certain decoding criterion to obtain binary bit information transmitted by the transmitting end. Common decoding algorithms include maximum likelihood (Maximum Likelihood, ML) decoding, maximum a posteriori probability (Maximum A Priori Probability, MAP) decoding, belief propagation (Belief Propagation, BP) decoding, and the like.
The information sink is a receiver of the information and is used for receiving the binary bit information obtained by decoding and converting the binary bit information to obtain a message sent by the information source.
The low density parity check code is widely used in modern digital communication systems as a linear block code whose performance approaches shannon's limit. The block code is to group the input information sequence with every k symbols, and the channel encoder generates r redundant symbols (called check elements) according to a certain rule for each information group, so as to form a codeword with length of n=k+r, and the block code is generally represented by (n, k). When block codeWhen the relation between the information symbols and the check elements is linear, the block code is called a linear block code. There are two important matrices for linear block codes: generating a matrix G and a check matrix H, for any one of the input information sequences u= (u) 0 ,u 1 ,...u k-1 ) The corresponding codeword of length N is v=u·g and h·v T =0, where v T The representation transposes the vector v.
The low density parity check code is defined as the null space of the check matrix H satisfying the following characteristics: 1) Each row has ρ non-0 elements; 2) Lambda non-0 elements in each column; 3) Compared with the code length N and the number of rows of the check matrix H, the number rho and the number lambda are much smaller, namely the check matrix H has sparse characteristics.
The low density parity check code may be represented by a Tanner graph, which is shown in fig. 2, taking the check matrix H described below as an example.
Figure BDA0002932480080000051
In FIG. 2, { x 0 ,x 1 ,...,x 7 And is a variable node, i.e., codeword v= (v) 0 ,v 1 ,...,v 7 ) Corresponding transmission symbols, according to the mapping rules x defined in the third generation partnership project (the 3rd Generation Partner Project,3GPP) standard n ＝1-2v n The method comprises the following steps: bit 0 maps to symbol 1; bit 1 maps to symbol-1; { s 0 ,s 1 ,s 2 ,s 3 And the check nodes respectively correspond to four check equations H.v T =0, i.e.:
Figure BDA0002932480080000052
wherein, the liquid crystal display device comprises a liquid crystal display device,
Figure BDA0002932480080000053
representing a modulo-2 addition operation. When H (m, n) =1, then the check node s is represented m And variable node x n Connected, i.e. s m Corresponding check equationWherein certain comprises x n Corresponding bit v n 。
Belief propagation decoding algorithms are widely used in decoding of low density parity check codes due to their massively parallel processing characteristics. The basic idea of belief propagation decoding is: soft information (or confidence) is exchanged between the variable nodes and the check nodes, and the exchanged soft information is called a message. The specific implementation is as follows: after receiving all the messages of the check nodes (variable nodes) connected with the variable nodes (check nodes), the variable nodes (check nodes) update the messages transmitted to the check nodes (variable nodes) and transmit the updated messages to the check nodes (variable nodes) connected with the variable nodes, so that the message transmission is performed iteratively, and the message transmission is specifically shown as 3.
The following describes in detail the specific calculation process of each flow in fig. 3:
step 1: initializing.
The input to belief propagation decoding is each transmitted bit v n Channel soft information of (i.e. transmit bit v) n Is denoted by L r (v n ) It is defined as follows:
Figure BDA0002932480080000061
wherein y is n Representing the transmitted symbol x n Corresponding received symbols, p r (. Cndot.) represents probability values and ln (. Cndot.) represents log-taking operations.
VN2CN-msg in FIG. 3 represents variable node x n Pass to check node s m Variable node x n Passed to the check node s connected thereto m Is recorded as a message of
Figure BDA0002932480080000062
The definition and calculation formula are as follows:
Figure BDA0002932480080000063
wherein, the liquid crystal display device comprises a liquid crystal display device,S n representation and variable node x n Connected check node set S n \s m Representation set S n Removing element s m The set of remaining elements that follow up,
Figure BDA0002932480080000064
representing a received symbol vector (y 0 ,y 1 ,...,y N-1 ) N represents the total number of variable nodes,
Figure BDA0002932480080000065
representing the ith iteration check node s m' Pass to variable node x n The definition and calculation formula of the message see check node update flow. During the initialization process, p->
Figure BDA0002932480080000066
Initializing:
Figure BDA0002932480080000067
step 2): and (5) checking node updating.
Check node s m Receiving variable node x connected with it n Update messages passed to each variable node to which it is connected according to the following:
Figure BDA0002932480080000071
wherein, the liquid crystal display device comprises a liquid crystal display device,
Figure BDA0002932480080000072
X m representation and verification node s m Connected variable node set X m \x n Representing a collection X m Removing element x n The remaining element sets after.
Step 3): and updating the variable nodes.
Variable node x n Receiving a signal from a connected deviceAfter checking the node's message, according to
Figure BDA0002932480080000073
Updating the formula updates the message passed to each check node connected thereto:
Figure BDA0002932480080000074
at the same time, the variable node calculates its transmission bit v n Posterior probability of (2)
Figure BDA0002932480080000075
The definition and calculation formula are as follows:
Figure BDA0002932480080000076
step 4): and judging the iteration termination condition.
In the related art, an iteration termination judgment is performed by combining a low-density parity check code with an error detection code, for example, a forward error correction channel coding technology of a low-density parity check code and a common error detection code technology of a cyclic redundancy check (Cyclic Redundancy Check, CRC) code are adopted by a physical downlink shared channel (Physical Downlink Shared Channel, PDSCH) of a New air interface (New Radio, NR) of a Fifth Generation (five G) mobile communication system, so as to perform an iteration termination judgment, which is specifically as follows:
using a posterior probability of each transmitted bit calculated during variable node update
Figure BDA0002932480080000077
Hard decision is carried out to obtain the decoding result of the sending bit sequence, namely the decoding bit sequence +.>
Figure BDA0002932480080000081
The hard decision is made as follows:
Figure BDA0002932480080000082
then, for decoding bit sequence
Figure BDA0002932480080000083
And (3) performing cyclic redundancy check, wherein the check process is as follows: decoding bit sequence +.>
Figure BDA0002932480080000084
As input, generating cyclic redundancy check codes according to the cyclic redundancy check code generating process in 3gpp Release 16, if the generated cyclic redundancy check codes are all zero (i.e. the remainder is zero), the cyclic redundancy check is successful, and then stopping decoding, and considering that the decoding is correct; otherwise, the cyclic redundancy check is considered to fail, and when the iteration number reaches the set maximum iteration number, the decoding is stopped, and the decoding is considered to fail, if the iteration number does not reach the maximum iteration number, the next iteration decoding is continued.
As known from 3gpp Release 16, the length of the cyclic redundancy check code includes two types, 16 bits and 24 bits, and the false detection probability of the cyclic redundancy check code of 16 bits is not negligible, especially for the Ultra-high reliability low latency communication (Ultra-Reliable and Low Latency Communications, URLLC) scenario of one of three major scenarios in 5G. However, in the above iterative process, the iteration is terminated as long as the crc check is successfully verified, and the decoding result is considered to be correct, thereby resulting in a non-negligible false detection probability.
In order to solve the technical problems, the invention concept of the application is as follows: and stopping iteration when the current decoding bit sequence is successfully checked and the turnover proportion of the decoding bit sequence is smaller than a preset threshold value when the current decoding bit sequence is iterated for two times.
In one embodiment, a decoding method is provided, which can be applied to the channel decoder shown in fig. 1, and referring to fig. 4, the decoding method includes the following steps:
step 402, in the iterative decoding process, the decoded bit sequence of each iteration is checked, and the flip ratio of the decoded bit sequence in the two previous and subsequent iterations is calculated.
For example, referring to fig. 3, in an iterative decoding process, one iteration refers to: the check node and the variable node complete one-time updating, specifically: after receiving the information from the variable nodes connected with the check nodes, the check nodes update the information transferred to each variable node connected with the check nodes according to the formula (7) and send the information to the variable nodes connected with the check nodes, and after receiving the information from the check nodes connected with the variable nodes, the variable nodes update the information transferred to each check node connected with the variable nodes according to the formula (8).
After each iteration is completed, checking the decoding bit sequence of each iteration, and calculating the turnover proportion of the decoding bit sequence in the previous and subsequent iterations.
The decoding bit sequence is the decoding result of the transmitting bit sequence. Optionally, the decoded bit sequence is obtained according to the following steps: and in the variable node updating process, calculating the posterior probability of each transmitted bit, and performing hard decision on the posterior probability to obtain a decoding bit sequence.
Specifically, after each iteration is completed, the posterior probability of each transmitted bit at the time of the iteration is obtained
Figure BDA0002932480080000091
And posterior probability per transmitted bit at previous iteration +.>
Figure BDA0002932480080000092
As shown in the above formula (9), and +.>
Figure BDA0002932480080000093
And->
Figure BDA0002932480080000094
Making hard decisions to obtain a decoded bit sequence, wherein the hard decisions are made according to the following formula:
Figure BDA0002932480080000095
decoding bit sequence when obtaining this iteration
Figure BDA0002932480080000096
And the decoded bit sequence at the previous iteration +.>
Figure BDA0002932480080000097
And then, calculating the turnover proportion of the decoding bit sequence in the two times of iteration. Optionally, calculating the flip ratio of the decoded bit sequence in the two previous and subsequent iterations includes: and performing modulo-2 addition operation on the decoded bit sequences iterated before and after, and calculating the turnover proportion according to the modulo-2 addition operation result. That is, the decoded bit sequence for the two previous and subsequent iterations +.>
Figure BDA0002932480080000098
And->
Figure BDA0002932480080000099
And performing modulo-2 addition operation, and calculating the turnover proportion according to the modulo-2 addition operation result, wherein the turnover proportion is specifically shown in the following formula:
Figure BDA00029324800800000910
at the same time, for the decoding bit sequence in the current iteration
Figure BDA00029324800800000911
And (5) checking. Optionally, verifying the decoded bit sequence of each iteration includes: and taking the decoded bit sequence as input, generating a cyclic redundancy detection (CRC) code, and determining that the decoded bit sequence is successfully checked when the CRC code is all 0.
That is, the decoded bit sequence at the time of this iteration is to be decoded
Figure BDA0002932480080000101
As input, generating according to a preset cyclic redundancy check codeThe algorithm generates a cyclic redundancy check, CRC, code (i.e., cyclic redundancy check code) and determines the CRC code. If the CRC code is all zero, the decoded bit sequence is determined +.>
Figure BDA0002932480080000102
And (5) checking success.
Step 404, terminating the iteration when the current decoded bit sequence is successfully verified and the flip ratio is less than a preset threshold value.
At each iteration, determining the decoding bit sequence at the time of the iteration in the way
Figure BDA0002932480080000104
The verification is successful, and the calculated inversion ratio eta of the decoded bit sequence is smaller than the preset threshold value alpha (which can be obtained through simulation) when the two iterations are performed before and after, namely, the decoded bit sequence +.>
Figure BDA0002932480080000103
If the verification is successful and eta is less than alpha, the decoding is determined to be correct, and the iteration is terminated; otherwise, the next iteration is continued. That is, when the decoding bit sequence in the current iteration is successfully checked and the turnover proportion is smaller than the preset threshold value, the decoding is considered to be correct, and the iteration is terminated, otherwise, the iteration is continued.
Therefore, compared with a mode of performing iteration termination judgment only through the cyclic redundancy check code, the method has the advantages that judgment on the inversion proportion, namely the number of times of bit inversion, is increased, and therefore the false detection probability can be effectively reduced. And when the iteration is terminated, comparing the turnover proportion with a preset threshold value, and considering that false detection occurs when the turnover proportion is larger than the preset threshold value, compared with a mode of recognizing that false detection occurs only by bit turnover, the method can effectively reduce the possibility that some bits with correct decoding are mistakenly considered to be false detection, and can improve the decoding performance by adjusting the preset threshold value, so that the false detection rate can be reduced. That is, compared with the mode of performing iteration termination judgment only through the cyclic redundancy check code and the mode of determining that false detection occurs as long as bit inversion exists, the method has lower false detection probability and greatly improves decoding performance. In addition, compared with a termination iteration judgment mode based on a syndrome (the syndrome refers to the product of a correction matrix and a decoding bit vector, and the syndrome is zero when decoding correctly), the method has the advantages of no need of matrix multiplication calculation, simplicity in calculation and low complexity.
Optionally, the decoding method further includes: acquiring iteration times; and when the verification of the current decoding bit sequence fails or the turnover proportion is larger than or equal to a preset threshold value, if the iteration number reaches a preset maximum iteration number, ending the iteration.
That is, when decoding a bit sequence
Figure BDA0002932480080000111
If the verification fails or eta is more than or equal to alpha, if the iteration number reaches the preset maximum iteration number I max The iteration is terminated to avoid that the iteration cannot be terminated.
The following describes the effects of the decoding method provided in the present application with reference to table 1.
Table 1 is a comparison table of decoding iteration termination method and false detection probability and average iteration number of the decoding method of the present application in the related art. Wherein, the simulation parameters are set as follows: the code block size k=8448, the code rate is 1/2, alpha=0.02, i max =16, the number of simulations was set to 20000.
TABLE 1
Figure BDA0002932480080000112
As can be seen from table 1, the decoding method of the present application has a reduced false detection rate by one order of magnitude, and the average iteration number is hardly increased, compared with the decoding iteration termination method of the related art, and the decoding method of the present application is simpler to calculate.
In summary, according to the decoding method of the embodiment of the present invention, in the iterative decoding process, the decoded bit sequence of each iteration is checked, the turnover proportion of the decoded bit sequence in two iterations is calculated, and when the current decoded bit sequence is checked successfully and the turnover proportion is smaller than the preset threshold value, the iteration is terminated. Therefore, the false detection probability can be effectively reduced, and the calculation is simple.
In one embodiment, a computer-readable storage medium is provided, on which a decoding program is stored, which, when executed by a processor, implements the aforementioned decoding method.
According to the computer readable storage medium, the false detection probability can be effectively reduced through the decoding method.
In one embodiment, as shown in fig. 5, an electronic device is provided, which includes a memory, a processor, and a decoding program stored in the memory and executable on the processor, where the decoding program is executed by the processor to implement the foregoing decoding method.
In particular, the memory may include a non-volatile storage medium that may store an operating system, computer programs, databases, and the like, and an internal memory that provides an environment for the operating system and computer programs in the non-volatile storage medium to run. The processor is adapted to provide computing and control capabilities that when executed by the computer program implement the aforementioned decoding method. It will be appreciated by those skilled in the art that the structure shown in fig. 5 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the electronic device to which the present application is applied, and that a particular electronic device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
According to the electronic equipment provided by the embodiment of the invention, the false detection probability can be effectively reduced through the decoding method.
In one embodiment, as shown in fig. 6, a decoder is provided, which includes a memory, a processor, and a decoding program stored in the memory and executable on the processor, where the processor implements the foregoing decoding method when executing the decoding program.
In particular, the memory may include a non-volatile storage medium, which may store computer programs, databases, and the like, and an internal memory, which provides an environment for the execution of the computer programs in the non-volatile storage medium. The processor is adapted to provide computing and control capabilities that when executed by the computer program implement the aforementioned decoding method. It will be appreciated by those skilled in the art that the structure shown in fig. 6 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the decoder to which the present application is applied, and that a particular decoder may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
According to the decoder provided by the embodiment of the invention, the false detection probability can be effectively reduced through the decoding method.
In one embodiment, there is provided a decoding apparatus, as shown with reference to fig. 7, including: a verification module 10, a calculation module 20 and a termination module 30.
The verification module 10 is configured to verify a decoded bit sequence of each iteration in the iterative decoding process; the calculating module 20 is configured to calculate a flip ratio of the decoded bit sequence during two iterations in the iterative decoding process; the termination module 30 is configured to terminate the iteration when the current decoded bit sequence is successfully verified and the flip ratio is less than a preset threshold value.
In one embodiment, the calculating module 20 is further configured to perform a modulo-2 addition on the decoded bit sequence of the two previous and subsequent iterations, and calculate the flip ratio according to the modulo-2 addition result.
In one embodiment, the checking module 10 is further configured to take the decoded bit sequence as input, generate a cyclic redundancy check CRC code, and determine that the decoded bit sequence is successfully checked when the CRC code is all 0.
In one embodiment, the calculating module 20 is further configured to calculate a posterior probability of each transmitted bit in the variable node update process, and make a hard decision on the posterior probability to obtain a decoded bit sequence.
In one embodiment, the decoding apparatus further includes an obtaining module (not shown in the figure) configured to obtain the number of iterations; the termination module 30 is further configured to terminate the iteration if the iteration number reaches a preset maximum iteration number when the current decoded bit sequence fails to verify or the flip ratio is greater than or equal to a preset threshold value.
For specific limitations of the decoding apparatus, reference may be made to the above limitations of the decoding method, and no further description is given here. The various modules in the above-described decoding apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
According to the decoding device provided by the embodiment of the invention, the decoding bit sequence of each iteration is checked in the iterative decoding process, the turnover proportion of the decoding bit sequence in the two previous and subsequent iterations is calculated, and the iteration is terminated when the current decoding bit sequence is successfully checked and the turnover proportion is smaller than the preset threshold value. Thus, the false detection probability can be effectively reduced.
In one embodiment, a decoder is provided, including the foregoing decoding apparatus.
According to the decoder provided by the embodiment of the invention, the error detection probability can be effectively reduced through the decoding device.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. A method of decoding, comprising:
in the iterative decoding process, verifying the decoding bit sequence of each iteration, and calculating the turnover proportion of the decoding bit sequence in the two previous and subsequent iterations, wherein the decoding bit sequence is the decoding result of the sending bit sequence;
and stopping iteration when the current decoding bit sequence is successfully checked and the turnover proportion is smaller than a preset threshold value.
2. The decoding method of claim 1, wherein calculating the flip ratio of the decoded bit sequence in two iterations before and after comprises:
and carrying out modulo-2 addition operation on the decoded bit sequences iterated before and after, and calculating the turnover proportion according to the modulo-2 addition operation result.
3. The decoding method of claim 1, wherein verifying the decoded bit sequence for each iteration comprises:
and taking the decoded bit sequence as input, generating a cyclic redundancy detection (CRC) code, and determining that the decoded bit sequence is successfully checked when the CRC code is all 0.
4. A decoding method according to any of claims 1-3, characterized in that the decoded bit sequence is obtained according to the following steps:
and in the variable node updating process, calculating the posterior probability of each transmitted bit, and performing hard decision on the posterior probability to obtain the decoding bit sequence.
5. The decoding method of claim 1, further comprising:
acquiring iteration times;
and when the verification of the current decoding bit sequence fails or the turnover proportion is larger than or equal to a preset threshold value, if the iteration number reaches a preset maximum iteration number, ending the iteration.
6. A computer-readable storage medium, on which a decoding program is stored, which decoding program, when executed by a processor, implements the decoding method according to any one of claims 1-5.
7. An electronic device comprising a memory, a processor and a decoding program stored on the memory and executable on the processor, the processor implementing the decoding method according to any one of claims 1-5 when executing the decoding program.
8. A decoder comprising a memory, a processor and a decoding program stored on the memory and executable on the processor, the processor implementing the decoding method according to any of claims 1-5 when executing the decoding program.
9. A decoding apparatus, comprising:
the verification module is used for verifying the decoding bit sequence of each iteration in the iterative decoding process, wherein the decoding bit sequence is the decoding result of the sending bit sequence;
the calculation module is used for calculating the turnover proportion of the decoding bit sequence in the iterative decoding process in the two times of iteration;
and the termination module is used for terminating iteration when the current decoding bit sequence is successfully checked and the turnover proportion is smaller than a preset threshold value.
10. The decoding device of claim 9, further comprising an acquisition module configured to acquire a number of iterations;
the termination module is further configured to terminate the iteration if the iteration number reaches a preset maximum iteration number when the current decoding bit sequence fails to check or the flip ratio is greater than or equal to a preset threshold value.
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