CN103905063B - Decoding method for LDPC coder - Google Patents

Abstract

The invention discloses a decoding method for an LDPC coder. When a layered decoding algorithm is adopted and decoding of each layer is completed, except whether a calibration equation is met, whether overturn of sign bit decodes of all posteriori information (please find the formula in the specification) participating in the decoding happens is further calculated, and correctness and completeness of the termination condition of an HiTx result calculated previously are ensured. According to the decoding method for the LDPC coder, when hardware is achieved, the fault iteration termination situation can be avoided by only adding a small quantity of hardware logics so that the decoding condition of the system can be more complete and a lower bit error rate can be obtained. The decoding method for the LDPC coder can enable a fall line transitional zone of the bit error rate of the LDPC coder to be narrower and enable an error code flat layer to be lower.

Description

A kind of method that ldpc decoder terminates decoding

Technical field

The present invention relates to a kind of method terminating decoding, the method that particularly a kind of ldpc decoder terminates decoding.

Background technology

In whole communication system, channel coding is a very important part, and it ensure that the reliability of communication system. Mobile communication increasingly tends to real time high-speed transmission now, and user is closer to the concern of data reliability in this case, Therefore, the algorithm research to the channel coding with excellent in performance and hardware realize particularly important.Low-density checksum LDPC (Low Density Parity check, LDPC) code is one of key technology of mobile communication, its excellent error-correcting performance and Its applications well prospect in channel transmitting, has become as the study hotspot that current field of channel coding attracts most attention. The trend replacing Turbo code is readily apparent that, it will be in deep space communication, fiber optic communication, satellite by LDPC code in many cases Digital video and audio broadcasting, magnetic optical/Hologram Storage, movement and fixed radio communication, cable modulator/demodulator and numeral are used It is used widely in family line (DSL).Such as 10 GBICs (10GBASE-T), Digital European mobile broadcast (DVB- S2), WiMax (802.16e), the radio individual of Wi-Fi (802.11n), state's CMMB standard (CMMB) and 60GHz The communication standards such as LAN WPAN (802.15.3c) all adopt LDPC code as channel decoding scheme.

LDPC code is the special linear block codes of a class, and special character is that non-zero entry in its parity check matrix H The number of element is considerably less, far smaller than the number of neutral element, so LDPC code can be defined by its check matrix.According to verification square Often whether row is equal with the number of nonzero element in each column for battle array H, and LDPC code can be divided into regular LDPC code and irregular LDPC codes. In the check matrix of regular LDPC code, each row comprise d_vIndividual nonzero element, every a line comprises d_cIndividual nonzero element, if code length is N, (N, d then can be designated as_v,d_c).What formula (1) represented is exactly the regular LDPC code of (10,3,6), corresponding check equations formula such as formula (2) Shown.

According to statistics, in modern communication chip, there are nearly 1/2 area, 1/3 power consumption in channel decoding mould Block, it can be seen that the performance quality of channel decoding module will determine cost and the complexity of communication chip, also will determine numeral Video transmitter and the quality of receiver, and then determine company competitiveness commercially.So designing and Implementing one High-performance, bottom surface amass and the ldpc decoder of more low-power consumption is most important for whole system.

LDPC decoding algorithm has material impact to design of encoder.The decoding algorithm of LDPC is numerous at present, main flow algorithm Including：Sum-product algorithm, minimum-sum algorithm, hierarchical algorithm and residual, information algorithm etc..Wherein minimum-sum algorithm and hierarchical algorithm are The algorithm that design of encoder mainly adopts at present, these algorithms are all based on the thought of iterative decoding, need certain iterations Complete to decode.During ldpc decoder realizes aspect, the resource shared by memory is topmost, so how to design one It is design key that individual memory resource takies few ldpc decoder.It is typically all to adopt in the realization of the ldpc decoder of early stage Realizing, it controls simple minimum-sum algorithm, is easier to realize.It is nearly all to ldpc decoder recently using hierarchical algorithm Carry out hardware realization, hierarchical algorithm does not need to store intermediate variable nodal information, and convergence rate is faster than minimum-sum algorithm One times, storage money is greatly saved, especially strict to power consumption requirements ldpc decoder has very big attraction.

Hierarchical algorithm is a kind of parallel iterative decoding algorithm, first updates all of check-node in iteration, then Update all of variable node again, and the renewal of check-node can only be using the bit node information in last iterative process. For the information of the updated variable node of utilization as early as possible, accelerate the convergent iterations speed of code word.

Binary phase shift keying (BPSK) is adopted to modulate under additive white Gaussian noise (AWGN) channel, hierarchical algorithm decodes Process is as follows：

(1) initialize：

Set maximum iteration time I_max

Posterior information initializes：(0≤j<N).y_jReceive Soft Inform ation, σ for channel²For Noise variance, N is LDPC code word length

Checking information initializes：(0≤i<M).M is check matrix line number

(2) iterative step:I=0,1 ..., M-1；

A) check informationUpdate：

α is correction factor, and k is current iteration number of times

B) posterior informationUpdate：

(3) judgement of code word x and check equations calculate

If H^TX=0 or reach maximum iteration time I_max, then terminate decoding, otherwise return step Suddenly (2) continue iteration, and iterations adds one.

When having been carried out to ldpc decoder when hardware is realized using hierarchical algorithm, terminate in advance decoding to realize high-performance, The ldpc decoder of more low-power consumption is most important for whole system.In prior art,

The larger decoding iteration number of times I of the general ratio fixing by setting_max, each decoding all iterates to maximum times I_max Just exit decoding.A kind of also scheme terminating decoding, that is, translate whether completely a layering calculates this layering Sufficient check equations, until all layerings all meet check equations (H^TX=0) then terminate decoding.The maximum shortcoming of the first scheme Being that power consumption is too big, because not needing in most cases to iterate to maximum times, leading to the decoder most of the time doing " idle work ", so hardly adopt this method in practical application.Second scheme, as shown in figure 1, CMMB standard 3/4 Totally nine layers of the check matrix H of code check, every layer of Hi (1≤i<10) size is 256x9216.When decoder, to have translated ground floor simultaneously complete Check equations H1 calculating ground floor are become^TWhether x is 0, and then the decoding second layer and calculating second layer check equations H2^TX is No is 0, by that analogy until having calculated H9^TTill whether x is 0, then an iteration completes, as all H1^Tx,H2^Tx,…, H9^TX is that when 0, then decoder output decodes result.This scheme realizes ldpc decoder shortcoming, such as when having decoded first Layer and H1^TX=0, and then the process of the decoding second layer may be the symbol of the posterior information of ground floor participation calculating check equations Number change so that H1^TX is not 0 again.When all check equations of such calculating all expire (Hi^TX=0), but decoding not necessarily complete But terminate decoding in advance, that is, the completeness terminating decoding condition is inadequate when correct.Bit error rate (BER) performance requirement is compared High system, such as, the digital satellite broadcasting such as ABS, dvb-s2, especially for ABS only one of which LDPC channel decoder System, in addition only one bit mistake be likely to lead to video below to show that a sheet of mosaic occurs in key position.

Content of the invention

The technical problem to be solved is, not enough for prior art, provides a kind of ldpc decoder to terminate translating The method of code, solves the problems, such as that existing method power consumption is big, it is incomplete to terminate decoding condition, bit error rate is high.

For solving above-mentioned technical problem, the technical solution adopted in the present invention is：A kind of ldpc decoder terminates decoding Method, the method is：

1) initialize：Emulation determines maximum iteration time I_max, posterior informationAnd variable node informationInitially Value0≤j<N, y_jThe Soft Inform ation receiving for channel, σ²For noise variance, N is LDPC code word Length；Initializing test information：I=0,1 ..., M-1；M is check matrix line number；

2) make k=1；

3) following formula is utilized to update checking information

Wherein,c_iFor i-th check-node, v_jFor j-th variable node, M(c_i) represent the bit symbol information aggregate constraining with verification code element i phase, M (c_i)/v_jRepresent M (c_i) do not comprise v_jSubset, α For correction factor, 0<α<1；Sgn () is sign function；

4) following formula is utilized to update posterior information

5) judgeWhether it is equal toIfIt is equal to AndThen terminate decoding；Or reach maximum iteration time I_max, then terminate decoding；Otherwise, the value of k is added 1, return 3)；Wherein H_iFor i-th layer of check matrix,

Compared with prior art, the present invention had the advantage that for：The present invention removes while every layer of decoding completes It is outer whether calculating check equations meet, and also calculates all posterior informations participating in this decodingBefore and after sign bit decoding it is No occur overturning the Hi it is ensured that being calculated^TThe correctness of x result and the completeness of end condition；When hardware of the present invention is realized Only need to add a small amount of hardware logic it is prevented that the termination iteration situation of mistake occurs, system closure decoding condition can be made More complete and obtain lower bit error rate, be particularly useful high order modulation communication receiver system when, the method for the present invention can So that the fall line intermediate zone of hard-wired ldpc decoder bit error rate is narrower.

Brief description

Fig. 1 is one embodiment of the invention check matrix schematic diagram；

Fig. 2 is one embodiment of the invention method flow diagram；

Fig. 3 realizes block diagram for one embodiment of the invention.

Specific embodiment

Hardware-implemented logic block diagram such as Fig. 3 of the present invention, specific implementation step is as follows:S1, required for this layer is decodedInformation and check information take out from posterior information memory module and check information memory module respectively, and handleSign bit Keep in.S2, sends data into arithmetic element computing and updates check information and posterior informationS3, calculates check equations Hi^TX and judge whether sign bit overturns by XOR.S4, is stored back to memory module new posterior information and check information.If S3 meets then, output decoding result, otherwise returns S1 and starts next iteration until reaching the maximum iteration time setting.

All meet H in order to solve all check equations^TX=0, but terminate decoding in advance when decoding is not necessarily completely correct Problem, the present invention participates in this and decodes except calculating check equations and whether meet outer also calculating while every layer of decoding completes All posterior informationsWhether occur overturning, that is, before and after sign bit decodingWhether it is equal toAs figure 2.The Hi being calculated before this ensure that^TThe correctness of x result and the completeness of end condition.As each layer of Hi^TX is 0 And each layer participated in decodeJust export this when symbol does not all change before and after decoding and decode result.

Method of the present invention step is as follows：

(1) initialize：

Set maximum iteration time I_max,(0≤j<N).y_jReceive soft letter for channel Breath, σ²For noise variance, N is LDPC code word length

Checking information initializes：(0≤i<M).M is check matrix line number

(2) iterative step:I=0,1 ..., M-1；

A) check informationUpdate：

α is correction factor, and k is current iteration number of times；

B) posterior informationUpdate：

C) calculate whether sign bit overturnsWhether it is equal to

C) every layer of information participating in calculating makes decisionsAnd calculate Hi^TWhether x is 0；

(3) exit iteration judgement

If all Hi^TX is 0 and every layer of sign bit calculating all does not overturn or reach maximum iteration time I_max, then Terminate decoding, otherwise return to step (2) continues iteration, iterations adds one.

It is as follows that hardware-implemented logic block diagram such as Fig. 3 of the present invention, decoding and decoding terminate step:S1, required for the decoding of this layer WantInformation and check information take out from posterior information memory module and check information memory module respectively, and handle Sign bit is kept in.S2, sends data into arithmetic element computing and updates check information and posterior informationS3, calculates school Proved recipe journey Hi^TX and judge whether sign bit overturns by XOR.S4, is stored back to new posterior information and check information to store mould Block.If S3 meets, output decoding result, otherwise return S1 and start next iteration until reaching the greatest iteration setting time Number.

Claims (1)

1. a kind of ldpc decoder terminates the method for decoding it is characterised in that the method comprises the following steps：

1) initialize：Emulation determines maximum iteration time I_max, posterior informationAnd variable node informationInitial value0≤j<N, y_jThe Soft Inform ation receiving for channel, σ²For noise variance, N is LDPC code word length Degree；Initializing test information：I=0,1 ..., M-1；M is check matrix line number；

2) make k=1；

3) following formula is utilized to update checking information

${m^k}_{c_i\&RightArrow;v_j}=\mathrm{\&alpha;}\&CenterDot;\underset{v_n\&Element;M\left(c_i\right)/v_j}{\&Pi;}\mathrm{sgn}\left({m^{k-1}}_{v_n\&RightArrow;c_i}\right)\&CenterDot;\underset{v_n\&Element;M\left(c_i\right)/v_j}{min}\left|{m^{k-1}}_{v_n\&RightArrow;c_i}\right|;$

Wherein,c_iFor i-th check-node, v_jFor j-th variable node, M (c_i) represent the bit symbol information aggregate constraining with verification code element i phase, M (c_i)/v_jRepresent M (c_i) do not comprise v_jSubset, α is Correction factor, 0<α<1；Sgn () is sign function；

4) following formula is utilized to update posterior information

5) judgeWhether it is equal toIfIt is equal toAndThen terminate decoding；Or reach maximum iteration time I_max, then terminate decoding；Otherwise, the value of k is added 1, return 3)； Wherein H_iFor i-th layer of check matrix,