CN112953569A - Decoding method and device, storage medium, electronic device, and decoder - Google Patents

Decoding method and device, storage medium, electronic device, and decoder Download PDF

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CN112953569A
CN112953569A CN202110152508.3A CN202110152508A CN112953569A CN 112953569 A CN112953569 A CN 112953569A CN 202110152508 A CN202110152508 A CN 202110152508A CN 112953569 A CN112953569 A CN 112953569A
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decoding
bit sequence
iteration
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CN112953569B (en
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匡肃奉
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

The application relates to a decoding method and device, a storage medium, electronic equipment and a decoder, wherein the method comprises the following steps: in the iterative decoding process, checking the decoded bit sequence of each iteration, and calculating the turning proportion of the decoded bit sequence in the two iterations; and terminating the iteration when the current decoding bit sequence is successfully checked and the turnover ratio is smaller than a preset threshold value. Therefore, the false detection probability can be effectively reduced.

Description

Decoding method and device, storage medium, electronic device, and decoder
Technical Field
The present application relates to the field of decoding technologies, and in particular, to a decoding method and apparatus, a storage medium, an electronic device, and a decoder.
Background
A Low Density Parity Check (LDPC) code is widely used in a modern digital communication system as a linear block code whose performance approaches the shannon limit. Belief Propagation (BP) decoding algorithm is widely applied to decoding of low density parity check codes due to its characteristic of massive parallel processing. The basic idea of belief propagation decoding is to exchange messages between variable nodes and check nodes, and the specific implementation is that after the variable nodes (check nodes) receive messages of all the check nodes (variable nodes) connected with the variable nodes, the messages transmitted to the check nodes (variable nodes) are updated, the updated messages are transmitted to the check nodes (variable nodes) connected with the check nodes, and thus, the messages are transmitted iteratively.
In the related art, the low-density parity check code and the cyclic redundancy check code are combined to perform iteration termination judgment, wherein if the cyclic redundancy check code is verified correctly, decoding is terminated and is considered to be correct, but the error detection probability which is not negligible is caused.
Disclosure of Invention
In view of the above, it is desirable to provide a decoding method and apparatus, a storage medium, an electronic device, and a decoder, which can effectively reduce the false detection probability.
A method of decoding, comprising:
in the iterative decoding process, checking the decoded bit sequence of each iteration, and calculating the turning proportion of the decoded bit sequence in the two iterations;
and terminating the iteration when the verification of the current decoding bit sequence is successful and the turnover ratio is smaller than a preset threshold value.
A computer readable storage medium, on which a decoding program is stored, the decoding program, when executed by a processor, implementing the decoding method as described above.
An electronic device comprises a memory, a processor and a decoding program stored on the memory and capable of running on the processor, wherein when the processor executes the decoding program, the decoding method is realized.
A decoder comprises a memory, a processor and a decoding program which is stored on the memory and can run on the processor, wherein when the processor executes the decoding program, the decoding method is realized.
A decoding device, comprising:
the check module is used for checking the decoding bit sequence of each iteration in the iterative decoding process;
the calculation module is used for calculating the turnover ratio of the decoded bit sequence in the iteration decoding process for two times;
and the termination module is used for terminating the iteration when the current decoding bit sequence is successfully checked and the turnover ratio is smaller than a preset threshold value.
A decoder comprises the decoding device.
According to the decoding method and device, the storage medium, the electronic equipment and the decoder, in the iterative decoding process, the decoded bit sequence of each iteration is checked, the overturning proportion of the decoded bit sequence in the two iterations before and after is calculated, and the iteration is terminated when the current decoded bit sequence is successfully checked and the overturning proportion is smaller than a preset threshold value. Therefore, the false detection probability can be effectively reduced.
Drawings
FIG. 1 is a schematic diagram of the basic architecture of a modern digital communication system;
FIG. 2 is a diagram of Tanner of low density parity check code in the related art;
FIG. 3 is a flow chart of decoding iteration in the related art;
FIG. 4 is a flow chart of a decoding method according to one embodiment of the present invention;
FIG. 5 is a block diagram of an electronic device according to one embodiment of the invention;
FIG. 6 is a block diagram of a decoder according to one embodiment of the invention;
FIG. 7 is a block diagram of a decoding device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that, referring to fig. 1, a modern digital communication system may include a source, a channel encoder, a modulator, a channel, a demodulator, a channel decoder, and a sink.
The source is the issuer of the information and is used to generate a binary bit stream of the information to be transmitted.
The channel encoder is used to encode the binary bit stream to improve the ability of the receiving end to identify errors, thereby reducing the bit error rate to improve the quality of the recovered information. Specifically, in the transmission process of a digital signal in a channel, due to the non-ideal digital transmission characteristics of the actual channel and the presence of additive noise, an Error code may be generated at a receiving end, and in order to control an Error, an Automatic repeat Request (ARQ) Error detection technique and a Forward Error Correction (FEC) encoding technique are generally applied to a channel encoder, so as to improve the reliability of information transmission, and further reduce an Error rate to improve the quality of recovered information. The most commonly used forward error correction coding techniques at present are: convolutional codes, TURBO codes, low density parity check codes, polar codes, etc.
The modulator is used to map (carry) the coded binary bit stream onto a carrier to improve spectral efficiency. Generally, the modulator adopts an IQ Modulation (specifically, data is divided into two paths, carrier Modulation is performed respectively, and the two paths of carriers are orthogonal to each other), and the corresponding common Modulation methods include Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QAM), and the like.
A channel is a channel for information transfer, i.e., a medium through which electromagnetic waves propagate, and in a wireless communication system, a channel is a free space. When information is transmitted through a channel, a noise source may damage transmitted information, and the noise source may be generally classified into external noise and internal noise according to its source, where the external noise includes various electromagnetic wave interferences existing in the nature, and the internal noise refers to various noises generated by an electronic device itself.
The demodulator is used for detecting the binary bit sent by the sending end by using a certain criterion according to the modulation mode of the modulator at the sending end. At present, soft demodulation is mainly adopted, so as to obtain soft bits corresponding to transmission bits, that is, Log Likelihood Ratio (LLR) of the transmission bits, which is defined as follows:
Figure BDA0002932480080000041
wherein, LLR (v)n) Indicates the transmission bit vnCorresponding soft bit, pr(yn|vnA) represents a transmission bit vnReceiving symbol y when anA ∈ {0, 1 }; ln (·) represents a logarithmic operation.
The channel decoder is used for decoding the soft bit information obtained by demodulation according to the forward error correction coding technology adopted by the channel encoder at the sending end by adopting a certain decoding rule to obtain the binary bit information sent by the sending end. Common coding algorithms include Maximum Likelihood (ML) coding, Maximum a Priori Probability (MAP) coding, Belief Propagation (BP) coding, and the like.
The information sink is a receiver of the information and is used for receiving the binary bit information obtained by decoding and converting the binary bit information to obtain the information sent by the information source.
The low density parity check code is widely applied to modern digital communication systems as a linear block code with performance approaching to the shannon limit. Block codes are generally expressed as (n, k), in which an input information sequence is grouped into k symbols, and a channel encoder generates r redundant symbols (called check symbols) according to a certain rule for each information group, so as to form a codeword with a length of n ═ k + r. When the relationship between the information symbols and the check symbols of a block code is linear, the block code is referred to as a linear block code. Linear block codes have two important matrices: generating a matrix G and a check matrix H, for any one input information sequence u ═ u (u)0,u1,...uk-1) The corresponding code word of length N is v ═ u · G and H · vT0, wherein vTIndicating that the vector v is transposed.
The low density parity check code is defined as a null space of the check matrix H satisfying the following characteristics: 1) each row has ρ non-0 elements; 2) each column has lambda non-0 elements; 3) compared to the code length N and the number of rows of the check matrix H, both ρ and λ are much smaller, i.e. the check matrix H has a sparse property.
The low density parity check code can be represented by a Tanner graph, for example, the check matrix H described below, which is shown in fig. 2.
Figure BDA0002932480080000051
In FIG. 2, the last letterx0,x1,...,x7Is a variable node, i.e. the codeword v ═ v (v)0,v1,...,v7) Corresponding transmitted symbols according to a mapping rule x defined in the 3rd Generation Partner Project (3 GPP) standardn＝1-2vnNamely: bit 0 is mapped to symbol 1; bit 1 is mapped to symbol-1; { s0,s1,s2,s3Is a check node corresponding to four check equations H.vT0, namely:
Figure BDA0002932480080000052
wherein the content of the first and second substances,
Figure BDA0002932480080000053
representing a modulo-2 addition operation. When H (m, n) is 1, it represents check node smAnd variable node xnAre connected, i.e. smX must be included in the corresponding check equationnCorresponding bit vn。
The belief propagation decoding algorithm is widely applied to decoding of the low-density parity-check code due to the characteristic of massive parallel processing. The basic idea of belief propagation decoding is: soft information (or called confidence) is exchanged between variable nodes and check nodes, and the exchanged soft information is called a message. The concrete implementation is as follows: after receiving the messages of all the check nodes (variable nodes) connected to the variable nodes (check nodes), the variable nodes (check nodes) update the messages transmitted to the check nodes (variable nodes), and transmit the updated messages to the check nodes (variable nodes) connected to the variable nodes (check nodes), so that message transmission is performed iteratively, as shown in fig. 3.
The following details each of the processes in fig. 3:
step 1: and (5) initializing.
The input to belief propagation decoding is each transmitted bit vnOf channels, i.e. transmit bits vnLog likelihood ratio of (D), noted as Lr(vn)，It is defined as follows:
Figure BDA0002932480080000061
wherein, ynDenotes the transmitted symbol xnCorresponding received symbol, pr(. cndot.) denotes probability values, ln (. cndot.) denotes logarithm operation.
VN2CN-msg in FIG. 3 represents variable node xnTo check node smMessage of (2), node x of variablenTo check node s connected theretomIs marked as
Figure BDA0002932480080000062
The definition and calculation formula is as follows:
Figure BDA0002932480080000063
wherein S isnRepresentation and variable node xnConnected set of check nodes, Sn\smRepresentation set SnRemoval of element smThe set of the remaining elements that follows,
Figure BDA0002932480080000064
representing a received symbol vector (y)0,y1,...,yN-1) N represents the total number of variable nodes,
Figure BDA0002932480080000065
representing the ith iteration check node sm'To variable node xnThe definition and the calculation formula of the message are shown in the check node updating process. In the initialization process, pair
Figure BDA0002932480080000066
And (3) initializing:
Figure BDA0002932480080000067
step 2): and updating the check node.
Check node smReceives a variable node x from the node connected with the variable node xnAfter the message is transmitted to each variable node connected with the variable node, the message is updated according to the following formula:
Figure BDA0002932480080000071
wherein the content of the first and second substances,
Figure BDA0002932480080000072
Xmrepresentation and check node smConnected sets of variable nodes, Xm\xnA set of representations XmRemoval of element xnThe remaining set of elements.
Step 3): and (5) updating variable nodes.
Variable node xnAfter receiving the message from the check node connected with the check node, according to the method
Figure BDA0002932480080000073
The update formula updates the messages passed to each check node connected to it:
Figure BDA0002932480080000074
at the same time, the variable node calculates its transmitted bit vnA posteriori probability of
Figure BDA0002932480080000075
The definition and calculation formula is as follows:
Figure BDA0002932480080000076
step 4): and judging an iteration termination condition.
In the related art, the iteration termination determination is performed by combining a low-density parity Check code and an error detection code, for example, a Physical Downlink Shared Channel (PDSCH) of a New Radio interface (NR) of a Fifth Generation (5G) mobile communication system employs a forward error correction Channel coding technique of the low-density parity Check code and a common error detection code technique of a Cyclic Redundancy Check (CRC) code to perform the iteration termination determination, which is specifically as follows:
using the A posteriori probability of each transmitted bit calculated in the variable node update process
Figure BDA0002932480080000077
Hard decision is carried out to obtain the decoding result of the sending bit sequence, namely the decoding bit sequence
Figure BDA0002932480080000081
The hard decision is made as follows:
Figure BDA0002932480080000082
then, the decoded bit sequence is decoded
Figure BDA0002932480080000083
And performing cyclic redundancy check, wherein the check process is as follows: will decode the bit sequence
Figure BDA0002932480080000084
As input, generating a cyclic redundancy check code according to a cyclic redundancy check code generation process in 3GPP Release 16, if the generated cyclic redundancy check codes are all zero (namely the remainder is zero), then the cyclic redundancy check is successful, terminating the decoding, and considering that the decoding is correct; otherwise, the cyclic redundancy check is considered to fail, when the iteration times reach the set maximum iteration times, the decoding is terminated, the decoding is considered to fail, and if the maximum iteration times are not reached, the next round of iterative decoding is continued.
As known from 3GPP Release 16, the length of the crc code includes two types, 16 bits and 24 bits, and for the 16-bit crc code, the false detection probability is not negligible, especially for the Ultra-Reliable and Low Latency Communications (URLLC) scenario, which is one of three scenarios in 5G. However, in the above iteration process, as long as the crc is successfully checked, the iteration is terminated, and the decoding result is considered to be correct, thereby resulting in a non-negligible false detection probability.
In order to solve the technical problem, the inventive concept of the present application is: and when the current decoding bit sequence is successfully checked and the turnover ratio of the decoding bit sequence is smaller than a preset threshold value in two iterations, terminating the iteration.
In one embodiment, a decoding method is provided, which can be applied to the channel decoder shown in fig. 1, and referring to fig. 4, the decoding method includes the following steps:
step 402, in the iterative decoding process, the decoded bit sequence of each iteration is checked, and the inversion ratio of the decoded bit sequence in the two iterations is calculated.
For example, referring to fig. 3, in the iterative coding process, one iteration refers to: the check nodes and the variable nodes are updated once, specifically: after receiving the message from the variable node connected with the variable node, the check node updates the message transmitted to each variable node connected with the variable node according to the formula (7) and sends the message to the variable node connected with the variable node, and after receiving the message from the check node connected with the variable node, the variable node updates the message transmitted to each check node connected with the variable node according to the formula (8).
After each iteration is completed, the decoded bit sequence of each iteration is checked, and the turning proportion of the decoded bit sequence in the two iterations is calculated.
The decoded bit sequence is the decoded result of the transmitted bit sequence. Optionally, the decoded bit sequence is obtained according to the following steps: in the variable node updating process, the posterior probability of each sending bit is calculated, and hard decision is carried out on the posterior probability to obtain a decoding bit sequence.
Specifically, after each iteration is completed, the posterior probability of each transmission bit in the current iteration is obtained
Figure BDA0002932480080000091
And a posteriori probability of each transmitted bit at a previous iteration
Figure BDA0002932480080000092
As shown in the above equation (9), and for the posterior probability
Figure BDA0002932480080000093
And
Figure BDA0002932480080000094
and carrying out hard decision to obtain a decoding bit sequence, wherein the hard decision is carried out according to the following formula:
Figure BDA0002932480080000095
obtaining the decoded bit sequence of the current iteration
Figure BDA0002932480080000096
And the decoded bit sequence at the previous iteration
Figure BDA0002932480080000097
Then, the inverse proportion of the decoded bit sequence in two iterations can be calculated. Optionally, calculating a flip ratio of the decoded bit sequence in two iterations includes: and performing modulo-2 addition operation on the decoded bit sequences of the two iterations, and calculating the turnover ratio according to the modulo-2 addition operation result. I.e. for the decoded bit sequence of two iterations before and after
Figure BDA0002932480080000098
And
Figure BDA0002932480080000099
performing modulo-2 addition and counting according to the modulo-2 addition resultCalculating the turning proportion, which is specifically shown by the following formula:
Figure BDA00029324800800000910
at the same time, the decoding bit sequence at the iteration is carried out
Figure BDA00029324800800000911
And (6) checking. Optionally, the checking the decoded bit sequence of each iteration includes: and taking the decoded bit sequence as input, generating a Cyclic Redundancy Check (CRC) code, and determining that the decoded bit sequence is successfully checked when the CRC codes are all 0.
That is, the decoded bit sequence at the current iteration is decoded
Figure BDA0002932480080000101
And as input, generating a cyclic redundancy check CRC code (namely a cyclic redundancy check code) according to a preset cyclic redundancy check code generation algorithm, and judging the CRC code. If the CRC codes are all zero, determining the decoding bit sequence
Figure BDA0002932480080000102
And (6) the verification is successful.
And step 404, terminating iteration when the current decoding bit sequence is successfully checked and the turnover ratio is smaller than a preset threshold value.
After each iteration is finished, the decoding bit sequence of the current iteration is determined by the mode
Figure BDA0002932480080000104
The check is successful, and the calculated flip ratio eta of the decoded bit sequence in two iterations is smaller than a preset threshold value alpha (which can be obtained through simulation), namely, the decoded bit sequence
Figure BDA0002932480080000103
If the verification is successful and eta is less than alpha, the decoding is determined to be correct, and the iteration is terminated; otherwise, the next iteration is continued. That isThat is, when the decoded bit sequence is successfully checked and the turnover ratio is smaller than the preset threshold value during the current iteration, the decoding is considered to be correct, and the iteration is terminated, otherwise, the iteration is continued.
Therefore, compared with the mode of carrying out iteration termination judgment only through the cyclic redundancy check code, the method increases the judgment on the turnover ratio, namely the number of bit turnover, so that the false detection probability can be effectively reduced. And when the iteration is terminated and judged, the turnover ratio is compared with a preset threshold value, and the false detection is considered to occur when the turnover ratio is larger than the preset threshold value. That is to say, compared with the mode of performing iteration termination judgment only through the cyclic redundancy check code and the mode of determining that false detection occurs as long as bit flipping exists, the method has lower false detection probability and greatly improves decoding performance. In addition, compared with a syndrome-based termination iteration judgment mode (the syndrome refers to the product of a correction matrix and a decoding bit vector, and when the decoding is correct, the syndrome is zero), the method does not need matrix multiplication calculation, and is simple in calculation and low in complexity.
Optionally, the decoding method further includes: obtaining iteration times; and when the current decoding bit sequence is failed to be checked or the turnover ratio is greater than or equal to a preset threshold value, if the iteration times reach a preset maximum iteration times, terminating the iteration.
That is, when decoding a bit sequence
Figure BDA0002932480080000111
If the verification fails or eta is larger than or equal to alpha, if the iteration times reach the preset maximum iteration times ImaxThe iteration is terminated to avoid the iteration failing to terminate.
The following describes the effect of the decoding method provided in the present application with reference to table 1.
Table 1 is a comparison table of false detection probabilities and average iteration times of the decoding iteration termination method in the related art and the decoding method using the present application. Wherein, the simulation parameters are set as follows: code block size k 8448, code rate 1/2, α 0.02, ImaxThe number of simulations is set to 20000, 16.
TABLE 1
Figure BDA0002932480080000112
As can be seen from table 1, compared with the decoding iteration termination method in the related art, the error detection rate is reduced by one order of magnitude by using the decoding method of the present application, the average iteration number is hardly increased, and the calculation of the decoding method of the present application is simpler.
In summary, according to the decoding method of the embodiment of the present invention, in the iterative decoding process, the decoded bit sequence of each iteration is checked, the turn-over ratio of the decoded bit sequence in the previous iteration and the next iteration is calculated, and when the check of the current decoded bit sequence is successful and the turn-over ratio is smaller than the preset threshold value, the iteration is terminated. Therefore, the false detection probability can be effectively reduced, and the calculation is simple.
In one embodiment, a computer-readable storage medium is provided, on which a decoding program is stored, which when executed by a processor implements the aforementioned decoding method.
According to the computer-readable storage medium of the embodiment of the invention, the false detection probability can be effectively reduced by the decoding method.
In one embodiment, as shown in fig. 5, an electronic device is provided, which includes a memory, a processor, and a decoding program stored in the memory and executable on the processor, and when the processor executes the decoding program, the decoding method is implemented.
Specifically, the memory may include a nonvolatile storage medium that may store an operating system, a computer program, a database, and the like, and an internal memory that provides an environment for the operating system and the computer program in the nonvolatile storage medium to run. The processor is used to provide the computing and control capabilities when executing the computer program to implement the aforementioned decoding method. Those skilled in the art will appreciate that the configuration shown in fig. 5 is a block diagram of only a portion of the configuration associated with the present application, and does not constitute a limitation on the electronic device to which the present application is applied, and a particular electronic device may include more or less components than those shown in the drawings, or may combine certain components, or have a different arrangement of components.
According to the electronic equipment provided by the embodiment of the invention, the false detection probability can be effectively reduced by the decoding method.
In one embodiment, as shown in fig. 6, there is provided a decoder, which includes a memory, a processor, and a decoding program stored in the memory and executable on the processor, and when the processor executes the decoding program, the decoding method is implemented.
Specifically, the memory may include a nonvolatile storage medium that can store a computer program, a database, and the like, and an internal memory that provides an environment for the computer program in the nonvolatile storage medium to run. The processor is used to provide the computing and control capabilities when executing the computer program to implement the aforementioned decoding method. Those skilled in the art will appreciate that the architecture shown in fig. 6 is a block diagram of only a portion of the architecture associated with the subject application, and does not constitute a limitation on the decoders to which the subject application is applied, and that a particular decoder may include more or fewer components than those shown, or some components may be combined, or have a different arrangement of components.
According to the decoder provided by the embodiment of the invention, the false detection probability can be effectively reduced by the decoding method.
In one embodiment, there is provided a decoding apparatus, as shown with reference to fig. 7, including: a verification module 10, a calculation module 20 and a termination module 30.
The checking module 10 is configured to check a decoded bit sequence of each iteration in an iterative decoding process; the calculating module 20 is configured to calculate a turning ratio of the decoded bit sequence during two iterations in the iterative decoding process; the termination module 30 is configured to terminate the iteration when the current decoded bit sequence is successfully checked and the rollover ratio is smaller than a preset threshold value.
In one embodiment, the calculating module 20 is further configured to perform modulo-2 addition on the decoded bit sequences of the two previous and subsequent iterations, and calculate the inversion ratio according to the modulo-2 addition result.
In one embodiment, the check module 10 is further configured to take the decoded bit sequence as an input, generate a cyclic redundancy check CRC code, and determine that the check on the decoded bit sequence is successful when the CRC code is all 0.
In one embodiment, the calculating module 20 is further configured to calculate a posterior probability of each transmitted bit during the variable node updating process, and perform hard decision on the posterior probability to obtain a decoded bit sequence.
In an embodiment, the decoding apparatus further includes an obtaining module (not shown in the figure) for obtaining the number of iterations; the termination module 30 is further configured to, when the check on the current decoded bit sequence fails or the rollover ratio is greater than or equal to a preset threshold value, terminate the iteration if the iteration number reaches a preset maximum iteration number.
For the specific limitation of the decoding apparatus, reference may be made to the above limitation of the decoding method, which is not described herein again. The modules in the decoding device can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
According to the decoding device provided by the embodiment of the invention, in the iterative decoding process, the decoded bit sequence of each iteration is checked, the turnover ratio of the decoded bit sequence in the two iterations before and after is calculated, and the iteration is terminated when the current decoded bit sequence is successfully checked and the turnover ratio is smaller than the preset threshold value. Therefore, the false detection probability can be effectively reduced.
In one embodiment, a decoder is provided, which comprises the decoding device.
According to the decoder provided by the embodiment of the invention, the false detection probability can be effectively reduced through the decoding device.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A decoding method, comprising:
in the iterative decoding process, checking the decoded bit sequence of each iteration, and calculating the turning proportion of the decoded bit sequence in the two iterations;
and terminating the iteration when the verification of the current decoding bit sequence is successful and the turnover ratio is smaller than a preset threshold value.
2. The decoding method of claim 1, wherein calculating a flip ratio of the decoded bit sequence in two iterations comprises:
and performing modulo-2 addition operation on the decoded bit sequences iterated twice before and after, and calculating the turnover ratio according to the modulo-2 addition operation result.
3. The decoding method of claim 1, wherein checking the decoded bit sequence for each iteration comprises:
and taking the decoded bit sequence as input, generating a Cyclic Redundancy Check (CRC) code, and determining that the decoded bit sequence is successfully checked when the CRC codes are all 0.
4. The decoding method according to any one of claims 1-3, wherein said decoded bit sequence is obtained according to the following steps:
in the process of updating the variable nodes, the posterior probability of each sending bit is calculated, and hard decision is carried out on the posterior probability to obtain the decoding bit sequence.
5. The decoding method of claim 1, further comprising:
obtaining iteration times;
and when the current decoding bit sequence is failed to be checked or the turnover ratio is greater than or equal to a preset threshold value, if the iteration times reach a preset maximum iteration times, terminating the iteration.
6. A computer-readable storage medium, having stored thereon a decoding program which, when executed by a processor, implements a decoding method according to any one of claims 1 to 5.
7. An electronic device comprising a memory, a processor, and a decoding program stored in the memory and executable on the processor, wherein the processor executes the decoding program to implement the decoding method according to any one of claims 1 to 5.
8. A decoder comprising a memory, a processor and a decoding program stored in the memory and executable on the processor, wherein the processor executes the decoding program to implement the decoding method according to any one of claims 1-5.
9. A decoding apparatus, comprising:
the check module is used for checking the decoding bit sequence of each iteration in the iterative decoding process;
the calculation module is used for calculating the turnover ratio of the decoded bit sequence in the iteration decoding process for two times;
and the termination module is used for terminating the iteration when the current decoding bit sequence is successfully checked and the turnover ratio is smaller than a preset threshold value.
10. The decoding device according to claim 9, further comprising an obtaining module for obtaining a number of iterations;
the termination module is further configured to terminate the iteration if the iteration count reaches a preset maximum iteration count when the check on the current decoded bit sequence fails or the rollover ratio is greater than or equal to a preset threshold value.
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