CN108462558B - Method and device for decoding polarization code SCL and electronic equipment - Google Patents

Method and device for decoding polarization code SCL and electronic equipment Download PDF

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CN108462558B
CN108462558B CN201810173286.1A CN201810173286A CN108462558B CN 108462558 B CN108462558 B CN 108462558B CN 201810173286 A CN201810173286 A CN 201810173286A CN 108462558 B CN108462558 B CN 108462558B
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邢莉娟
李卓
魏红丽
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    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract

The embodiment of the invention discloses a method, a device and electronic equipment for decoding a polarization code SCL, belonging to the technical field of channel coding of digital communication, wherein the method comprises the following steps: initializing a received channel output bit sequence; carrying out binarization bit estimation on the current bit in the channel output bit sequence, and sequencing candidate paths according to a metric value obtained by the bit estimation; respectively carrying out competition and path length judgment on the sorted candidate paths to obtain candidate decoding paths meeting the conditions; and performing FC verification on the candidate decoding paths meeting the conditions, and selecting one decoding path with the maximum path metric value from the verified candidate decoding paths as a decoding result. Through the scheme of the application, the decoding performance is improved.

Description

Method and device for decoding polarization code SCL and electronic equipment
Technical Field
The invention belongs to the technical field of channel coding of digital communication, and particularly relates to an SCL decoding algorithm based on Fletcher inspection and assistance in a polarization code.
Background
Polar Codes (Polar Codes) are proposed by e.arika in 2009 based on the Channel polarization phenomenon, and for any given symmetric Binary input Discrete Memoryless Channel (B-DMC), under the Serial Cancellation (SC) decoding algorithm, it is the first Channel coding scheme that strictly proves to reach shannon Channel capacity mathematically, and is a major breakthrough in the field of Channel coding. Due to its unique algebraic structure and low encoding and decoding complexity, it has a great influence in the communication field once it is proposed, and becomes one of the research hotspots in recent years in the channel coding field. In 11 months in 2016, the predominantly push polar code scheme was adopted in the 87 th conference of RAN1 of the third generation partnership project (3GPP), which is a coding scheme for a control channel in an enhanced Mobile Broadband (eMBB) scenario of the fifth generation Mobile communication technology (5G).
The SC decoding algorithm is a depth-first search algorithm and is based on local optimization, however, under a limited code length, the performance of the SC decoding algorithm of the polarization code is not ideal. As an improvement of the SC decoding algorithm, a Successive Cancellation List (SCL) decoding algorithm is proposed, which has decoding performance close to Maximum Likelihood (ML) decoding. In order to further improve the decoding performance of the polarization code, Ido Tal et al uses Cyclic Redundancy Check (CRC) in an SCL decoding algorithm (SCL-CRC), at an encoding end, performs CRC encoding on an original information sequence to obtain a CRC Check sequence, and adds the CRC Check sequence to the tail end of the original information sequence by sacrificing multi-bit information bits, and the two form a source information sequence to be input into an encoder for polarization code encoding; at a decoding end, SCL decoding is firstly carried out, when the SCL decoding is carried out to the final stage, CRC (cyclic redundancy check) is carried out on L candidate decoding paths, paths which do not pass the CRC are directly filtered, and then one path with the largest metric value is selected from all candidate decoding paths meeting the CRC as a decoding result. In the worst case, that is, no L decoding candidate paths pass CRC check, a path with the largest metric value is selected from the L decoding candidate paths as a decoding result, and the decoding performance even exceeds some Low-density Parity-check Codes (LDPC) and Turbo Codes under a specific code length and code rate.
In view of this, the present application proposes a new decoding scheme for the polarization code SCL.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for decoding a polar code SCL, and an electronic device, which at least partially solve the problems in the prior art.
In a first aspect, an embodiment of the present invention provides a method for decoding a polar code SCL, including:
initializing a received channel output bit sequence;
carrying out binarization bit estimation on the current bit in the channel output bit sequence, and sequencing candidate paths according to a metric value obtained by the bit estimation;
respectively carrying out competition and path length judgment on the sorted candidate paths to obtain candidate decoding paths meeting the conditions;
and performing FC verification on the candidate decoding paths meeting the conditions, and selecting one decoding path with the maximum path metric value from the verified candidate decoding paths as a decoding result.
According to a specific implementation method of the embodiment of the invention, initializing a received channel output bit sequence comprises the following steps:
receiving channel output bit sequence
Figure BDA0001586093700000021
The transition probability of each bit is W (y)i|xi)；
And setting the value of the number L of the reserved paths in the decoding process, and setting the initial path as a null path.
According to a specific implementation method of the embodiment of the present invention, the performing binarization bit estimation on the current bit in the channel output bit sequence includes:
respectively calculating the probability that the current bit value is 0 and 1:
Figure BDA0001586093700000022
and
Figure BDA0001586093700000023
if the current bit is a fixed bit, then
Figure BDA0001586093700000024
Otherwise, updating the path metric value, and expanding each current candidate path according to bit 0 or 1.
According to a specific implementation method of the embodiment of the present invention, the performing the competition and the path length judgment on the sorted candidate paths respectively includes:
counting the number of the current candidate paths, if the number of the current candidate paths is less than L, keeping all the current paths, otherwise, keeping the L candidate paths with the maximum path metric value in the current layer, and deleting the rest paths.
According to a specific implementation method of the embodiment of the present invention, the performing the competition and the path length judgment on the sorted candidate paths respectively includes:
and judging whether the length of each current candidate path reaches the code length N, if so, performing FC verification, and otherwise, continuing bit estimation.
According to a specific implementation method of the embodiment of the present invention, the performing FC verification on the candidate decoding paths that meet the condition includes:
and respectively taking out the k-long original information estimation sequence and the h-long check estimation sequence in the candidate decoding path, recalculating the k-long original information estimation sequence by using an FC algorithm to obtain a new h-long check sequence, comparing whether the h-long check estimation sequence is the same as the new h-long check sequence, if so, determining that the current bit estimation sequence passes the FC check, otherwise, not passing the FC check.
According to a specific implementation method of the embodiment of the present invention, the method further includes:
and if the L candidate decoding paths do not pass the FC verification, selecting one path with the maximum path metric value from the L candidate decoding paths as a decoding result.
In a second aspect, an embodiment of the present invention further provides a decoding device for a polar code SCL, including:
the initialization module is used for initializing the received channel output bit sequence;
the estimation module is used for carrying out binarization bit estimation on the current bit in the channel output bit sequence and sequencing candidate paths according to the metric values obtained by the bit estimation;
the judging module is used for respectively carrying out competition and path length judgment on the sorted candidate paths to obtain candidate decoding paths meeting the conditions;
and the processing module is used for performing FC verification on the candidate decoding paths meeting the conditions and selecting one decoding path with the maximum path metric value from the verified candidate decoding paths as a decoding result.
In a third aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method for decoding a polarization code SCL as described in any of the first aspects and any implementation of the first aspects.
According to the method, the device and the electronic equipment for decoding the polar code SCL, provided by the embodiment of the invention, the auxiliary check code is added in the SCL decoding process to improve the error correction performance of the polar code SCL decoding algorithm, so that the frame error rate performance of the polar code SCL decoding algorithm is greatly improved, wherein the frame error rate is 10-3Meanwhile, the SCL-FC decoding algorithm is improved by about 0.7dB of gain relative to the SCL decoding algorithm; compared with the SCL-CRC decoding algorithm based on the same idea, the FC decoding algorithm has the advantages that the decoding performance is the same as that of the SCL-CRC decoding algorithm, the FC decoding algorithm is simple in operation, and the time complexity of generating the check sequence with the same length is lower than that of the CRC.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts:
fig. 1 is a path search diagram of an SC decoding algorithm with an N-3 time slot according to an embodiment of the present invention;
fig. 2 is a path search diagram of an SCL decoding algorithm for a polar code when N is 3 and L is 2 according to an embodiment of the present invention;
FIG. 3 is a block diagram illustrating the operation of a polar code communication scheme using an SCL-CRC decoding algorithm according to an embodiment of the present invention;
FIG. 4 is a flowchart of an SCL-CRC decoding process provided by an embodiment of the present invention;
FIG. 5 is a block diagram illustrating the operation of a polar code communication scheme using an SCL-FC decoding algorithm according to an embodiment of the present invention;
FIG. 6 is a flowchart of an embodiment of the SCL-FC decoding process.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The Fletcher Checksum (FC) algorithm is an error detection algorithm with lower operation amount than the CRC check algorithm, which is proposed by John g.fletcher in 1982 by using a summation technique, is one of Checksum algorithms, and is an improvement of the internet protocol (IPv4) header Checksum algorithm. The following outlines its basic principles for error detection in the field of data communications. At a sending end, firstly, an FC algorithm is used for calculating a k-bit original binary information sequence to obtain an h (h is an even number) bit check sequence, the check sequence is attached to the tail end of the original binary information sequence and sent to a receiving end, the receiving end recalculates the check sequence for the received binary information sequence and compares the check sequence with the received check sequence, if the check sequence and the check sequence are the same, the information transmission is considered to be correct, otherwise, the information transmission is wrong. The h-bit check sequence calculated by the FC algorithm consists of two parts of sum1 and sum2 with the length of h/2, and the specific calculation processes of sum1 and sum2 are as follows:
the first step, equally dividing the k-bit binary information sequence into m (when m is not an integer, 0 is added to the original information sequence finally to make m an integer) blocks, and respectively recording as S0，S1，…，Sm-1Each block contains h/2 bit binary information, and the initial values of sum1 and sum2 are set to the same known value (both set to 0 in this application).
Second, sum1 and sum2 are calculated using the inverse code operation of 1 (i.e., adding the high bits to the low bits when the high bits overflow during the binary addition operation), and the calculation formula is as follows:
Figure BDA0001586093700000051
Figure BDA0001586093700000052
the h-bit check sequence is a combination of sum1 and sum2, namely sum2 is added at the end of sum 1.
Based on the SCL-CRC decoding structure, the FC algorithm is used for replacing the CRC algorithm for auxiliary checking, the FC-assisted SCL decoding algorithm (SCL-FC) for the polar code is provided, the method not only greatly improves the frame error rate performance of the SCL decoding algorithm, but also is simple in operation of the FC algorithm and lower in time complexity of generating a check sequence with the same length than the CRC algorithm when the same decoding performance is achieved compared with the SCL-CRC decoding algorithm.
The polarization code is proposed based on the channel polarization phenomenon, the channel polarization is divided into two processes of channel combination and channel separation, when the number of combined channels tends to infinity, a part of channels become good and tend to be noiseless channels through polarization, useful information is transmitted by using the channels, the other part of channels become poor and tend to be pure noise channels, and fixed information known by a receiver and a sender is transmitted by using the channels. The polarization encoding process of the polarization code is briefly described below.
Let a symmetric B-DMC W be defined as: x → Y, X being the input symbol set, Y being the output symbol set, W (Y | X) being the channel transition probability, where X is for X, Y is for Y, and X is for {0, 1},
Figure BDA0001586093700000061
setting the length of the polarization code as N2n(N is a natural number), the information bit length is K, the fixed bit length is N-K, and a combined channel vector W is obtained by combining N W channelsNThe channel transition probability is:
Figure BDA0001586093700000062
here, W (y)i|xi) The channel transition probability for the ith bit,
Figure BDA0001586093700000063
in order to be the source bit sequence,
Figure BDA0001586093700000064
in order to encode a sequence of bits, the bit sequence,
Figure BDA0001586093700000065
outputting a bit sequence for the channel, wherein
Figure BDA0001586093700000066
And is
Figure BDA0001586093700000067
And
Figure BDA0001586093700000068
the following relationships exist:
Figure BDA0001586093700000069
here, ,
Figure BDA00015860937000000610
is a reversible generator matrix of size NxN dimensions, in which
Figure BDA00015860937000000611
Figure BDA0001586093700000071
Expressed as an n-dimensional kronecker product of a matrix, BNThe matrix is inverted for the bit sequence. Obtaining N different polarized sub-channels through channel separation, and recording the N different polarized sub-channels as
Figure BDA0001586093700000072
The polarized subchannel transfer probability is:
Figure BDA0001586093700000073
wherein
Figure BDA0001586093700000074
Figure BDA0001586093700000075
Is that
Figure BDA0001586093700000076
The sub-vectors of (2).
In all polarized sub-channels
Figure BDA0001586093700000077
In the method, K most reliable sub-channels are selected to transmit information bit sequence
Figure BDA0001586093700000078
Figure BDA0001586093700000079
Is a set of information bits that are,
Figure BDA00015860937000000710
transmitting fixed bit sequences for the remaining N-K unreliable sub-channels
Figure BDA00015860937000000711
Figure BDA00015860937000000712
Is a fixed bit set of
Figure BDA00015860937000000713
Complement of (2), moreover
Figure BDA00015860937000000714
Known to the transceiver, when the sender sends information and the receiver recovers it
Figure BDA00015860937000000715
The value is set to a fixed value, usually 0.
The work to be done by the decoding is based on
Figure BDA00015860937000000716
Obtaining a source bit sequence
Figure BDA00015860937000000717
Is estimated bit sequence
Figure BDA00015860937000000718
The polar code can be decoded by an SC decoding algorithm having a low decoding complexity o (nlogn), but the algorithm is sequentially decoded, and when one bit is decided to be erroneous, it is impossible to correct the error in the decoding process thereafter. When in use
Figure BDA00015860937000000719
When it is, then
Figure BDA00015860937000000720
Otherwise, the coding criteria are as follows:
Figure BDA00015860937000000721
the SC decoding process can be regarded as a process of performing path search on a code tree, and the path search is defined from a root node to the first node on the code treeiThe decoding path of a layer is
Figure BDA0001586093700000081
The path metric being that the path is in the second placeiLayer(s)
Figure BDA0001586093700000082
Probability of value 0 or 1, i.e.
Figure BDA0001586093700000083
Or
Figure BDA0001586093700000084
Calculating the metric values of two decoding paths expanded by the successive nodes in turn from the root node, and reserving one path with a larger metric value each time if the metric value is on the second nodeiWhen the layer is to be expanded, the layer is expanded,
Figure BDA0001586093700000085
then, without calculating the path metric value, will directly
Figure BDA0001586093700000086
The value of (d) is 0. The path searching process is carried out layer by layer, the searching is finished when the leaf nodes are met, and the finally obtained searching path is a decoding result, namely
Figure BDA0001586093700000087
Fig. 1 is an example of a path search diagram of the SC decoding algorithm.
The SC decoding algorithm may lose the ML path in the path expanding process, and in order to reduce the possibility of losing the correct code word, the SCL decoding algorithm is provided. The algorithm is an improved algorithm of the SC decoding algorithm, and different from the SC decoding algorithm that only one path is reserved when each layer of path is expanded, the SCL decoding algorithm reserves at most L candidate paths, wherein L is a positive integer. In the process of SCL decoding, each information bit
Figure BDA0001586093700000088
Both candidate paths are preserved, i.e.
Figure BDA0001586093700000089
And
Figure BDA00015860937000000810
the number of paths is doubled. There is an upper limit to the number of paths, up to L. When the number of paths is not more than L, the number of paths is continuously doubled; when the number of paths is greater than L, the path pruning operation is carried out, only the front L paths with the maximum metric value are reserved, and the rest paths are deleted. When the decoding is finished, selecting one path with the maximum metric value from the L paths as a decoding result, wherein the SCL decoding complexity isO (LNlogN). When L is 1. The SCL decoding algorithm is degenerated to the SC decoding algorithm. Fig. 2 is an example of a path search graph of the SCL decoding algorithm.
In the SCL decoding process, the metric of the correct path is not always the largest, so when SCL decoding proceeds to the last bit, selecting the path with the largest metric as the output will also cause decoding errors at a certain probability. Therefore, the CRC can be used in an SCL decoding algorithm (SCL-CRC), which is an improvement of the SCL decoding algorithm, and the good error detection performance of the CRC is utilized to obtain better decoding performance of the algorithm. At the encoding end, performing CRC encoding on a K-bit original information sequence to obtain an h-bit CRC check sequence, attaching the CRC check sequence to the tail end of the original information sequence by sacrificing the h-bit information bits, and forming a K-bit source information sequence by the H-bit information bits and the CRC check sequence to be input into an encoder to perform polarization code encoding; at a decoding end, SCL decoding is firstly carried out, when the SCL decoding is carried out to the final stage, CRC (cyclic redundancy check) is carried out on L candidate decoding paths, paths which do not pass the CRC are directly filtered, and then one path with the largest metric value is selected from all candidate decoding paths meeting the CRC as a decoding result. And in the worst case, namely, if all the L decoding candidate paths do not pass the CRC check, selecting one path with the largest metric value from the L decoding candidate paths as a decoding result. The following first gives a block diagram of the operation flow of the polar code communication scheme using the SCL-CRC decoding algorithm as shown in fig. 3, and then gives a flow diagram of the SCL-CRC decoding process as shown in fig. 4.
The SCL-CRC decoding algorithm comprises the following specific steps:
(I) inputting: receiving channel output bit sequence
Figure BDA0001586093700000091
The transition probability of each bit is W (y)i|xi)。
(II) initialization: and setting the value of the number L of the reserved paths in the decoding process, and setting the initial path as a null path.
(III) bit estimation: expanding each current candidate path according to bit 0 or 1, if the current bit is a fixed bit, then
Figure BDA0001586093700000092
Otherwise, updating the path metric value, namely respectively calculating the probability that the current bit value is 0 and 1:
Figure BDA0001586093700000093
and
Figure BDA0001586093700000094
the candidate paths are sorted by metric value.
(IV) competition: counting the number of the current candidate paths, and if the number of the current candidate paths is less than L, reserving the current paths; otherwise, the L candidate paths with the maximum path metric value in the current layer are kept, and the rest paths are deleted.
(V) determining path length: judging whether the length of each current candidate path reaches the code length N, if so, turning to (VI); otherwise, go to (III).
(VI) CRC checking: and performing CRC check on each candidate decoding path one by one according to the output sequence.
(VII) judgment: and selecting one decoding path with the largest path metric value from all candidate decoding paths passing the CRC check as a decoding result. And if the L candidate decoding paths do not pass the CRC check, selecting one path with the maximum path metric value from the L candidate decoding paths as a decoding result.
For the medium-short code length polarization code adopting the SCL decoding algorithm, the error correction performance of the medium-short code length polarization code still has a larger difference with the Shannon limit, and the difference cannot be made up by increasing the number of paths alone, so that the auxiliary check code is added in the SCL decoding process to improve the error correction performance of the SCL decoding algorithm, but the SCL-CRC decoding algorithm uses the CRC algorithm in the polarization pre-coding stage, namely CRC coding is carried out before polarization coding and CRC checking is carried out in the final decoding stage, and the CRC algorithm is based on polynomial division operation of a coefficient on GF (2), and has complex operation and high time complexity. In order to solve the problems, the FC algorithm is used for replacing the CRC algorithm, the SCL-FC decoding algorithm is provided, the decoding algorithm not only greatly improves the frame error rate performance of the SCL decoding algorithm of the polarization code, but also has the advantages that compared with the SCL-CRC decoding algorithm, the FC algorithm is based on simple integer summation operation, the operation is simple, and the time complexity of generating the check sequence with the same length is lower than that of the CRC algorithm when the same decoding performance is achieved.
Using SCL-FC decoding algorithm, at the encoding end, firstly performing FC encoding, namely using FC algorithm to calculate K-bit original information sequence to obtain h-bit FC check sequence, adding the FC check sequence to the tail end of the original information sequence by sacrificing h-bit information bit, and then forming K-bit source information sequence by the two to input into an encoder to perform polarization code encoding; at a decoding end, SCL decoding is firstly carried out, when the SCL decoding is carried out to the final stage, FC verification is carried out on L candidate decoding paths, paths which do not pass the FC verification are directly filtered, and then one path with the largest metric value is selected from all candidate decoding paths which pass the FC verification to serve as a decoding result. In the worst case, that is, all the L decoding candidate paths do not pass FC verification, one path with the largest metric value is selected from the L decoding candidate paths as the decoding result. The operation flow diagram of the polar code communication scheme using the SCL-FC decoding algorithm is shown in FIG. 5, and the operation flow diagram of the SCL-FC decoding algorithm is shown in FIG. 6.
The specific steps of the SCL-FC decoding algorithm are as follows:
(I) inputting: receiving channel output bit sequence
Figure BDA0001586093700000111
The transition probability of each bit is W (y)i|xi)。
(II) initialization: and setting the value of the number L of the reserved paths in the decoding process, and setting the initial path as a null path.
(III) bit estimation: each current candidate path is extended by bit 0 or 1. If the current bit is a fixed bit, then
Figure BDA0001586093700000112
Otherwise, updating the path metric value, namely respectively calculating the probability that the current bit value is 0 and 1:
Figure BDA0001586093700000113
and
Figure BDA0001586093700000114
the candidate paths are sorted by metric value.
(IV) competition: counting the number of the current candidate paths, and if the number of the current candidate paths is less than L, reserving the current paths; otherwise, the L candidate paths with the maximum path metric value in the current layer are reserved, and the rest paths are deleted.
(V) determining path length: judging whether the length of each current candidate path reaches the code length N, if so, turning to (VI); otherwise, go to (III).
(VI) FC verification: and performing FC (fiber channel) check on each candidate decoding path one by one according to the output sequence. The FC check process for each candidate decoding path is as follows: respectively taking out a k-long original information estimation sequence and an h-long check estimation sequence in a candidate decoding path, recalculating the k-long original information estimation sequence by using an FC algorithm to obtain a new h-long check sequence, comparing whether the h-long check estimation sequence is the same as the new h-long check sequence, if so, determining that the current bit estimation sequence passes the FC check, otherwise, determining that the current bit estimation sequence does not pass the FC check, and determining that the current bit estimation sequence does not pass the FC check.
(VII) judgment: and selecting one decoding path with the maximum path metric value from all the candidate decoding paths passing through the FC verification as a decoding result. And if the L candidate decoding paths do not pass the FC verification, selecting one path with the maximum path metric value from the L candidate decoding paths as a decoding result.
Experimental tests show that the SCL-FC decoding algorithm greatly improves the frame error rate performance of the SCL decoding algorithm, and the frame error rate is 10-3Meanwhile, the SCL-FC decoding algorithm is improved by about 0.7dB of gain relative to the SCL decoding algorithm; and the performance of the SCL-FC decoding algorithm is almost the same as that of the SCL-CRC decoding algorithm.
In the decoding process of SCL-FC and SCL-CRC, the FC algorithm and the CRC algorithm only act on k long information bit bits, in order to analyze the complexity difference of the two more intuitively, the fixed code rate R is 0.5, and the code length N of the polarization code is used for describing instead of k. Setting generation of h-bit check bits, the FC algorithm is based on simple integer summation operation, and the time complexity is O (N); the CRC decoding algorithm is based on a polynomial division operation of coefficients over GF (2) with a temporal complexity of o (hn). The additional factor h does not affect the time complexity of the FC algorithm, so the FC algorithm is less time complex than the CRC algorithm.
It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof.
In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (7)

1. A FC-assisted polar code SCL decoding method is characterized by comprising the following steps:
initializing a received channel output bit sequence;
carrying out binarization bit estimation on the current bit in the channel output bit sequence, and sequencing candidate paths according to a metric value obtained by the bit estimation;
respectively carrying out competition and path length judgment on the sorted candidate paths to obtain candidate decoding paths meeting the conditions;
performing FC verification on the candidate decoding paths meeting the conditions, and selecting one decoding path with the maximum path metric value from the verified candidate decoding paths as a decoding result;
wherein,
the binarizing bit estimation of the current bit in the channel output bit sequence comprises:
respectively calculating the probability that the current bit value is 0 and 1:
Figure FDA0002755591690000011
and
Figure FDA0002755591690000012
if the current bit is a fixed bit, then
Figure FDA0002755591690000013
Otherwise, updating the path metric value, and expanding each current candidate path according to bit 0 or 1;
the performing FC check on the eligible candidate decoding paths includes:
respectively taking out a k-long original information estimation sequence and an h-long check estimation sequence in a candidate decoding path, recalculating the k-long original information estimation sequence by using an FC algorithm to obtain a new h-long check sequence, comparing whether the h-long check estimation sequence is the same as the new h-long check sequence, if so, determining that the current bit estimation sequence passes the FC check, otherwise, not passing the FC check;
the h-bit check sequence calculated by the FC algorithm consists of two parts of sum1 and sum2 with the length of h/2, and the specific calculation processes of sum1 and sum2 are as follows:
the first step, equally dividing the k-bit binary information sequence into m (when m is not an integer, 0 is added to the original information sequence finally to make m an integer) blocks, and respectively recording as S0，S1，…，Sm-1Each block contains h/2-bit binary information, and the initial values of sum1 and sum2 are set to the same known value (both set to 0 in this application);
second, sum1 and sum2 are calculated using the inverse code operation of 1 (i.e., adding the high bits to the low bits when the high bits overflow during the binary addition operation), and the calculation formula is as follows:
Figure FDA0002755591690000021
Figure FDA0002755591690000022
the h-bit check sequence is a combination of sum1 and sum2, namely sum2 is added at the end of sum 1.
2. The method of claim 1, wherein initializing the received channel output bit sequence comprises:
receiving channel output bit sequence
Figure FDA0002755591690000023
The transition probability of each bit is W (y)i|xi)；
And setting the value of the number L of the reserved paths in the decoding process, and setting the initial path as a null path.
3. The method of claim 1, wherein the performing contention and path length determination processing on the sorted candidate paths respectively comprises:
counting the number of the current candidate paths, if the number of the current candidate paths is less than L, keeping all the current paths, otherwise, keeping the L candidate paths with the maximum path metric value in the current layer, and deleting the rest paths.
4. The method of claim 1, wherein the performing contention and path length determination processing on the sorted candidate paths respectively comprises:
and judging whether the length of each current candidate path reaches the code length N, if so, performing FC verification, and otherwise, continuing bit estimation.
5. The method of claim 1, wherein the method further comprises:
and if the L candidate decoding paths do not pass the FC verification, selecting one path with the maximum path metric value from the L candidate decoding paths as a decoding result.
6. An FC-assisted polar code SCL decoding device implemented according to any one of claims 1 to 5, comprising:
the initialization module is used for initializing the received channel output bit sequence;
the estimation module is used for carrying out binarization bit estimation on the current bit in the channel output bit sequence and sequencing candidate paths according to the metric values obtained by the bit estimation;
the judging module is used for respectively carrying out competition and path length judgment on the sorted candidate paths to obtain candidate decoding paths meeting the conditions;
and the processing module is used for performing FC verification on the candidate decoding paths meeting the conditions and selecting one decoding path with the maximum path metric value from the verified candidate decoding paths as a decoding result.
7. An electronic device, characterized in that the electronic device comprises:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the polar code SCL decoding method of any of the preceding claims 1-5.
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