CN108462558B - A kind of polar code SCL decoding method, device and electronic equipment - Google Patents

Abstract

Embodiments of the present invention disclose a polar code SCL decoding method, device and electronic equipment, which belong to the technical field of channel coding for digital communication. The method includes: initializing a received channel output bit sequence; The current bit in the bit sequence is subjected to binarization bit estimation, and the candidate paths are sorted according to the metric value obtained from the bit estimation; code path; FC check is performed on the qualified candidate decoding paths, and a decoding path with the largest path metric value is selected from the checked candidate decoding paths as a decoding result. Through the solution of the present application, the decoding performance is improved.

Description

A kind of polar code SCL decoding method, device and electronic equipment

technical field

The invention belongs to the technical field of channel coding of digital communication, and in particular relates to an SCL decoding algorithm based on Fletcher checksum assistance in polar codes.

Background technique

Polar Codes (Polar Codes) was proposed by E. Arikan in 2009 based on the channel polarization phenomenon. For any given symmetric binary input discrete memoryless channel (Binary-input Discrete Memoryless Channel, B-DMC), in the serial Under the Successive Cancellation (SC) decoding algorithm, it is the first channel coding scheme that can be mathematically proved strictly to reach the Shannon channel capacity, and is a major breakthrough in the field of channel coding. Because of its unique algebraic structure and low coding and decoding complexity, it has a great influence in the field of communication once it is proposed, and it has become one of the research hotspots in the field of channel coding in recent years. In November 2016, at the 87th meeting of RAN1 of the 3rd Generation Partnership Project (3GPP), an international wireless standardization organization, the polar code scheme promoted by Huawei became the fifth generation mobile communication technology (5G) enhanced mobile broadband (5G). The coding scheme of the control channel in the Enhance Mobile Broadband, eMBB) scenario.

SC decoding algorithm is a depth-first search algorithm based on local optimum. However, the performance of SC decoding algorithm of polar codes is not ideal under the limited code length. As an improvement of the SC decoding algorithm, a Successive Cancellation List (SCL) decoding algorithm is proposed, and its decoding performance is close to that of the Maximum Likelihood (ML) decoding. In order to further improve the decoding performance of polar codes, Ido Tal et al. used Cyclic Redundancy Check (CRC) in the SCL decoding algorithm (SCL-CRC). The CRC check sequence is obtained by CRC encoding. By sacrificing multiple information bits, the CRC check sequence is appended to the end of the original information sequence. The two form the source information sequence and input it into the encoder for polar code encoding. SCL decoding, when the SCL decoding is in the final stage, CRC check is performed on L candidate decoding paths, and the paths that fail the CRC check are directly filtered out, and then all candidate decoding paths that satisfy the CRC check are decoded A path with the largest metric value among the paths is selected as the decoding result. In the worst case, that is, none of the L candidate decoding paths have passed the CRC check, the path with the largest metric value is selected from the L candidate decoding paths as the decoding result. At the same time, its decoding performance even exceeds some low-density parity-check codes (Low-density Parity-check Codes, LDPC) and Turbo codes.

In view of this, this application proposes a new polar code SCL decoding scheme.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present invention provide a polar code SCL decoding method, apparatus, and electronic device, which at least partially solve the problems existing in the prior art.

In a first aspect, an embodiment of the present invention provides a polar code SCL decoding method, including:

Initialize the received channel output bit sequence;

Perform binarization bit estimation on the current bit in the channel output bit sequence, and sort the candidate paths according to the metric value obtained from the bit estimation;

Performing competition and path length judgment processing on the sorted candidate paths, respectively, to obtain qualified candidate decoding paths;

FC checking is performed on the qualified candidate decoding paths, and a decoding path with the largest path metric value is selected from the checked candidate decoding paths as a decoding result.

According to a specific implementation method of the embodiment of the present invention, initializing the received channel output bit sequence includes:

每个比特的转移概率为W(y_i|x_i)；Receive channel output bit sequence

The transition probability of each bit is W(y _i | _xi );

Set the value of the number of paths L reserved in the decoding process, and set the initial path as an empty path.

According to a specific implementation method of the embodiment of the present invention, the performing binarization bit estimation on the current bit in the channel output bit sequence includes:

和

Calculate the probability that the current bit is 0 and 1, respectively:

and

否则更新路径度量值，将当前每条候选路径按比特0或1进行扩展。If the current bit is a fixed bit, then

Otherwise, the path metric is updated, and each current candidate path is extended by bit 0 or 1.

According to a specific implementation method of the embodiment of the present invention, the process of performing competition and path length judgment processing on the sorted candidate paths respectively includes:

Count the number of current candidate paths. If the number of current candidate paths is less than L, keep all the current paths. Otherwise, keep the L candidate paths with the largest path metric value in the current layer, and delete the rest.

According to a specific implementation method of the embodiment of the present invention, the process of performing competition and path length judgment processing on the sorted candidate paths respectively includes:

It is judged whether the current length of each candidate path reaches the code length N, and if it is equal to N, the FC check is performed, otherwise, the bit estimation is continued.

According to a specific implementation method of the embodiment of the present invention, the performing FC check on the qualified candidate decoding paths includes:

Take out the k-length original information estimation sequence and the h-length check estimation sequence in the candidate decoding path respectively, use the FC algorithm to recalculate the k-length original information estimation sequence to obtain a new h-length check sequence, and compare the h-length check estimation sequence Whether it is the same as the new h-length check sequence, if it is the same, it is considered that the current bit estimation sequence has passed the FC check; otherwise, it has not passed the FC check.

According to a specific implementation method of an embodiment of the present invention, the method further includes:

If none of the L candidate decoding paths pass the FC check, a path with the largest path metric value is selected from the L candidate decoding paths as the decoding result.

In a second aspect, an embodiment of the present invention also provides a polar code SCL decoding apparatus, including:

an initialization module, used to initialize the received channel output bit sequence;

an estimation module, configured to perform binarization bit estimation on the current bits in the channel output bit sequence, and sort the candidate paths according to the metric values obtained by the bit estimation;

a judgment module, configured to perform competition and path length judgment processing on the sorted candidate paths respectively, to obtain qualified candidate decoding paths;

The processing module is configured to perform FC check on the qualified candidate decoding paths, and select a decoding path with the largest path metric value from the checked candidate decoding paths as a decoding result.

In a third aspect, an embodiment of the present invention further provides an electronic device, the electronic device comprising:

at least one processor; and,

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the foregoing first aspects and any of the first aspects. The polar code SCL decoding method described in an implementation manner.

In the polar code SCL decoding method, device, and electronic device provided by the embodiments of the present invention, an auxiliary check code is added in the SCL decoding process to improve the error correction performance of the polar code SCL decoding algorithm, which not only greatly improves the polarization The frame error rate performance of the code SCL decoding algorithm, when the frame error rate is 10 ^-3 , the SCL-FC decoding algorithm improves the gain of about 0.7dB compared with the SCL decoding algorithm; The SCL-CRC decoding algorithm achieves the same decoding performance as the FC algorithm, and the operation of the FC algorithm is simple, and the time complexity of generating a check sequence of the same length is lower than that of the CRC.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort:

1 is a path search diagram of a polar code SC decoding algorithm when N=3 according to an embodiment of the present invention;

2 is a path search diagram of a polar code SCL decoding algorithm when N=3 and L=2 provided by an embodiment of the present invention;

3 is a block diagram of an operation flow of a polar code communication scheme using an SCL-CRC decoding algorithm provided by an embodiment of the present invention;

4 is a flowchart of an SCL-CRC decoding process provided by an embodiment of the present invention;

5 is a block diagram of an operation flow of a polar code communication scheme using an SCL-FC decoding algorithm provided by an embodiment of the present invention;

FIG. 6 is a flowchart of an SCL-FC decoding process provided by an embodiment of the present invention.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The Fletcher Checksum (FC) algorithm is an error detection algorithm proposed by John G. Fletcher in 1982 using the summation technique with a lower computational complexity than the CRC check algorithm. It is one of the checksum algorithms. It is an improvement of the Internet Protocol (IPv4) header checksum algorithm. The basic principle of its use in error detection in the field of data communication is described below. At the sending end, first use the FC algorithm to calculate the k-bit original binary information sequence to obtain the h (h is an even number) bit check sequence, and append the check sequence to the end of the original binary information sequence and send it to the receiving end. The received binary information sequence recalculates the check sequence and compares it with the received check sequence. If the two are the same, it is considered that the information transmission is correct; otherwise, there is an error in the information transmission. Among them, the h-bit check sequence calculated by the FC algorithm consists of two parts, sum1 and sum2, both of which have a length of h/2. The specific calculation process of sum1 and sum2 is as follows:

In the first step, the k-bit binary information sequence is divided into m equal blocks (when m is not an integer, 0 is added at the end of the original information sequence, so that m is an integer) blocks, which are respectively denoted as S ₀ , S ₁ , ..., S _m-1 , each block contains h/2 bits of binary information, and the initial values of sum1 and sum2 are both set to the same known value (both set to 0 in this application).

The second step is to use the one's complement operation (that is, in the process of binary addition, when the high bit overflows, add the high bit to the low bit) to calculate sum1 and sum2. The calculation formula is as follows:

The h-bit check sequence is a combination of sum1 and sum2, that is, appending sum2 to the end of sum1.

Based on the decoding structure of SCL-CRC, this application uses the FC algorithm instead of the CRC algorithm for auxiliary verification, and proposes an FC-assisted polar code SCL decoding algorithm (SCL-FC), which not only greatly improves the polar code SCL The frame error rate performance of the decoding algorithm, and compared with the SCL-CRC decoding algorithm, while achieving the same decoding performance as the FC algorithm, the operation of the FC algorithm is simple, and the time complexity of generating a check sequence of the same length is higher than that of the CRC algorithm. Low.

Polar codes are proposed based on the phenomenon of channel polarization. Channel polarization is divided into two processes: channel combination and channel separation. When the number of combined channels tends to be infinite, after polarization, some channels become very good and tend to be non-existent. Noise channels are used to transmit useful information, and another part of the channel becomes very poor and tends to be pure noise channels. These channels are used to transmit fixed information known to both the sender and the receiver. The polar coding process of polar codes is briefly described below.

设极化码码长为N＝2ⁿ(n为自然数)，信息位长度为K，固定位长度为N-K，经过N个W信道组合，得到组合信道向量W_N，其信道转移概率为：Let a symmetric B-DMC W be defined as: X→Y, X is the input symbol set, Y is the output symbol set, W(y|x) is the channel transition probability, where x∈X, y∈Y, X∈{0 ,1},

Suppose the length of polar code is N=2 ⁿ (n is a natural number), the length of information bits is K, and the length of fixed bits is NK. After N W channel combinations, the combined channel vector W _N is obtained, and its channel transition probability is:

为源比特序列，

为编码比特序列，

为信道输出比特序列，其中

并且

与

有如下关系：Here, W(y _i |x _i ) is the channel transition probability of the i-th bit,

is the source bit sequence,

is the encoded bit sequence,

output bit sequence for the channel, where

and

and

There are the following relationships:

是一个大小为N×N维的可逆生成矩阵，其中here,

is an invertible generator matrix of size N × N dimensions, where

表示为一个矩阵的n维克罗内克积，B_N为比特序列翻转矩阵。经过信道分离，得到N个不同的极化子信道，记为

极化子信道转移概率为：

Represented as the n Vikroneck product of a matrix, B _N is the bit sequence flip matrix. After channel separation, N different polarized sub-channels are obtained, denoted as

The polar sub-channel transition probability is:

是

的子向量。in

Yes

subvector of .

中，选择K个最可靠的子信道传输信息比特序列

是信息位集合，

其余N-K个不可靠子信道传输固定比特序列

是固定位集合，是

的补集，而且

对收发方是已知的，在发送端发送信息和接收端恢复信息时，把

设为固定的值，通常设为0。in all polarized sub-channels

, select the K most reliable sub-channel transmission information bit sequences

is the set of information bits,

The remaining NK unreliable subchannels transmit fixed bit sequences

is a fixed-bit set, yes

complement of , and

It is known to the sender and receiver, when the sender sends information and the receiver recovers the information, the

Set to a fixed value, usually 0.

得到源比特序列

的估计比特序列

极化码可以通过SC译码算法进行译码，SC译码算法具有较低的译码复杂度O(NlogN)，但该算法是顺序译码的，当一个比特被判决错误时，在其后面的译码过程中纠正这个错误是不可能的。当

时，则

否则，译码准则如下：The work to be done by decoding is based on

get the source bit sequence

The estimated bit sequence of

The polar code can be decoded by the SC decoding algorithm. The SC decoding algorithm has a low decoding complexity O(NlogN), but the algorithm is sequentially decoded. When a bit is judged incorrectly, the following It is impossible to correct this error during the decoding process. when

time, then

Otherwise, the decoding criteria are as follows:

路径度量值为该路径在第_i层

取值为0或1的概率即

或

从根节点开始，依次计算后继节点所扩展出的两条译码路径的度量值，每次保留度量值大的一条路径，如果在对第_i层进行扩展时，

则不计算路径度量值，直接将

的值判为0。上述路径搜索过程是逐层进行的，遇到叶子节点时搜索结束，最后得到的搜索路径即为译码结果，即

图1为SC译码算法的路径搜索图示例。The SC decoding process can be regarded as a process of path searching on the code tree. The decoding path from the root node to the _i -th layer on the decoding tree is defined as

The path metric is the path at level _i

The probability of taking a value of 0 or 1 is

or

Starting from the root node, calculate the metric values of the two decoding paths extended by the subsequent nodes in turn, and keep a path with a larger metric value each time. If the _i -th layer is extended,

Then the path metric value is not calculated, and the

value is 0. The above path search process is carried out layer by layer, and the search ends when a leaf node is encountered, and the final search path obtained is the decoding result, that is,

FIG. 1 is an example of a path search graph of the SC decoding algorithm.

都会保留两条候选路径，即

和

路径数会加倍。路径数有一个上限，最多L条。当路径数不大于L时，路径数会不断地加倍；当路径数大于L时，就会进行修剪路径操作，只保留度量值最大的前L条路径，其余路径被删除。译码结束时，就从L条路径中选择一条度量值最大路径的作为译码结果，SCL译码复杂度为O(LNlogN)。当L＝1时。SCL译码算法就退化为SC译码算法。图2为SCL译码算法的路径搜索图示例。The SC decoding algorithm may lose the ML path in the process of path expansion. In order to reduce the possibility of losing the correct codeword, the SCL decoding algorithm is proposed. This algorithm is an improved algorithm of SC decoding algorithm. Unlike SC decoding algorithm, which only retains one path when each layer path is expanded, SCL decoding algorithm retains L candidate paths at most, where L is a positive integer. During SCL decoding, each information bit

will keep two candidate paths, namely

and

The number of paths will be doubled. The number of paths has an upper limit, at most L. When the number of paths is not greater than L, the number of paths will be continuously doubled; when the number of paths is greater than L, the path trimming operation will be performed, only the first L paths with the largest metric value are retained, and the rest are deleted. At the end of decoding, a path with the largest metric value is selected from the L paths as the decoding result, and the SCL decoding complexity is O(LNlogN). when L=1. The SCL decoding algorithm degenerates into the SC decoding algorithm. FIG. 2 is an example of a path search graph of the SCL decoding algorithm.

In the SCL decoding process, the metric value of the correct path may not always be the largest. Therefore, when the SCL decoding reaches the last bit, selecting the path with the largest metric value as the output may also cause decoding errors with a certain probability. Therefore, CRC can be used in the SCL decoding algorithm (SCL-CRC), which is an improvement of the SCL decoding algorithm. The good error detection performance of CRC enables this algorithm to obtain better decoding performance. At the encoding end, perform CRC encoding on the k-bit original information sequence to obtain an h-bit CRC check sequence. By sacrificing the h-bit information bits, the CRC check sequence is attached to the end of the original information sequence, and the two form the K-bit source information sequence input. The encoder performs polar code encoding; at the decoding end, SCL decoding is performed first, and when the SCL decoding reaches the final stage, CRC verification is performed on the L candidate decoding paths, and the paths that fail the CRC verification are directly checked. Filter out, and then select a path with the largest metric value from all the candidate decoding paths that satisfy the CRC check as the decoding result. In the worst case, that is, none of the L candidate decoding paths pass the CRC check, a path with the largest metric value is selected from the L candidate decoding paths as the decoding result. The following first provides a block diagram of the operation flow of the polar code communication scheme using the SCL-CRC decoding algorithm, as shown in Figure 3, and then provides a flow chart of the SCL-CRC decoding process, as shown in Figure 4.

The specific steps of the SCL-CRC decoding algorithm are as follows:

每个比特的转移概率为W(y_i|x_i)。(I) Input: Receive channel output bit sequence

The transition probability of each bit is W(y _i | _xi ).

(II) Initialization: Set the value of the number of paths L reserved in the decoding process, and set the initial path as an empty path.

否则更新路径度量值，即分别计算出当前比特取值为0和1的概率：

和

将候选路径按度量值排序。(III) Bit estimation: Extend each current candidate path by bit 0 or 1. If the current bit is a fixed bit, then

Otherwise, update the path metric value, that is, calculate the probability that the current bit is 0 and 1 respectively:

and

Sort candidate paths by metric value.

(IV) Competition: Count the number of current candidate paths, if the number of current candidate paths is less than L, keep all the current paths; otherwise, keep the L candidate paths with the largest path metric value in the current layer, and delete the rest.

(V) Judging path length: Judging whether the length of each current candidate path reaches the code length N, if it is equal to N, go to (VI); otherwise, go to (III).

(VI) CRC check: CRC check is performed on each candidate decoding path one by one according to the output order.

(VII) Decision: select a decoding path with the largest path metric value as the decoding result from all the candidate decoding paths that have passed the CRC check. If none of the L candidate decoding paths pass the CRC check, a path with the largest path metric value is selected from the L candidate decoding paths as the decoding result.

For the medium and short code length polar codes using the SCL decoding algorithm, there is still a big gap between the error correction performance and the Shannon limit, and this gap cannot be made up by increasing the number of paths alone. Therefore, considering the SCL decoding process The auxiliary check code is added to improve the error correction performance of the polar code SCL decoding algorithm, but the SCL-CRC decoding algorithm performs CRC coding in the polar precoding stage, that is, before polar coding, and performs CRC in the final stage of decoding. The CRC algorithm is used in the verification, and the CRC algorithm is based on the polynomial division operation of the coefficients on GF(2), which is complicated in operation and high in time complexity. In order to solve the above problems, this application uses the FC algorithm instead of the CRC algorithm, and proposes the SCL-FC decoding algorithm, which not only greatly improves the frame error rate performance of the polar code SCL decoding algorithm, but also compares with the SCL algorithm. -CRC decoding algorithm, while achieving the same decoding performance, because the FC algorithm is based on a simple integer summation operation, the operation is simple, and the time complexity of generating a check sequence of the same length is lower than that of the CRC algorithm.

Using the SCL-FC decoding algorithm, at the encoding end, FC encoding is first performed, that is, the FC algorithm is used to calculate the k-bit original information sequence to obtain the h-bit FC check sequence. By sacrificing the h-bit information bits, the FC check sequence is added. At the end of the original information sequence, the two form a K-bit source information sequence, which is input to the encoder for polar code encoding; at the decoding end, SCL decoding is performed first, and when the SCL decoding reaches the final stage, the L candidate The decoding path is subjected to FC verification, and the paths that fail the FC verification are directly filtered out, and then the path with the largest metric value is selected from all the candidate decoding paths that have passed the FC verification as the decoding result. In the worst case, that is, none of the L candidate decoding paths pass the FC check, a path with the largest metric value is selected from the L candidate decoding paths as the decoding result. The block diagram of the operation flow of the polar code communication scheme using the SCL-FC decoding algorithm is shown in Figure 5, and the flow chart of the SCL-FC decoding is shown in Figure 6.

The specific steps of the SCL-FC decoding algorithm are as follows:

每个比特的转移概率为W(y_i|x_i)。(I) Input: Receive channel output bit sequence

The transition probability of each bit is W(y _i | _xi ).

(II) Initialization: Set the value of the number of paths L reserved in the decoding process, and set the initial path as an empty path.

否则更新路径度量值，即分别计算出当前比特取值为0和1的概率：

和

将候选路径按度量值排序。(III) Bit estimation: extend each current candidate path by bit 0 or 1. If the current bit is a fixed bit, then

Otherwise, update the path metric value, that is, calculate the probability that the current bit is 0 and 1 respectively:

and

Sort candidate paths by metric value.

(IV) Competition: Count the number of current candidate paths. If the number of current candidate paths is less than L, keep all the current paths; otherwise, keep the L candidate paths with the largest path metric value in the current layer, and delete the rest.

(V) Judging path length: Judging whether the length of each current candidate path reaches the code length N, if it is equal to N, go to (VI); otherwise, go to (III).

(VI) FC check: perform FC check on each candidate decoding path one by one according to the output order. The FC check process of each candidate decoding path is as follows: respectively take out the k-length original information estimation sequence and h-length check estimation sequence in the candidate decoding path, and use the FC algorithm to recalculate the k-length original information estimation sequence to obtain a new h-length check sequence, compare whether the h-length check estimation sequence and the new h-length check sequence are the same. If they are the same, the current bit estimation sequence is considered to have passed the FC check; otherwise, it will fail the FC check. fc.

(VII) Decision: select a decoding path with the largest path metric value as the decoding result from all the candidate decoding paths that have passed the FC check. If none of the L candidate decoding paths pass the FC check, a path with the largest path metric value is selected from the L candidate decoding paths as the decoding result.

Through experimental tests, it can be seen that the SCL-FC decoding algorithm greatly improves the frame error rate performance of the polar code SCL decoding algorithm. When the frame error rate is 10 ^-3 , the SCL-FC decoding algorithm is better than the SCL decoding algorithm. A gain of about 0.7dB is achieved; and the performance of the SCL-FC decoding algorithm is almost the same as that of the SCL-CRC decoding algorithm.

In the SCL-FC and SCL-CRC decoding process, the FC algorithm and the CRC algorithm only act on the k-long information bits. In order to analyze the complexity difference between the two more intuitively, the fixed code rate R=0.5, and the polar code is used. The code length N is replaced by k to describe. Assuming that h-bit check bits are generated, the FC algorithm is based on a simple integer summation operation, and the time complexity is O(N); the CRC decoding algorithm is based on the polynomial division operation of the coefficients on GF(2), and the time complexity is The degree is O(hN). The extra factor h does not affect the time complexity of the FC algorithm, so the time complexity of the FC algorithm is lower than that of the CRC algorithm.

It should be noted that, in the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations There is no such actual relationship or order between them. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion such that a process, method, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments.

In particular, for the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and reference may be made to some descriptions of the method embodiments for related parts.

The logic and/or steps represented in flowcharts or otherwise described herein, for example, may be considered an ordered listing of executable instructions for implementing the logical functions, may be embodied in any computer-readable medium, For use with, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch instructions from and execute instructions from an instruction execution system, apparatus, or apparatus) or equipment. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or apparatus. More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections with one or more wiring (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), Read Only Memory (ROM), Erasable Editable Read Only Memory (EPROM or Flash Memory), Fiber Optic Devices, and Portable Compact Disc Read Only Memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, followed by editing, interpretation, or other suitable medium as necessary process to obtain the program electronically and then store it in computer memory.

It should be understood that various parts of the present invention may be implemented in hardware, software, firmware or a combination thereof.

In the above-described embodiments, various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following techniques known in the art: Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, Programmable Gate Arrays (PGA), Field Programmable Gate Arrays (FPGA), etc.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (7)

1. A FC-assisted polar code SCL decoding method is characterized by comprising the following steps:

initializing a received channel output bit sequence;

carrying out binarization bit estimation on the current bit in the channel output bit sequence, and sequencing candidate paths according to a metric value obtained by the bit estimation;

respectively carrying out competition and path length judgment on the sorted candidate paths to obtain candidate decoding paths meeting the conditions;

performing FC verification on the candidate decoding paths meeting the conditions, and selecting one decoding path with the maximum path metric value from the verified candidate decoding paths as a decoding result;

wherein,

the binarizing bit estimation of the current bit in the channel output bit sequence comprises:

respectively calculating the probability that the current bit value is 0 and 1:

and

if the current bit is a fixed bit, then

Otherwise, updating the path metric value, and expanding each current candidate path according to bit 0 or 1;

the performing FC check on the eligible candidate decoding paths includes:

respectively taking out a k-long original information estimation sequence and an h-long check estimation sequence in a candidate decoding path, recalculating the k-long original information estimation sequence by using an FC algorithm to obtain a new h-long check sequence, comparing whether the h-long check estimation sequence is the same as the new h-long check sequence, if so, determining that the current bit estimation sequence passes the FC check, otherwise, not passing the FC check;

the h-bit check sequence calculated by the FC algorithm consists of two parts of sum1 and sum2 with the length of h/2, and the specific calculation processes of sum1 and sum2 are as follows:

the first step, equally dividing the k-bit binary information sequence into m (when m is not an integer, 0 is added to the original information sequence finally to make m an integer) blocks, and respectively recording as S₀，S₁，…，S_m-1Each block contains h/2-bit binary information, and the initial values of sum1 and sum2 are set to the same known value (both set to 0 in this application);

second, sum1 and sum2 are calculated using the inverse code operation of 1 (i.e., adding the high bits to the low bits when the high bits overflow during the binary addition operation), and the calculation formula is as follows:

the h-bit check sequence is a combination of sum1 and sum2, namely sum2 is added at the end of sum 1.

2. The method of claim 1, wherein initializing the received channel output bit sequence comprises:

receiving channel output bit sequence

The transition probability of each bit is W (y)_i|x_i)；

And setting the value of the number L of the reserved paths in the decoding process, and setting the initial path as a null path.

3. The method of claim 1, wherein the performing contention and path length determination processing on the sorted candidate paths respectively comprises:

counting the number of the current candidate paths, if the number of the current candidate paths is less than L, keeping all the current paths, otherwise, keeping the L candidate paths with the maximum path metric value in the current layer, and deleting the rest paths.

4. The method of claim 1, wherein the performing contention and path length determination processing on the sorted candidate paths respectively comprises:

and judging whether the length of each current candidate path reaches the code length N, if so, performing FC verification, and otherwise, continuing bit estimation.

5. The method of claim 1, wherein the method further comprises:

and if the L candidate decoding paths do not pass the FC verification, selecting one path with the maximum path metric value from the L candidate decoding paths as a decoding result.

6. An FC-assisted polar code SCL decoding device implemented according to any one of claims 1 to 5, comprising:

the initialization module is used for initializing the received channel output bit sequence;

the estimation module is used for carrying out binarization bit estimation on the current bit in the channel output bit sequence and sequencing candidate paths according to the metric values obtained by the bit estimation;

the judging module is used for respectively carrying out competition and path length judgment on the sorted candidate paths to obtain candidate decoding paths meeting the conditions;

and the processing module is used for performing FC verification on the candidate decoding paths meeting the conditions and selecting one decoding path with the maximum path metric value from the verified candidate decoding paths as a decoding result.

7. An electronic device, characterized in that the electronic device comprises:

at least one processor; and the number of the first and second groups,

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the polar code SCL decoding method of any of the preceding claims 1-5.

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