CN114784101A - Folded silicon LIGBT with additional electrode and manufacturing method thereof - Google Patents
Folded silicon LIGBT with additional electrode and manufacturing method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 20
- 239000010703 silicon Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 239000007769 metal material Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- -1 phosphorus ions Chemical class 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 108091006146 Channels Proteins 0.000 description 19
- 239000004065 semiconductor Substances 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention relates to a transistor device, in particular to a folded silicon LIGBT with an extra electrode and a manufacturing method thereof. The technical problem that the tail end of a gate electrode extending in the existing transverse insulated gate bipolar transistor is easy to generate a strong electric field peak, and the improvement of the breakdown voltage of a device is limited is solved. The folded silicon LIGBT device comprises: a P-type substrate; a gate oxide layer and a field oxide layer; the P-type well region, and a P-type emitter region and an N-type emitter region in the P-type well region; an N-type drift region disposed within the P-type substrate; an N-type buffer layer region and a P-type collector region are formed in the N-type drift region in a doped mode; an emitter electrode disposed above the N-type and P-type emitter regions; a collector disposed above the P-type collector region; a metal gate electrode arranged above the junction of the gate oxide layer and the field oxide layer; an additional electrode disposed over the field oxide layer; the additional electrode is used to apply a forward bias voltage. The invention also provides a manufacturing method of the device.
Description
Technical Field
The invention relates to a transistor device, in particular to a folded silicon LIGBT with an additional electrode and a manufacturing method thereof.
Background
Power Semiconductor devices (Power Semiconductor devices), also known as Power electronic devices, play an important role in Power electronic systems, such as energy control and Power conversion, and are the core of Power electronic conversion. The continuous development and progress of the performance of the power semiconductor device promotes the rapid development of the information-based society and the improvement of the quality of life of people to a certain extent.
The Lateral Insulated Gate Bipolar Transistor (LIGBT) has the advantages of high input impedance and strong Gate control capability of a MOSFET, and also has the advantages of high current density, low on-state voltage drop and strong current handling capability of a BJT, and plays an important role in the field of high-voltage and large-current application. By extending the gate electrode to the surface of the drift region, accumulation of majority carriers is caused, and the forward conduction voltage drop of the device can be greatly reduced, however, the tail end of the extended gate electrode is easy to generate a strong electric field peak, and the improvement of the breakdown voltage of the device is limited.
Disclosure of Invention
The invention aims to solve the technical problems that the tail end of an extended gate electrode in the existing transverse insulated gate bipolar transistor is easy to generate a strong electric field peak and limits the improvement of the breakdown voltage of a device, and provides a folded silicon LIGBT with an additional electrode and a manufacturing method thereof. When the folded silicon LIGBT is conducted, a certain positive voltage is applied to the additional electrode, and the metal gate electrode partially extends on the surface of the N-type drift region, so that a majority carrier accumulation layer is formed on the surface of the N-type drift region, and the conduction characteristic of a device is greatly improved by combining the increase of the effective drift region area and the effective gate width of the device caused by the folded silicon structure.
The technical solution of the invention is as follows:
a folded silicon LIGBT with extra electrodes, characterized in that it comprises: a P-type substrate;
forming a channel which is formed on the upper part of the P-type substrate and extends along the left-right direction and grooves which are positioned on the front side and the rear side of the channel by an etching process;
the gate oxide layer and the field oxide layer are adjacently arranged on the front and rear side walls and the upper surface of the channel and the bottom surface of the channel from left to right;
the P-type well region is arranged on the left side of the upper part of the P-type substrate, and the P-type emitter region and the N-type emitter region are sequentially arranged on the left side of the upper part of the P-type well region from left to right;
the N-type drift region is arranged on the right side of the upper part of the P-type substrate; the N-type drift region comprises a first drift region and a second drift region; wherein the first drift region is located in the channel; the second drift region is located below the first drift region;
the N-type buffer layer region is arranged on the right side of the upper part of the N-type drift region and is formed by doping;
the doped N-type buffer layer region is arranged on the right side of the upper part of the N-type buffer layer region and is doped to form a P-type collector region;
the gate oxide layer is positioned above the P-type trap region, the left side of the gate oxide layer is in contact with the N-type emitter region, the left side of the field oxide layer is in contact with the gate oxide layer, the right side of the field oxide layer is in contact with the N-type buffer layer region, and the thickness of the gate oxide layer is smaller than that of the field oxide layer;
an emitter electrode disposed above a boundary of the N-type emitter region and the P-type emitter region;
a collector disposed over the P-type collector region;
a metal gate electrode arranged above the junction of the gate oxide layer and the field oxide layer;
an additional electrode disposed over the field oxide layer; a first gap is arranged between the additional electrode and the metal gate electrode; a second gap is arranged between the additional electrode and the collector electrode; the extra electrode is used for applying forward bias voltage, and the value range of the forward bias voltage is 10V-100V.
Further, the P-type substrateThe doping concentration of (A) is in the range of 1.0X 1014～1.0×1015cm-3；
The doping concentration of the N-type buffer region is 1.0 multiplied by 1017～5.0×1017cm-3；
The value range of the doping concentration of the P-type well region is 1.0 multiplied by 1016～1.0×1017cm-3；
The doping concentration value of the P type collector region is not less than 1.0 multiplied by 1019cm-3。
Further, a third gap is arranged between the P-type well region and the second drift region.
Further, the height range of the first drift region is 1-6 mu m.
Further, the forward bias voltage range is 10-60V.
Further, the forward bias voltage is 30V.
The method for manufacturing the folded silicon LIGBT with the additional electrode is characterized by comprising the following steps of:
step 1: preparing a P-type silicon material as a P-type substrate;
and 2, step: doping phosphorus ions with certain concentration on a P-type substrate to form an N-type drift region;
and 3, step 3: forming a channel which is formed on the upper part of the P-type substrate and extends along the left-right direction and grooves which are positioned on the front side and the rear side of the channel through an etching process, and dividing the N-type drift region into a first drift region and a second drift region by taking the bottom surface of the groove as a boundary;
and 4, step 4: carrying out phosphorus ion implantation on the surface of the first drift region, and carrying out rapid annealing treatment after the implantation is finished so as to enable the doping concentration of the first drift region to be higher than that of the second drift region;
and 5: forming a lightly doped P-type well region in the left side region of the upper part of the P-type substrate through an ion implantation process, and forming a lightly doped N-type buffer layer region in the right side region of the upper part of the N-type drift region;
and 6: generating field oxide layers of silicon dioxide materials on the front and rear side walls, the upper surface and the bottom surface of the trench through thermal oxidation;
and 7: forming a gate oxide layer which is made of the same material and has a thickness smaller than that of the field oxide layer on the front and rear side walls and the upper surface of the channel and the bottom surface of the channel and is close to the left boundary of the field oxide layer;
and 8: forming a heavily doped N-type emitter region in the P-type well region through phosphorus ion implantation, and performing rapid annealing treatment after the implantation is finished;
and step 9: forming a heavily doped P-type emitter region in the P-type well region and a heavily doped P-type collector region in the N-type buffer region by implanting boron ions, and performing rapid annealing treatment after the implantation;
step 10: etching at the junction position of the heavily doped N-type emitter region and the heavily doped P-type emitter region to form a first electrode contact hole, and depositing a metal material in the first electrode contact hole to form an emitter electrode;
step 11: etching the position of the heavily doped P-type collector region to form a second electrode contact hole, and depositing a metal material in the second electrode contact hole to form a collector;
step 12: depositing a metal material on the upper surfaces of the gate oxide layer and the field oxide layer to form a metal gate electrode, and enabling the metal gate electrode to partially cover the left side of the surface of the N-type drift region;
step 13: and depositing a metal material on the upper surface of the field oxide layer on the right side of the metal gate electrode to form an additional electrode, wherein gaps are reserved between the additional electrode and the metal gate electrode and between the additional electrode and the collector electrode.
The invention has the beneficial effects that:
1. according to the LIGBT structure, a certain positive voltage is added on the extra electrode, the metal gate electrode partially extends on the surface of the N-type drift region, when the LIGBT structure is conducted, a majority carrier accumulation layer can be formed on the surface of the N-type drift region, and the conduction characteristic of the device is greatly improved by combining the increase of the effective drift region area and the effective gate width of the device brought by the folded silicon structure.
2. According to the LIGBT structure, the distribution of an electric field in the drift region is optimized by using the voltage applied to the additional electrode, so that the overall performance of the device is improved.
3. According to the LIGBT structure, when the LIGBT is in a blocking state, the tail end of the metal gate electrode and the tail end of the additional electrode partially covering the right end of the surface of the drift region introduce a new electric field peak on the surface of the drift region, so that the electric field distribution on the surface of the drift region is optimized.
4. A gap is arranged between the P-type well region and the second drift region of the LIGBT structure, and a new electric field peak is introduced at the joint of the P-type substrate and the second drift region during breakdown to optimize the surface electric field distribution of the drift region.
5. According to the LIGBT structure, through a groove etching process, the transverse insulated gate bipolar transistor is provided with two drift regions, the height range of the formed first drift region is 1-6 mu m, a concave-convex folding drift region structure is formed, the effective area of the drift region and the effective area of a grid electrode are increased when a device is conducted through the folding drift region structure, and the forward conduction voltage drop of the device is favorably reduced. In addition, the folded drift region structure enables channel inversion layer electrons below the gate electrode and majority carriers in the drift region to be accumulated along the side wall of the groove, and the forward conduction voltage drop is further reduced.
6. Simulation experiments show that the forward conduction voltage drop of the device is reduced by 35.4% compared with that of a common LIGBT device under the same voltage withstanding level.
7. The method for manufacturing the LIGBT device is simple to operate, and is rapid and efficient.
Drawings
FIG. 1 is a schematic perspective view of an LIGBT device of the present invention;
FIG. 2 is a schematic diagram of the structure of the LIGBT device of the present invention;
FIG. 3 is a schematic structural diagram of a field oxide layer and an N-type drift region on a P-type substrate in the LIGBT device according to the present invention;
fig. 4 is a comparison graph of the turn-on characteristics of the LIGBT device of the present invention and a conventional LIGBT device at the same breakdown voltage level.
Reference numerals are as follows: 1-a first drift region, 2-a second drift region, 3-a P-type well region, 4-an emitter region, 5-a P-type emitter region, 6-an buffer region, 7-a P-type collector region, 8-gate oxide, 9-field oxide, 10-emitter electrode, 11-metal gate electrode, 12-additional electrode, 13-collector, 801-a P-type substrate.
Detailed Description
Taking an N-channel LIGBT as an example, as shown in fig. 1 to 3, the folded silicon LIGBT with additional electrodes provided by the present invention specifically includes:
a P-type substrate 801 of silicon material, wherein the doping concentration of the P-type substrate 801 has a value range of 1.0 × 1014～1.0×1015cm-3(ii) a Doping the upper right side of the P-type substrate 801 to form an N-type drift region; forming concave-convex folded channels extending in the left-right direction on the upper portion of a P-type substrate 801 and grooves located on the front side and the rear side of each channel through a groove etching process, dividing an N-type drift region into an upper portion and a lower portion, wherein a first drift region 1 is a region close to the surface of a device and located in each channel, a second drift region 2 is a region close to the substrate and located below the first drift region 1, the boundary between the first drift region 1 and the second drift region is the bottom surface of each groove, and the second drift region 2 is a region of the N-type drift region, which is etched, except for the first drift region 1; doping is carried out on the surface of the first drift region 1, so that the doping concentration of the first drift region 1 is higher than that of the second drift region 2; the height of the first drift region 1 is in the range of 1-6 μm.
The gate oxide layer 8 and the field oxide layer 9 are adjacently arranged on the front and rear side walls and the upper surface of the channel and the bottom surface of the channel from left to right, and the gate oxide layer 8 and the field oxide layer 9 are made of silicon dioxide materials.
A lightly doped P-type well region 3 disposed at the left side of the upper portion of the P-type substrate 801, and a heavily doped P-type emitter region 5 and a heavily doped N-type emitter region 4 disposed at the left side of the upper portion of the P-type well region 3 in sequence from left to right, wherein the doping concentration of the P-type well region 3 ranges from 1.0 × 1016～1.0×1017cm-3(ii) a A third gap is provided between the P-type well region 3 and the second drift region 2, and in other embodiments, there may be no gap between the P-type well region 3 and the second drift region 2.
The N-type buffer layer region 6 is formed on the right side of the upper part of the N-type drift region by doping, wherein the doping concentration range of the N-type buffer layer region 6 is 1.0 multiplied by 1017～5.0×1017cm-3。
Is arranged at the right side of the upper part of the N-type buffer layer region 6 and is heavily doped to form a P-type collector region 7, and the doping concentration of the P-type collector region 7 is not lower than 1.0 multiplied by 1019cm-3。
Wherein, gate oxide 8 is located 3 tops of P type trap area and the left side contacts with N type emitter region 4, and field oxide 9 left sides and gate oxide 8 contact, and the right side contacts with N type buffer layer region 6, and gate oxide 8's thickness is less than field oxide 9.
And an emitter electrode 10 disposed above a boundary of the N-type emitter region 4 and the P-type emitter region 5.
And a collector 13 disposed above the P-type collector region 7.
And a metal gate electrode 11 disposed over the interface of the gate oxide layer 8 and the field oxide layer 9.
An additional electrode 12 disposed over the field oxide layer 9; a first gap is arranged between the additional electrode 12 and the metal gate electrode 11; a second gap is arranged between the additional electrode 12 and the collector electrode 13; the additional electrode 12 is used for applying a forward bias voltage, and the value range of the forward bias voltage is 10V-100V.
The invention also provides a manufacturing method of the folded silicon LIGBT with the extra electrode, taking the N-channel LIGBT as an example, the folded silicon LIGBT can be prepared through the following steps:
step 1: preparing a P-type silicon material as a P-type substrate 801;
step 2: doping phosphorus ions with a certain concentration on a P-type substrate 801 to form an N-type drift region;
and 3, step 3: concave-convex folded channels which are formed on the upper part of the P-type substrate 801 and extend along the left-right direction and grooves which are positioned on the front side and the rear side of the channels are formed through plasma etching in dry etching, and the N-type drift region is divided into a first drift region 1 and a second drift region 2 by taking the bottom surface of the grooves as a boundary; the first drift region 1 is a region close to the surface of the device, the second drift region 2 is a region close to the substrate, and the second drift region 2 is a region of the N-type drift region except the first drift region 1 after the etching process;
and 4, step 4: phosphorus ion implantation is carried out on the surface of the first drift region 1, and rapid annealing treatment is carried out after the implantation is finished, so that the doping concentration of the first drift region 1 is higher than that of the second drift region 2;
and 5: through an ion implantation process, forming a lightly doped P-type well region 3 in the left side region of the upper part of a P-type substrate 801, and forming a lightly doped N-type buffer layer region 6 in the right side region of the upper part of an N-type drift region;
step 6: generating field oxide layers 9 of silicon dioxide materials on the front and rear side walls and the upper surface of the trench and the bottom surface of the trench through thermal oxidation;
and 7: forming a gate oxide layer 8 which is made of the same material and has a thickness smaller than that of the field oxide layer 9 on the front and rear side walls and the upper surface of the channel and the bottom surface of the channel and is close to the left boundary of the field oxide layer 9;
and 8: forming a heavily doped N-type emitter region 4 in the P-type well region 3 through phosphorus ion implantation, and performing rapid annealing treatment after the implantation is finished;
and step 9: forming a heavily doped P-type emitter region 5 in the P-type well region 3 and a heavily doped P-type collector region 7 in the N-type buffer layer region 6 by implanting boron ions, and performing rapid annealing treatment after the implantation;
step 10: etching the junction position of the heavily doped N-type emitter region 4 and the heavily doped P-type emitter region 5 to form a first electrode contact hole, and depositing a metal material in the first electrode contact hole to form an emitter electrode 10;
step 11: etching the position of the heavily doped P-type collector region 7 to form a second electrode contact hole, and depositing a metal material in the second electrode contact hole to form a collector 13;
step 12: depositing a metal material on the upper surfaces of the gate oxide layer 8 and the field oxide layer 9 to form a metal gate electrode 11, and enabling the metal gate electrode to partially cover the left side of the surface of the N-type drift region;
step 13: and depositing a metal material on the upper surface of the field oxide layer 9 on the right side of the metal gate electrode 11 to form an extra electrode 12, wherein a gap is reserved between the extra electrode 12 and the metal gate electrode 11 and the collector electrode 13.
As shown in fig. 4, according to simulation experiments, when a positive voltage of 30V is applied to the additional electrode 12, under the same withstand voltage level, the forward conduction voltage drop of the LIGBT device of the present invention is 0.93V, the forward conduction voltage drop of the ordinary LIGBT device is 1.44V, and the forward conduction voltage drop of the device of the present invention is reduced by 35.4% compared with the forward conduction voltage drop of the ordinary LIGBT device.
The LIGBT device in the present invention may also be a P-type channel, and its structure is equivalent to that of an N-channel LIGBT device, and in addition, an SOI-based substrate may also be used, which is also considered to belong to the protection scope of the claims of the present application, and is not described herein again.
The materials used in the present invention are mainly silicon semiconductor materials, and should be understood in a broad sense, that is, LIGBT devices formed by semiconductor materials of elements such as germanium, or wide band gap semiconductor materials such as silicon carbide, gallium nitride, etc. are equivalent to LIGBT devices described in the present invention, and should also be considered as belonging to the protection scope of the claims of the present application, and are not described herein again.
Claims (7)
1. A folded silicon LIGBT with extra electrodes, comprising: a P-type substrate (801);
forming a channel which is arranged on the upper part of a P-type substrate (801) and extends along the left-right direction and grooves which are arranged on the front side and the rear side of the channel through an etching process;
the gate oxide layer (8) and the field oxide layer (9) are adjacently arranged on the front and rear side walls and the upper surface of the trench and the bottom surface of the trench from left to right;
the P-type emitter region (5) and the N-type emitter region (4) are sequentially arranged on the left side of the upper part of the P-type well region (3) from left to right;
an N-type drift region arranged on the right side of the upper part of the P-type substrate (801); the N-type drift region comprises a first drift region (1) and a second drift region (2); wherein the first drift region (1) is located in the channel; the second drift region (2) is located below the first drift region (1);
the N-type buffer layer region (6) is arranged on the right side of the upper part of the N-type drift region and is formed by doping;
the doped P-type collector region (7) is arranged on the right side of the upper part of the N-type buffer layer region (6);
the gate oxide layer (8) is positioned above the P-type well region (3), the left side of the gate oxide layer is in contact with the N-type emitter region (4), the left side of the field oxide layer (9) is in contact with the gate oxide layer (8), the right side of the field oxide layer is in contact with the N-type buffer layer region (6), and the thickness of the gate oxide layer (8) is smaller than that of the field oxide layer (9);
an emitter electrode (10) disposed above a boundary of the N-type emitter region (4) and the P-type emitter region (5);
a collector (13) disposed above the P-type collector region (7);
a metal gate electrode (11) arranged above the junction of the gate oxide (8) and the field oxide (9);
an additional electrode (12) disposed above the field oxide layer (9); a first gap is arranged between the additional electrode (12) and the metal gate electrode (11); a second gap is arranged between the additional electrode (12) and the collector electrode (13); the additional electrode (12) is used for applying forward bias voltage, and the value range of the forward bias voltage is 10V-100V.
2. The folded silicon LIGBT with extra electrode as claimed in claim 1, wherein: the doping concentration range of the P-type substrate (801) is 1.0 multiplied by 1014～1.0×1015cm-3；
The doping concentration range of the N-type buffer region (6) is 1.0 multiplied by 1017～5.0×1017cm-3；
The value range of the doping concentration of the P-type well region (3) is 1.0 multiplied by 1016～1.0×1017cm-3；
The doping concentration of the P-type collector region (7) is not lower than 1.0 x 1019cm-3。
3. A folded silicon LIGBT with additional electrodes according to claim 1 or 2, characterized by: and a third gap is arranged between the P-type well region (3) and the second drift region (2).
4. A folded silicon LIGBT with extra electrodes according to claim 3 wherein: the height range of the first drift region (1) is 1-6 mu m.
5. The folded silicon LIGBT with additional electrodes as claimed in claim 4, wherein: the forward bias voltage range is 10-60V.
6. The folded silicon LIGBT with extra electrode in claim 5, wherein: the forward bias voltage is 30V.
7. A method for manufacturing a folded silicon LIGBT with extra electrodes as claimed in claims 1 to 6, comprising the steps of:
step 1: preparing a P-type silicon material as a P-type substrate (801);
step 2: doping phosphorus ions with certain concentration on a P-type substrate (801) to form an N-type drift region;
and step 3: forming a channel which is arranged on the upper part of a P-type substrate (801) and extends along the left-right direction and grooves which are arranged on the front side and the rear side of the channel through an etching process, and dividing an N-type drift region into a first drift region (1) and a second drift region (2) by taking the bottom surface of the groove as a boundary;
and 4, step 4: phosphorus ion implantation is carried out on the surface of the first drift region (1), and rapid annealing treatment is carried out after the implantation is finished, so that the doping concentration of the first drift region (1) is higher than that of the second drift region (2);
and 5: forming a lightly doped P-type well region (3) in the left side region of the upper part of a P-type substrate (801) and forming a lightly doped N-type buffer layer region (6) in the right side region of the upper part of an N-type drift region through an ion implantation process;
step 6: generating field oxide layers (9) of silicon dioxide material on the front and rear side walls and the upper surface of the trench and the bottom surface of the trench by thermal oxidation;
and 7: forming a gate oxide layer (8) which is made of the same material and has a thickness smaller than that of the field oxide layer (9) on the front and rear side walls, the upper surface and the bottom surface of the trench and next to the left boundary of the field oxide layer (9);
and 8: forming a heavily doped N-type emitter region (4) in the P-type well region (3) through phosphorus ion implantation, and performing rapid annealing treatment after the implantation is finished;
and step 9: forming a heavily doped P-type emitter region (5) in the P-type well region (3) and a heavily doped P-type collector region (7) in the N-type buffer layer region (6) by implanting boron ions, and performing rapid annealing treatment after the implantation is finished;
step 10: etching at the boundary position of the heavily doped N-type emitter region (4) and the heavily doped P-type emitter region (5) to form a first electrode contact hole, and depositing a metal material in the first electrode contact hole to form an emitter electrode (10);
step 11: etching at the position of the heavily doped P-type collector region (7) to form a second electrode contact hole, and depositing a metal material in the second electrode contact hole to form a collector (13);
step 12: depositing a metal material on the upper surfaces of the gate oxide layer (8) and the field oxide layer (9) to form a metal gate electrode (11), and enabling part of the metal gate electrode to cover the left side of the surface of the N-type drift region;
step 13: and depositing a metal material on the upper surface of the field oxide layer (9) on the right side of the metal gate electrode (11) to form an extra electrode (12), and reserving a gap between the extra electrode (12) and the metal gate electrode (11) and a collector electrode (13).
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| CN202210353013.1A CN114784101A (en) | 2022-03-31 | 2022-03-31 | Folded silicon LIGBT with additional electrode and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210353013.1A CN114784101A (en) | 2022-03-31 | 2022-03-31 | Folded silicon LIGBT with additional electrode and manufacturing method thereof |
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