CN114783305B - Display panel and display device - Google Patents
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- CN114783305B CN114783305B CN202210447450.XA CN202210447450A CN114783305B CN 114783305 B CN114783305 B CN 114783305B CN 202210447450 A CN202210447450 A CN 202210447450A CN 114783305 B CN114783305 B CN 114783305B
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- 238000002834 transmittance Methods 0.000 claims abstract description 67
- 230000007423 decrease Effects 0.000 claims abstract description 14
- 230000003247 decreasing effect Effects 0.000 claims description 23
- 230000000694 effects Effects 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 14
- 230000008859 change Effects 0.000 description 13
- 230000007704 transition Effects 0.000 description 10
- 230000003139 buffering effect Effects 0.000 description 9
- 239000013078 crystal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000035772 mutation Effects 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
Abstract
The invention discloses a display panel and a display device. The display panel includes: the display device comprises a first display area, a buffer area and a second display area; the light transmittance of the first display area is smaller than that of the second display area; the first display region surrounds the buffer region, the buffer region surrounds the second display region, and for two adjacent buffer regions, one buffer region is surrounded by the other buffer region; the display panel further includes a pixel circuit including at least one transistor; in a direction in which the first display region points to the second display region, transistor densities of m buffer regions among the plurality of buffer regions decrease, and pixel densities of the m buffer regions are unchanged; the pixel density of n buffers of the plurality of buffers is reduced and the transistor density of the n buffers is unchanged, m and n are integers greater than 1, and m and n are each less than the total number of buffers. According to the technical scheme, the second display area is prevented from having obvious dividing lines and saw-tooth display edges during display, and the display effect of the display panel is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the wide application of display devices, the development of the technology of the under-screen camera is faster and faster.
The light transmittance of the existing under-screen camera area is far smaller than that of the normal display area, so that the problems of obvious edge boundary and saw-tooth display edge boundary exist on the display of the under-screen camera area.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for avoiding the existence of obvious display boundaries in an under-screen camera area when the display panel displays.
According to an aspect of the present invention, there is provided a display panel including: the display device comprises a first display area, a buffer area and a second display area; the light transmittance of the first display area is smaller than that of the second display area;
the first display area surrounds the buffer area, the buffer area surrounds the second display area, the number of the buffer areas is a plurality of, and for two adjacent buffer areas, one buffer area is surrounded by the other buffer area; the display panel further comprises a pixel circuit for driving pixels of the first display area, the buffer area and the second display area to emit light, wherein the pixel circuit comprises at least one transistor;
in a direction in which the first display region points to the second display region, transistor densities of m buffer regions among the plurality of buffer regions decrease, and pixel densities of the m buffer regions are unchanged; and the pixel density of n buffer areas in the plurality of buffer areas is reduced, the transistor density of the n buffer areas is unchanged, m and n are integers greater than 1, and m and n are smaller than the total number of the buffer areas.
Optionally, the m buffers include a plurality of adjacent buffers, and/or the n buffers include a plurality of adjacent buffers.
Optionally, at least part of the transistors in the pixel circuits of one of the buffers are located in one or more target regions, the target regions comprising at least one of: the buffer area is arranged at the periphery of the buffer area, the first display area and the non-display area of the display panel.
Optionally, in a direction in which the first display region points to the second display region, the number of transistors in the pixel circuits of at least two of the buffer regions in the target region increases, so that the transistor density of at least two of the buffer regions decreases.
Optionally, the plurality of buffers includes a first buffer and a second buffer surrounding the first buffer, a part of transistors in a pixel circuit of the first buffer is located in the first display region or the non-display region, and another part of transistors is located in the second buffer.
Optionally, the transistor in the pixel circuit of the buffer area located in the target area includes at least one or more of the following: a data writing transistor, a threshold compensating transistor, and a reset transistor.
Optionally, the display panel satisfies at least one of:
the individual pixel circuits of each of the buffers have the same number of transistors;
the number of transistors of the single pixel circuit of the buffer area is the same as the number of transistors of the single pixel circuit of the first display area;
the number of transistors of the single pixel circuit of the buffer region is the same as the number of transistors of the single pixel circuit of the second display region.
Optionally, at least part of transistors in the pixel circuits of the second display area are located in the buffer area;
and/or the number of the groups of groups,
at least part of transistors in the pixel circuits of the second display area are positioned in the non-display area.
Optionally, the pixel density of the second display area is less than or equal to the pixel density of the buffer area adjacent to the second display area.
According to another aspect of the present invention, there is provided a display device including the display panel according to any one of the embodiments of the present invention.
According to the technical scheme, the light transmittance of the first display area is smaller than that of the second display area, and the buffer area is arranged between the first display area and the second display area, so that the transistor density of m buffer areas is decreased in the direction of the first display area pointing to the second display area, and the pixel density of m buffer areas is unchanged; the transistor density of the n buffers is unchanged and the pixel density of the n buffers is decremented. The m buffer areas are, for example, buffer areas close to the first display area, the n buffer areas are buffer areas close to the second display area, the crystal density of the buffer areas is firstly decreased, and the pixel density is then decreased; or, the n buffer areas are, for example, buffer areas close to the first display area, the m buffer areas are buffer areas close to the second display area, and the pixel density of the buffer areas is firstly decreased, and then the transistor density is decreased, so that the alternating change of the transistor density and the pixel density is formed; the light transmittance is gradually increased in the direction that the first display area points to the second display area, the transition and buffering effect of the buffer area can be improved, the transition of the light transmittance is more natural, the light transmittance of the second display area is prevented from being greatly different from that of other display areas, and therefore the second display area caused by the light transmittance mutation can be further prevented from having obvious dividing lines and sawtooth display edges during display, and the display effect of the display panel is further improved. The technical scheme of the embodiment of the invention solves the problem that the light transmittance of the under-screen camera area is far smaller than that of the normal display area, so that obvious edge boundaries and saw-tooth display edge boundaries exist on the display of the under-screen camera area, and improves the display effect of the display panel.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a display panel according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Just as the light transmittance of the existing under-screen camera area mentioned in the background art is far smaller than that of the normal display area, the problem that obvious edge boundaries and saw tooth display edge boundaries exist on the under-screen camera area display is caused, and the applicant finds that the reason for generating the technical problem is that: in order to prevent the photo taking interference, the light transmittance of the under-screen camera area is generally improved at present, so that the interference of a display device to capturing of image light beams by the camera is reduced, the purpose of improving the imaging effect is achieved, but the light transmittance of the under-screen camera area is too low, the light transmittance of the under-screen camera area is larger than that of a normal display area, and the abrupt change of the light transmittance can enable the under-screen camera area to display obvious edge boundaries and saw-tooth display edge boundaries.
In view of the foregoing, an embodiment of the present invention provides a display panel, and fig. 1 is a schematic structural diagram of the display panel provided in the embodiment of the present invention, and referring to fig. 1, the display panel includes: a first display area A, a buffer area B and a second display area C; the light transmittance of the first display area A is smaller than that of the second display area C; the first display area A surrounds the buffer area B, the buffer area B surrounds the second display area C, the number of the buffer areas B is a plurality, and for two adjacent buffer areas B, one buffer area B is surrounded by the other buffer area B; the display panel further comprises a pixel circuit for driving pixels of the first display area A, the buffer area B and the second display area C to emit light, wherein the pixel circuit comprises at least one transistor; in a direction in which the first display area a points to the second display area C, transistor densities of m buffer areas B among the plurality of buffer areas B decrease, and pixel densities of the m buffer areas B do not change; and the pixel density of n buffer areas B among the plurality of buffer areas B is reduced, and the transistor density of n buffer areas B is unchanged, m and n are integers greater than 1, and m and n are both smaller than the total number of buffer areas B.
In one example, the first display area a is, for example, a normal display area, and the second display area C is, for example, an under-screen camera area, where, in order to enhance the imaging effect of the camera, the light transmittance of the second display area C is greater than that of the first display area a. The transistor density of the pixel circuit of the first display area A can be larger than that of the pixel circuit of the buffer area B, and the transistor density of the pixel circuit of the buffer area B can be larger than that of the pixel circuit of the second display area C, so that the light transmittance of the first display area A is smaller than that of the buffer area B, the light transmittance of the buffer area B is smaller than that of the second display area C, the buffer area B can slow down the change of the light transmittance, the light transmittance gradually changes, namely the buffer area B can play a transitional and buffering effect, and the abrupt change of the light transmittance caused by the larger difference of the light transmittance of the second display area C and the light transmittance of the first display area A is avoided, therefore, the second display area C caused by the abrupt change of the light transmittance is prevented from having obvious boundary lines and saw-tooth display edges when being displayed, the display of the display panel is more uniform, and the quality of a display picture is improved. In addition, the pixel density of the first display area A can be set to be greater than that of the buffer area B, and the pixel density of the buffer area B is greater than that of the second display area C, so that the buffer area B further has the effects of transition and buffering, and the problem that the second display area C has an obvious boundary during display is further improved; and the number of pixels of the second display area C is smaller, so that the light transmittance of the second display area C is improved, and the imaging effect of the camera is improved.
The number of the buffer areas B is a plurality, and one buffer area B is surrounded by the other buffer area B in two adjacent buffer areas B; in the direction that the first display area A points to the second display area C, the transistor density of the m buffer areas B is decreased, and the pixel density of the m buffer areas is unchanged, so that the light transmittance of the m buffer areas B is gradually increased; the transistor density of the n buffer areas is unchanged, and the pixel density of the n buffer areas is decreased, so that the light transmittance of the n buffer areas B is gradually increased.
The m buffer areas B are, for example, buffer areas B close to the first display area a, and the n buffer areas B are buffer areas B close to the second display area C, so that the crystal density of the buffer areas B is firstly decreased, and then the pixel density is decreased; or, the n buffers B are, for example, buffers B close to the first display area a, and the m buffers B are buffers B close to the second display area C, so that the pixel densities of the buffers B decrease first and then the transistor densities decrease; the number of the buffer areas B is m+n, for example, the transistor density and the pixel density are successively decreased; the number of the buffer areas B is smaller than m+n, so that the decrease of the transistor density and the pixel density is coincident, and the transistor density and the pixel density form cross decrease; the number of the buffer areas B is greater than m+n, for example, there may be buffer areas B having the same pixel density or buffer areas B having the same transistor density; thereby forming an alternating variation of transistor density and pixel density; the light transmittance is gradually increased in the direction that the first display area A points to the second display area C, the transition and buffering effect of the buffer area B can be improved, the transition of the light transmittance is more natural, the light transmittance of the second display area C is prevented from being larger than that of other display areas, the second display area C caused by the abrupt change of the light transmittance can be further prevented from having obvious dividing lines and sawtooth display edges when being displayed, and the display effect of the display panel is further improved.
It should be noted that, when the number of the buffer areas B is m+n, for example, there may be buffer areas B with constant pixel density and constant transistor density, the transistor density and the pixel density form a cross decrease; similarly, when the number of buffers B is greater than m+n, a cross-taper of transistor density and pixel density may also be formed.
According to the technical scheme, the light transmittance of the first display area is smaller than that of the second display area, and the buffer area is arranged between the first display area and the second display area, so that the transistor density of m buffer areas is decreased in the direction of the first display area pointing to the second display area, and the pixel density of m buffer areas is unchanged; the transistor density of the n buffers is unchanged and the pixel density of the n buffers is decremented. The m buffer areas are, for example, buffer areas close to the first display area, the n buffer areas are buffer areas close to the second display area, the crystal density of the buffer areas is firstly decreased, and the pixel density is then decreased; or, the n buffer areas are, for example, buffer areas close to the first display area, the m buffer areas are buffer areas close to the second display area, and the pixel density of the buffer areas is firstly decreased, and then the transistor density is decreased, so that the alternating change of the transistor density and the pixel density is formed; the light transmittance is gradually increased in the direction that the first display area points to the second display area, the transition and buffering effect of the buffer area can be improved, the transition of the light transmittance is more natural, the light transmittance of the second display area is prevented from being greatly different from that of other display areas, and therefore the second display area caused by the light transmittance mutation can be further prevented from having obvious dividing lines and sawtooth display edges during display, and the display effect of the display panel is further improved. The technical scheme of the embodiment of the invention solves the problem that the light transmittance of the under-screen camera area is far smaller than that of the normal display area, so that obvious edge boundaries and saw-tooth display edge boundaries exist on the display of the under-screen camera area, and improves the display effect of the display panel.
In one embodiment, the number of transistors of the pixel circuits of the first display area is greater than the number of transistors of the pixel circuits of the buffer area, and the number of transistors of the pixel circuits of the buffer area is greater than the number of transistors of the pixel circuits of the second display area, so that the light transmittance of the first display area a is smaller than that of the buffer area, the light transmittance of the buffer area is smaller than that of the second display area, the buffer area can slow down the change of the light transmittance, namely the buffer area can play a role in transition and buffering, and abrupt changes of the light transmittance caused by larger light transmittance differences between the second display area and the first display area are avoided, therefore, the second display area caused by abrupt changes of the light transmittance can be prevented from having obvious boundary lines in display, the display of the display panel can be more uniform, and the quality of a display picture is improved.
On the basis of the above technical solution, optionally, the display panel meets at least one of the following:
the individual pixel circuits of each buffer B have the same number of transistors; the number of transistors of the single pixel circuit of the buffer area B is the same as that of the single pixel circuit of the first display area a; the number of transistors of the single pixel circuit of the buffer B is the same as that of the single pixel circuit of the second display region B.
Specifically, the individual pixel circuits of each buffer B have the same number of transistors, i.e., the number of transistors included in each pixel circuit of each buffer B is the same, and when the transistor density of the buffer B decreases, only the number of transistors located in the buffer B in each pixel circuit of the buffer B decreases.
The number of transistors of the single pixel circuit of the buffer B is the same as the number of transistors of the single pixel circuit of the first display area a, i.e. the number of transistors of each pixel circuit of the buffer B is the same as the number of transistors of each pixel circuit of the first display area a, and when the transistor density of the buffer B is smaller than the transistor density of the first display area a, only the number of transistors in the buffer B per pixel circuit of the buffer B is reduced. The number of transistors of the single pixel circuit of the buffer B is the same as the number of transistors of the single pixel circuit of the second display area B, i.e. the number of transistors of each pixel circuit of the buffer B is the same as the number of transistors of each pixel circuit of the second display area C, and when the transistor density of the second display area C is smaller than the transistor density of the buffer B, only the number of transistors in the second display area C in each pixel circuit of the second display area C is reduced.
Optionally, with continued reference to fig. 1, the m buffers B include adjacent pluralities of buffers B, and/or the n buffers B include adjacent pluralities of buffers B.
Specifically, the m buffer areas B include a plurality of adjacent buffer areas B, in a direction in which the first display area a points to the second display area C, the transistor density of the m buffer areas decreases, and the pixel density of the m buffer areas is unchanged, so that the light transmittance of the m buffer areas B gradually increases; the n buffer areas B include two adjacent buffer areas B, in a direction in which the first display area a points to the second display area C, transistor densities of the n buffer areas are unchanged, and pixel densities of the n buffer areas are decreased, so that light transmittance of the n buffer areas B is gradually increased.
Or the m buffer areas B comprise two adjacent buffer areas B, the transistor density of the m buffer areas B is decreased in a direction that the first display area A points to the second display area C, and the pixel density of the m buffer areas is unchanged, so that the light transmittance of the m buffer areas B is gradually increased; the n buffer areas B include a plurality of adjacent buffer areas B, in a direction in which the first display area a points to the second display area C, transistor densities of the n buffer areas are unchanged, and pixel densities of the n buffer areas are decreased, so that light transmittance of the n buffer areas B is gradually increased.
Or the m buffer areas B comprise a plurality of adjacent buffer areas B, the transistor density of the m buffer areas is reduced in the direction that the first display area A points to the second display area C, and the pixel density of the m buffer areas is unchanged, so that the light transmittance of the m buffer areas B is gradually increased; the n buffer areas B include a plurality of adjacent buffer areas B, in a direction in which the first display area a points to the second display area C, transistor densities of the n buffer areas are unchanged, and pixel densities of the n buffer areas are decreased, so that light transmittance of the n buffer areas B is gradually increased.
Fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention, optionally, referring to fig. 2, at least part of transistors in a pixel circuit of a buffer B are located in one or more target areas, and the target areas include at least one of the following: the buffer area B is arranged at the periphery of the buffer area B, the first display area A and the non-display area E of the display panel.
Specifically, the display panel further includes a non-display area E, and at least part of the transistors in the pixel circuits of the buffer area B are moved to one or more target areas, for example, the buffer area B that can be moved to the periphery of the buffer area B, the first display area a, or the non-display area E; the transistor density in the buffer area B is reduced, the light transmittance of the buffer area B is improved, the buffer area B achieves the transitional and buffering effects, the transition of the light transmittance is more natural, the light transmittance of the second display area C is prevented from being larger than that of other display areas, and therefore the second display area C caused by the abrupt change of the light transmittance can be further prevented from having obvious dividing lines and sawtooth display edges during display, and the display effect of the display panel is further improved.
Alternatively, with continued reference to fig. 2, in a direction in which the first display area a points to the second display area C, the number of transistors in the target area in the pixel circuit of the at least two buffer areas B increases, so that the transistor density of the at least two buffer areas B decreases.
Specifically, the transistors in the pixel circuits of at least two buffer areas B are moved to the target area, and the number of transistors in the pixel circuits of at least two buffer areas B increases in the direction in which the first display area a points to the second display area C, that is, the number of transistors in the pixel circuits of the buffer areas B near the second display area C is greater than the number of transistors in the pixel circuits of the buffer areas B near the first display area a; the transistor density of at least two buffer areas B is reduced, the light transmittance is increased along the direction that the first display area A points to the second display area C, the buffer areas B achieve the transitional and buffering effects, the transitional of the light transmittance is more natural, and therefore the obvious dividing line and saw-tooth display edges of the second display area C caused by the abrupt change of the light transmittance can be further avoided when the second display area C is displayed, and the display effect of the display panel is further improved.
Optionally, fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, referring to fig. 3, the plurality of buffers B includes a first buffer B1 and a second buffer B2 surrounding the first buffer B1, a part of transistors in a pixel circuit of the first buffer B1 are located in the first display area a or the non-display area E, and another part of transistors are located in the second buffer B2.
Specifically, the display panel includes a first buffer B1 and a second buffer B2, the first buffer B1 surrounding the second display region C, the second buffer B2 surrounding the first buffer B1, and the first display region a surrounding the second buffer B2. A part of the transistors in the pixel circuits of the first buffer B1 may be moved to the first display area a or the non-display area E, and another part of the transistors may be moved to the second buffer B2, for example, when the pixel circuits of the first buffer B1 include 7 transistors, two transistors may be moved to the first display area a or the non-display area E, and then the other two transistors may be moved to the second buffer B2, and then the number of transistors in each pixel circuit of the first buffer B1 is 3; each pixel circuit of the second buffer B2 includes 7 transistors, and the first buffer B1 is moved to two transistors of the second buffer B2, so that the transistor density of the first buffer B1 is smaller than the transistor density of the second buffer B2; the transistors in the second buffer area B2 may be moved to the first display area a or the non-display area E, so long as the transistor density in the first buffer area B1 is ensured to be less than the transistor density in the second buffer area B2, so that the transistor density in the two buffer areas B is reduced along the direction of the first display area a pointing to the second display area C, the light transmittance is increased, the buffer area B achieves the transitional and buffering effects, the transition of the light transmittance is more natural, and therefore the obvious boundary and saw-tooth display edges of the second display area C caused by the abrupt change of the light transmittance can be further avoided when the second display area C is displayed, and the display effect of the display panel is further improved.
Optionally, the transistor in the target region in the pixel circuit of the buffer region B includes at least one or more of: a data writing transistor, a threshold compensating transistor, and a reset transistor.
Specifically, the reset transistor includes, for example, a first initialization transistor and a second initialization transistor; fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, as shown in fig. 4, the pixel circuit includes a first light emitting control transistor T1, a driving transistor T2, a second light emitting control transistor T3, a first initialization transistor T4, a threshold compensation transistor T5, a second initialization transistor T6, a data writing transistor T7, a capacitor C1 and a light emitting diode D1, where the first light emitting control transistor T1, the driving transistor T2, the second light emitting control transistor T3 and the light emitting diode D1 form a driving current path.
In moving the transistors in the pixel circuit of the buffer B, for example, at least one of the data writing transistor T7, the first initializing transistor T4, the threshold compensating transistor T5, and the second initializing transistor T6 is moved to the target region first; by preferentially moving the transistors that are not in the drive current path, the distance between the drive current and the light emitting diode D1 can be reduced, reducing the wiring length, and facilitating the reduction of voltage drop loss.
Optionally, with continued reference to fig. 2, at least some of the transistors in the pixel circuits of the second display area C are located in the buffer area B; and/or at least part of transistors in the pixel circuits of the second display area C are located in the non-display area E.
Specifically, part of transistors of the pixel circuits in the second display area C may be moved into the non-display area E, so that the light transmittance of the second display area C is high, which is beneficial for the camera to image. Preferably, the transistor which is not in the driving current path may be preferentially moved into the non-display region E, and the distance from the driving current to the light emitting diode D1 may be reduced, which is advantageous in reducing the voltage drop loss.
Alternatively, part of the transistors of the pixel circuit in the second display region C may be moved into the buffer region B, so that the number of transistors in the second display region C is smaller than that in the buffer region B, so that the light transmittance of the second display region C is higher, and the buffer region B is closer to the second display region C, which may reduce the wiring length, and reduce the voltage drop loss and cost. Preferably, at least one of the data writing transistor, the threshold compensating transistor, and the reset transistor may be preferentially moved into the buffer B, that is, the transistor not in the driving current path may be preferentially moved into the buffer B, and the distance between the driving current and the light emitting diode D1 may be reduced, which is advantageous for reducing voltage drop loss.
Optionally, with continued reference to fig. 2, the pixel density of the second display region C is less than or equal to the pixel density of the buffer region B adjacent to the second display region C.
Specifically, when the transistor density of the second display region C is smaller than the transistor density of the buffer region B adjacent to the second display region C, the pixel density of the second display region C may be equal to the pixel density of the buffer region B adjacent to the second display region C; when the transistor density of the second display area C is equal to the transistor density of the buffer area B adjacent to the second display area C, the pixel density of the second display area C is smaller than the pixel density of the buffer area B adjacent to the second display area C, so as to ensure that the light transmittance of the second display area C is larger than that of the buffer area B, so that the light transmittance gradually increases along the direction of the first display area a toward the second display area C, and the problem of display edge demarcation or saw-tooth of the second display area C caused by abrupt change of the light transmittance can be improved.
Fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 5, the display panel includes four buffers B, namely, a first buffer B1, a second buffer B2, a third buffer B3, and a fourth buffer B4; the first display area a surrounds the fourth buffer area B4, the fourth buffer area B4 surrounds the third buffer area B3, the third buffer area B3 surrounds the second buffer area B2, the second buffer area B2 surrounds the first buffer area B1, and the first buffer area B1 surrounds the second display area C. The pixel circuits of the first display area a, the buffer area B and the second display area C are all the pixel circuits shown in fig. 4.
The arrangement of the transistors and pixels of the first display area a, the four buffer areas B and the second display area C may be as shown in table 1:
TABLE 1 arrangement of transistors and pixels in each region
As can be seen from table 1, the number of transistors in the first display area a in one pixel circuit of the first display area a is 7, and the pixel density of the first display area a is N. The first initializing transistor T4 and the threshold compensating transistor T5 in each pixel circuit of the fourth buffer B4 are moved to the first display area a or the non-display area E, that is, 2 transistors in each pixel circuit of the fourth buffer B4 are not placed in the present area, 5 transistors in one pixel circuit of the fourth buffer B4 are placed in the present area, and the pixel density of the fourth buffer B4 is still N. The first initializing transistor T4, the threshold compensating transistor T5, and the second initializing transistor T6 in each pixel circuit of the third buffer B3 are moved to the first display area a or the non-display area E, and the pixel density of the third buffer B3 is still N; the transistors in each pixel circuit of the second buffer B2 are moved to the first display area A or the non-display area E, and the pixel density of the second buffer B2 is M, wherein M < N; the first initializing transistor T4, the threshold compensating transistor T5, the second initializing transistor T6 and the data writing transistor T7 of the first buffer area B1 are moved to the second buffer area B2, the remaining three transistors are moved to the first display area A or the non-display area E, and the pixel density of the first buffer area B1 is M; moving four transistors (e.g., a first initializing transistor T4, a threshold compensating transistor T5, a second initializing transistor T6, and a data writing transistor T7) of the second display region C to the first buffer region B1, the pixel density of the second display region C being L, L < M; the number of transistors in each pixel circuit of the fourth buffer B4 is 5 and the pixel density is N; the number of transistors in each pixel circuit of the third buffer B3 is 4, and the pixel density is N; the number of transistors in the second buffer B2 is 4, and the pixel density is M; the number of transistors in the first buffer B1 is 4, and the pixel density is M; the number of transistors in the second display area C is 3, and the pixel density is L, so that the light transmittance gradually increases along the direction in which the first display area a points to the second display area C.
Fig. 6 is a schematic structural diagram of still another display panel according to an embodiment of the present invention, and referring to fig. 6, the display panel includes five buffers B, namely, a first buffer B1, a second buffer B2, a third buffer B3, a fourth buffer B4, and a fifth buffer B5; the first display area a surrounds the fifth buffer area B5, the fifth buffer area B5 surrounds the fourth buffer area B4, the fourth buffer area B4 surrounds the third buffer area B3, the third buffer area B3 surrounds the second buffer area B2, the second buffer area B2 surrounds the first buffer area B1, and the first buffer area B1 surrounds the second display area C. The pixel circuits of the first display area a, the buffer area B and the second display area C are all the pixel circuits shown in fig. 4, and the arrangement of the transistors and pixels of the first display area a, the five buffer areas B and the second display area C are shown in table 2:
TABLE 2 arrangement of transistors and pixels in each region
As can be seen from table 2, the number of transistors in the pixel circuit of the first display area a located in the first display area a is 7, and the pixel density of the first display area a is N; two transistors in each pixel circuit of the fifth buffer B5 are moved to the first display area a or the non-display area E, and the pixel density is N; moving three transistors in each pixel circuit of the fourth buffer region B4 to the first display region A or the non-display region E, wherein the pixel density is N; moving four transistors in each pixel circuit of the third buffer region B3 to the first display region A or the non-display region E, wherein the pixel density is N; one transistor in each pixel circuit of the second buffer area B2 is moved to the third buffer area B3, four transistors in each pixel circuit of the second buffer area B2 are moved to the first display area A or the non-display area E, and the pixel density is N; two transistors in each pixel circuit of the first buffer B1 are moved to the second buffer B2, one transistor in each pixel circuit of the first buffer B1 is moved to the first display area A or the non-display area E, and the pixel density isMoving four transistors of the second display region C to the first buffer region B1 with pixel density ofThe number of transistors in each pixel circuit of the fifth buffer B5 is 5, the pixel density is N, and the transistor density is 5; the number of transistors in each pixel circuit of the fourth buffer B4 is 4, the pixel density is N, and the transistor density is 4; the number of transistors in each pixel circuit of the third buffer B3 is 4, the pixel density is N, and the transistor density is 4; crystals in each pixel circuit of the second buffer B2The number of the transistors is 4, the pixel density is N, and the transistor density is 4; the number of transistors in each pixel circuit of the first buffer B1 is 8, and the pixel density is +.>Transistor density is +.>The number of transistors in each pixel circuit of the second display area C is 3, and the pixel density is +.>Transistor density is +.>It is ensured that the light transmittance gradually increases in the direction in which the first display area a points to the second display area C. Note that the transistor density shown in table 2 is a relative density, for example, the pixel density in the first display area a is N, the number of transistors per pixel is 7, and the transistor density is, for example, 7; the fifth buffer area B5 has a pixel density of N, and the number of transistors in each pixel is 5, so that the transistor density is 5 relative to the first display area a; the pixel density of the first buffer B1 is +.>The number of transistors per pixel is 8, the transistor density is +.>
Fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 7, the display device includes a display panel according to any embodiment of the present invention, and the display device may be a mobile phone, a tablet, a display, a smart watch, an MP3, an MP4, or other wearable devices, etc., and therefore, the display device includes the display panel according to any embodiment of the present invention, and therefore, the display device has the same advantages and is not described herein again.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A display panel, comprising: the display device comprises a first display area, a buffer area and a second display area; the light transmittance of the first display area is smaller than that of the second display area; the first display area surrounds the buffer area, the buffer area surrounds the second display area, the number of the buffer areas is a plurality of, and for two adjacent buffer areas, one buffer area is surrounded by the other buffer area; the display panel further comprises a pixel circuit for driving pixels of the first display area, the buffer area and the second display area to emit light, wherein the pixel circuit comprises at least one transistor;
in a direction in which the first display region points to the second display region, transistor densities of m buffer regions among the plurality of buffer regions decrease, and pixel densities of the m buffer regions are unchanged; and the pixel density of n buffer areas in the plurality of buffer areas is reduced, the transistor density of the n buffer areas is unchanged, m and n are integers greater than 1, and m and n are smaller than the total number of the buffer areas;
the m buffer areas are buffer areas close to the first display area, and the n buffer areas are buffer areas close to the second display area, so that the transistor density of the buffer areas is firstly decreased, and the pixel density is then decreased; or, the n buffer areas are buffer areas close to the first display area, and the m buffer areas are buffer areas close to the second display area, so that the pixel density of the buffer areas is firstly decreased, and then the transistor density is decreased.
2. The display panel of claim 1, wherein the m buffers comprise adjacent pluralities of buffers and/or the n buffers comprise adjacent pluralities of buffers.
3. The display panel of claim 1, wherein the display panel comprises,
at least some of the transistors in the pixel circuits of one of the buffers are located in one or more target regions, the target regions comprising at least one of: the buffer area is arranged at the periphery of the buffer area, the first display area and the non-display area of the display panel.
4. The display panel according to claim 3, wherein,
in the direction that the first display area points to the second display area, the number of transistors in the target area in the pixel circuits of at least two buffer areas is increased, so that the transistor density of at least two buffer areas is reduced.
5. The display panel according to claim 3, wherein,
the plurality of buffer areas comprise a first buffer area and a second buffer area surrounding the first buffer area, wherein one part of transistors in a pixel circuit of the first buffer area are positioned in the first display area or the non-display area, and the other part of transistors are positioned in the second buffer area.
6. The display panel according to claim 3, wherein,
the transistor in the pixel circuit of the buffer region, which is located in the target region, at least comprises one or more of the following: a data writing transistor, a threshold compensating transistor, and a reset transistor.
7. The display panel according to any one of claims 1 to 6, wherein the display panel satisfies at least one of:
the individual pixel circuits of each of the buffers have the same number of transistors;
the number of transistors of the single pixel circuit of the buffer area is the same as the number of transistors of the single pixel circuit of the first display area;
the number of transistors of the single pixel circuit of the buffer region is the same as the number of transistors of the single pixel circuit of the second display region.
8. The display panel according to any one of claims 1 to 6, wherein,
at least part of transistors in the pixel circuits of the second display area are positioned in the buffer area;
and/or the number of the groups of groups,
at least part of transistors in the pixel circuits of the second display area are positioned in the non-display area.
9. The display panel according to any one of claims 1 to 6, wherein a pixel density of the second display region is less than or equal to a pixel density of the buffer region adjacent to the second display region.
10. A display device comprising the display panel of any one of claims 1-9.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085766A (en) * | 2019-04-28 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof, display device |
| CN110648622A (en) * | 2019-10-31 | 2020-01-03 | Oppo广东移动通信有限公司 | Display device and electronic apparatus |
| CN110767099A (en) * | 2018-11-07 | 2020-02-07 | 云谷（固安）科技有限公司 | Display panel and display terminal |
| CN111028692A (en) * | 2019-12-26 | 2020-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| WO2020173060A1 (en) * | 2019-02-28 | 2020-09-03 | 云谷（固安）科技有限公司 | Display substrate, display panel and display apparatus |
| CN111627341A (en) * | 2020-06-30 | 2020-09-04 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111724732A (en) * | 2020-06-17 | 2020-09-29 | Oppo广东移动通信有限公司 | Electronic device and control method of display device |
| WO2020259473A1 (en) * | 2019-06-25 | 2020-12-30 | 华为技术有限公司 | Display screen and terminal |
| CN112634809A (en) * | 2020-12-24 | 2021-04-09 | 昆山国显光电有限公司 | Display panel and display device |
| CN113394258A (en) * | 2021-06-07 | 2021-09-14 | 昆山国显光电有限公司 | Display panel and display device |
-
2022
- 2022-04-26 CN CN202210447450.XA patent/CN114783305B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110767099A (en) * | 2018-11-07 | 2020-02-07 | 云谷（固安）科技有限公司 | Display panel and display terminal |
| WO2020173060A1 (en) * | 2019-02-28 | 2020-09-03 | 云谷（固安）科技有限公司 | Display substrate, display panel and display apparatus |
| CN110085766A (en) * | 2019-04-28 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof, display device |
| WO2020259473A1 (en) * | 2019-06-25 | 2020-12-30 | 华为技术有限公司 | Display screen and terminal |
| CN110648622A (en) * | 2019-10-31 | 2020-01-03 | Oppo广东移动通信有限公司 | Display device and electronic apparatus |
| CN111028692A (en) * | 2019-12-26 | 2020-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| CN112562518A (en) * | 2019-12-26 | 2021-03-26 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111724732A (en) * | 2020-06-17 | 2020-09-29 | Oppo广东移动通信有限公司 | Electronic device and control method of display device |
| CN111627341A (en) * | 2020-06-30 | 2020-09-04 | 武汉天马微电子有限公司 | Display panel and display device |
| CN112634809A (en) * | 2020-12-24 | 2021-04-09 | 昆山国显光电有限公司 | Display panel and display device |
| CN113394258A (en) * | 2021-06-07 | 2021-09-14 | 昆山国显光电有限公司 | Display panel and display device |
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|---|---|
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