CN114783305A - Display panel and display device - Google Patents
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Abstract
The invention discloses a display panel and a display device. The display panel includes: the display device comprises a first display area, a buffer area and a second display area; the light transmittance of the first display area is less than that of the second display area; the first display area surrounds the buffer area, the buffer area surrounds the second display area, and for two adjacent buffer areas, one buffer area is surrounded by the other buffer area; the display panel further includes a pixel circuit including at least one transistor; in the direction that the first display area points to the second display area, the transistor density of m buffer areas in the plurality of buffer areas is reduced, and the pixel density of the m buffer areas is unchanged; the pixel density of n buffers of the plurality of buffers is reduced, and the transistor density of the n buffers is unchanged, m and n are integers greater than 1, and m and n are less than the total number of buffers. The technical scheme of the invention avoids the obvious boundary and the sawtooth display edge when the second display area displays, and improves the display effect of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the wide application of display devices, the development of the technology of the camera under the screen is faster and faster.
The light transmittance of the existing camera area under the screen is far smaller than that of a normal display area, so that the problem of obvious edge boundary lines and sawtooth display edge boundary lines exists on the display of the camera area under the screen.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for avoiding an obvious display boundary in an area of a camera under a screen when the display panel displays.
According to an aspect of the present invention, there is provided a display panel including: the display device comprises a first display area, a buffer area and a second display area; the light transmittance of the first display area is smaller than that of the second display area;
the first display area surrounds the buffer area, the buffer area surrounds the second display area, the number of the buffer areas is multiple, and for two adjacent buffer areas, one buffer area is surrounded by the other buffer area; the display panel further comprises a pixel circuit for driving the pixels of the first display area, the buffer area and the second display area to emit light, the pixel circuit comprising at least one transistor;
in the direction in which the first display region points to the second display region, the transistor density of m buffer regions in the plurality of buffer regions is reduced, and the pixel density of the m buffer regions is unchanged; and the pixel density of n of the buffer regions is reduced, and the transistor density of the n buffer regions is unchanged, m and n are integers greater than 1, and m and n are less than the total number of the buffer regions.
Optionally, the m buffers comprise a plurality of adjacent buffers, and/or the n buffers comprise a plurality of adjacent buffers.
Optionally, at least some of the transistors in the pixel circuits of one of the buffer regions are located in one or more target regions, the target regions including at least one of: the display panel comprises a buffer area at the periphery of the buffer area, the first display area and a non-display area of the display panel.
Optionally, in a direction in which the first display area points to the second display area, the number of transistors located in the target area in the pixel circuits of at least two of the buffer areas is increased, so that the transistor density of at least two of the buffer areas is reduced.
Optionally, the plurality of buffer areas include a first buffer area and a second buffer area surrounding the first buffer area, a part of transistors in the pixel circuits of the first buffer area are located in the first display area or the non-display area, and another part of transistors are located in the second buffer area.
Optionally, the transistors in the target area in the pixel circuits of the buffer area at least include one or more of the following: a data writing transistor, a threshold compensation transistor, and a reset transistor.
Optionally, the display panel satisfies at least one of:
the single pixel circuit of each of the buffer regions has the same number of transistors;
the number of transistors of a single pixel circuit of the buffer area is the same as that of the transistors of a single pixel circuit of the first display area;
the number of transistors of a single pixel circuit of the buffer area is the same as the number of transistors of a single pixel circuit of the second display area.
Optionally, at least part of transistors in the pixel circuits of the second display region are located in the buffer region;
and/or the presence of a gas in the gas,
at least part of transistors in the pixel circuits of the second display area are positioned in the non-display area.
Optionally, the pixel density of the second display area is less than or equal to the pixel density of the buffer area adjacent to the second display area.
According to another aspect of the present invention, there is provided a display device including the display panel according to any one of the embodiments of the present invention.
According to the technical scheme of the embodiment of the invention, the light transmittance of the first display area is smaller than that of the second display area, and the transistor density of m buffer areas is decreased in the direction that the first display area points to the second display area by arranging the buffer area between the first display area and the second display area, and the pixel density of the m buffer areas is unchanged; the transistor density of the n buffers is unchanged, and the pixel density of the n buffers is decreased. The m buffer areas are, for example, buffer areas close to the first display area, the n buffer areas are buffer areas close to the second display area, the crystallinity density of the buffer areas is decreased first, and the pixel density is decreased second; or, the n buffer areas are, for example, buffer areas close to the first display area, and the m buffer areas are buffer areas close to the second display area, so that the pixel density of the buffer areas is decreased first, and then the transistor density is decreased, thereby forming the alternate change of the transistor density and the pixel density; the luminousness is gradually increased in the direction of pointing to the second display area in the first display area, the transition and the buffering effect of the buffering area can be improved, the transition of the luminousness is more natural, the luminousness of the second display area is prevented from being greatly different from the luminousness of other display areas, the second display area which is caused by the sudden change of the luminousness can be further prevented from having an obvious boundary and a sawtooth display edge when being displayed, and the display effect of the display panel is further improved. The technical scheme of the embodiment of the invention solves the problem that the light transmittance of the area of the camera under the screen is far smaller than that of the normal display area, so that the area of the camera under the screen has obvious edge boundary lines and sawtooth display edge boundary lines, and improves the display effect of the display panel.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a display panel according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the invention;
FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a display panel according to another embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As mentioned in the background art, the transmittance of the existing under-screen camera area is much smaller than that of the normal display area, which causes the problem of the display of the under-screen camera area having a distinct edge boundary and a jagged display edge boundary, the applicant has found through careful research that the technical problem is caused by: in order not to disturb and take a picture, can improve the regional luminousness of camera under the screen at present usually, and then reduce display device to the interference of camera seizure image light beam, thereby reach the purpose that promotes the formation of image effect, but the regional luminousness of camera under the screen is low excessively, can lead to regional luminousness of camera under the screen to differ great with the luminousness in normal display area, the luminousness change of sudden change can make camera regional under the screen show obvious marginal boundary and sawtooth when showing marginal limit.
In view of the above problem, an embodiment of the present invention provides a display panel, and fig. 1 is a schematic structural diagram of the display panel provided in the embodiment of the present invention, and referring to fig. 1, the display panel includes: a first display area A, a buffer area B and a second display area C; the light transmittance of the first display area A is less than that of the second display area C; the first display area A surrounds the buffer area B, the buffer area B surrounds the second display area C, the number of the buffer areas B is multiple, and for two adjacent buffer areas B, one buffer area B is surrounded by the other buffer area B; the display panel further comprises a pixel circuit for driving the pixels of the first display area A, the buffer area B and the second display area C to emit light, the pixel circuit comprising at least one transistor; in a direction in which the first display area a points to the second display area C, transistor densities of m buffer areas B of the plurality of buffer areas B decrease, and pixel densities of the m buffer areas B do not change; and the pixel density of n buffer regions B in the plurality of buffer regions B is reduced, and the transistor density of the n buffer regions B is unchanged, m and n are integers greater than 1, and m and n are less than the total number of the buffer regions B.
In one example, the first display area a is, for example, a normal display area, and the second display area C is, for example, an area of the camera under the screen, and in order to improve an imaging effect of the camera, a light transmittance of the second display area C is greater than a light transmittance of the first display area a. The transistor density of the pixel circuit of the first display area a may be greater than that of the pixel circuit of the buffer area B, the transistor density of the pixel circuit of the buffer area B may be greater than that of the pixel circuit of the second display area C, so that the light transmittance of the first display area A is less than that of the buffer area B, the light transmittance of the buffer area B is less than that of the second display area C, the buffer area B can slow down the change of the light transmittance to gradually change the light transmittance, namely, the buffer region B can play a role of transition and buffering, and prevent the light transmittance of the second display region C from being greatly different from the light transmittance of the first display region a to cause abrupt change of the light transmittance, and therefore, the second display area C caused by the sudden change of the light transmittance can be prevented from having obvious boundary lines and sawtooth display edges when being displayed, so that the display of the display panel is more uniform, and the quality of a display picture is improved. In addition, the pixel density of the first display area A can be set to be greater than that of the buffer area B, and the pixel density of the buffer area B is greater than that of the second display area C, so that the buffer area B further has the transition and buffering effects, and the problem that the second display area C has an obvious boundary during displaying is further solved; and the number of pixels of the second display area C is small, so that the light transmittance of the second display area C is improved, and the imaging effect of the camera is improved.
The number of the buffer areas B is multiple, and one of the two adjacent buffer areas B is surrounded by the other buffer area B; in the direction that the first display area A points to the second display area C, the transistor density of the m buffer areas B is decreased, and the pixel density of the m buffer areas B is unchanged, so that the light transmittance of the m buffer areas B is gradually increased; the transistor density of the n buffer regions is unchanged, and the pixel density of the n buffer regions is decreased gradually, so that the light transmittance of the n buffer regions B is gradually increased.
The m buffer areas B are, for example, the buffer areas B close to the first display area A, the n buffer areas B are the buffer areas B close to the second display area C, the crystallinity density of the buffer areas B is decreased first, and the pixel density is decreased; or, for example, the n buffer regions B are buffer regions B close to the first display region a, and then the m buffer regions B are buffer regions B close to the second display region C, then the pixel density of the buffer regions B is decreased first, and then the transistor density is decreased; if the number of the buffer areas B is m + n, the density of the transistors and the density of the pixels are decreased successively; if the number of the buffer areas B is less than m + n, the decreasing of the transistor density and the pixel density is overlapped, and the transistor density and the pixel density form a crossed decreasing; if the number of the buffer areas B is greater than m + n, for example, there may be buffer areas B having the same pixel density or buffer areas B having the same transistor density; thereby forming alternating variations in transistor density and pixel density; the light transmittance is gradually increased in the direction that the first display area A points to the second display area C, the transition and the buffering effect of the buffer area B can be improved, the transition of the light transmittance is more natural, the light transmittance of the second display area C is prevented from being different from those of other display areas, the second display area C which is prevented from light transmittance mutation can be further prevented from displaying an obvious boundary and a sawtooth display edge, and the display effect of the display panel is further improved.
It should be noted that, when the number of the buffer areas B is, for example, m + n, there may also be a buffer area B with unchanged pixel density and transistor density, the transistor density and the pixel density are decreased crosswise; similarly, when the number of the buffer areas B is larger than m + n, the crossed decrease of the transistor density and the pixel density can also be formed.
According to the technical scheme of the embodiment of the invention, the light transmittance of the first display area is smaller than that of the second display area, and the transistor density of m buffer areas is decreased in the direction that the first display area points to the second display area by arranging the buffer area between the first display area and the second display area, and the pixel density of the m buffer areas is unchanged; the transistor density of the n buffers is unchanged, and the pixel density of the n buffers is decreased. The m buffer areas are, for example, buffer areas close to the first display area, the n buffer areas are buffer areas close to the second display area, the crystallinity density of the buffer areas is decreased first, and the pixel density is decreased second; or, the n buffer areas are, for example, buffer areas close to the first display area, and the m buffer areas are buffer areas close to the second display area, so that the pixel density of the buffer areas is decreased first, and then the transistor density is decreased, thereby forming the alternate change of the transistor density and the pixel density; the light transmittance is gradually increased in the direction in which the first display area points to the second display area, the transition and the buffering effect of the buffering area can be improved, the transition of the light transmittance is more natural, the light transmittance of the second display area is prevented from being different from those of other display areas, and therefore the second display area caused by the sudden change of the light transmittance can be further prevented from having an obvious boundary and a sawtooth display edge when being displayed, and the display effect of the display panel is further improved. The technical scheme of the embodiment of the invention solves the problem that the light transmittance of the camera area under the screen is far smaller than that of a normal display area, so that an obvious edge boundary and a sawtooth display edge boundary exist on the display of the camera area under the screen, and the display effect of the display panel is improved.
In one embodiment, the number of transistors of the pixel circuit of the first display area is greater than the number of transistors of the pixel circuit of the buffer area, and the number of transistors of the pixel circuit of the buffer area is greater than the number of transistors of the pixel circuit of the second display area, so that the light transmittance of the first display area a is less than the light transmittance of the buffer area, and the light transmittance of the buffer area is less than the light transmittance of the second display area.
On the basis of the above technical solution, optionally, the display panel satisfies at least one of the following:
the single pixel circuit of each buffer B has the same number of transistors; the number of transistors of a single pixel circuit of the buffer area B is the same as that of the transistors of a single pixel circuit of the first display area A; the number of transistors of a single pixel circuit of the buffer area B is the same as that of transistors of a single pixel circuit of the second display area B.
Specifically, the single pixel circuits of the buffer regions B have the same number of transistors, that is, the number of transistors included in each pixel circuit of the buffer regions B is the same, and when the transistor density of the buffer regions B is reduced, only the number of transistors in the buffer regions B in each pixel circuit of the buffer regions B is reduced.
The number of transistors of the single pixel circuit of the buffer B is the same as that of the single pixel circuit of the first display area a, that is, the number of transistors of each pixel circuit of the buffer B is the same as that of each pixel circuit of the first display area a, and when the transistor density of the buffer B is lower than that of the first display area a, only the number of transistors in the buffer B in each pixel circuit of the buffer B is reduced. The number of transistors of the single pixel circuit of the buffer B is the same as that of the single pixel circuit of the second display area B, that is, the number of transistors of each pixel circuit of the buffer B is the same as that of each pixel circuit of the second display area C, and when the transistor density of the second display area C is lower than that of the buffer B, only the number of transistors located in the second display area C in each pixel circuit of the second display area C is reduced.
Optionally, with continued reference to fig. 1, the m buffers B comprise a contiguous plurality of buffers B, and/or the n buffers B comprise a contiguous plurality of buffers B.
Specifically, the m buffer areas B include a plurality of adjacent buffer areas B, in the direction in which the first display area a points to the second display area C, the transistor density of the m buffer areas decreases, and the pixel density of the m buffer areas does not change, so that the light transmittance of the m buffer areas B gradually increases; the n buffer areas B comprise two adjacent buffer areas B, the transistor density of the n buffer areas is unchanged in the direction that the first display area A points to the second display area C, and the pixel density of the n buffer areas is decreased progressively, so that the light transmittance of the n buffer areas B is increased progressively.
Or the m buffer areas B comprise two adjacent buffer areas B, in the direction in which the first display area a points to the second display area C, the transistor density of the m buffer areas B decreases progressively, and the pixel density of the m buffer areas is unchanged, so that the light transmittance of the m buffer areas B increases progressively; the n buffer areas B comprise a plurality of adjacent buffer areas B, the transistor density of the n buffer areas is unchanged in the direction of the first display area A pointing to the second display area C, and the pixel density of the n buffer areas is decreased gradually, so that the light transmittance of the n buffer areas B is gradually increased.
Or the m buffer areas B comprise a plurality of adjacent buffer areas B, in the direction that the first display area a points to the second display area C, the transistor density of the m buffer areas decreases progressively, and the pixel density of the m buffer areas does not change, so that the light transmittance of the m buffer areas B increases progressively; the n buffer areas B comprise a plurality of adjacent buffer areas B, in the direction that the first display area A points to the second display area C, the transistor density of the n buffer areas is unchanged, and the pixel density of the n buffer areas is decreased gradually, so that the light transmittance of the n buffer areas B is increased gradually.
Fig. 2 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and optionally, referring to fig. 2, at least some transistors in the pixel circuits of a buffer B are located in one or more target areas, where the target areas include at least one of the following: a buffer area B at the periphery of the buffer area B, a first display area A and a non-display area E of the display panel.
Specifically, the display panel further includes a non-display area E, and at least a part of transistors in the pixel circuits of the buffer area B are moved to one or more target areas, for example, the transistors can be moved to the buffer area B at the periphery of the buffer area B, the transistors can be moved to the first display area a, and the transistors can be moved to the non-display area E; the transistor density that makes to be located this buffer B reduces, then this buffer B's luminousness improves, buffer B reaches transition and buffering effect, makes the transition of luminousness more natural, avoids second display area C's luminousness and other display area's luminousness to differ greatly, thereby can further avoid the second display area C that the luminousness sudden change leads to obvious boundary and sawtooth display edge when showing, further promotes display panel's display effect.
Alternatively, with continued reference to fig. 2, in a direction in which the first display area a is directed to the second display area C, the number of transistors located at a target area in the pixel circuits of the at least two buffer areas B is increased so that the transistor density of the at least two buffer areas B is reduced.
Specifically, the transistors in the pixel circuits of the at least two buffer areas B are moved to the target area, and in the direction in which the first display area a points to the second display area C, the number of transistors in the target area in the pixel circuits of the at least two buffer areas B is increased, that is, the number of transistors in the target area in the pixel circuits of the buffer area B near the second display area C is greater than the number of transistors in the target area in the pixel circuits of the buffer area B near the first display area a; make along the direction that first display area A points to second display area C, the transistor density of two at least buffers B reduces, and the luminousness increases, and buffers B reaches transition and buffering effect for the transition of luminousness is more natural, thereby can further avoid the second display area C that the luminousness sudden change leads to obvious boundary line and sawtooth display edge when showing, further promotes display panel's display effect.
Optionally, fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 3, the plurality of buffer areas B include a first buffer area B1 and a second buffer area B2 surrounding the first buffer area B1, a part of transistors in the pixel circuit of the first buffer area B1 are located in the first display area a or the non-display area E, and another part of transistors are located in the second buffer area B2.
Specifically, the display panel includes a first buffer area B1 and a second buffer area B2, the first buffer area B1 surrounding the second display area C, the second buffer area B2 surrounding the first buffer area B1, and the first display area a surrounding the second buffer area B2. A part of the transistors in the pixel circuits of the first buffer B1 may be moved to the first display area a or the non-display area E, and another part of the transistors may be moved to the second buffer B2, for example, when the pixel circuits of the first buffer B1 include 7 transistors, two transistors may be moved to the first display area a or the non-display area E, and then the other two transistors may be moved to the second buffer B2, and then the number of transistors in each pixel circuit of the first buffer B1 is 3; each pixel circuit of the second buffer B2 includes 7 transistors, and the first buffer B1 moves to two transistors of the second buffer B2, so that the transistor density of the first buffer B1 is less than that of the second buffer B2; part of transistors of the second buffer area B2 can be moved to the first display area A or the non-display area E, as long as the transistor density of the first buffer area B1 is ensured to be smaller than that of the second buffer area B2, thereby the direction pointing to the second display area C along the first display area A is enabled, the transistor densities of the two buffer areas B are reduced, the light transmittance is increased, the buffer areas B achieve transition and buffer effects, the transition of the light transmittance is enabled to be more natural, thereby the second display area C caused by light transmittance mutation can be further prevented from having obvious boundary lines and sawtooth display edges when displaying, and the display effect of the display panel is further improved.
Optionally, the transistors in the target area in the pixel circuits of the buffer area B at least include one or more of the following: a data writing transistor, a threshold compensation transistor, and a reset transistor.
Specifically, the reset transistor includes, for example, a first initialization transistor and a second initialization transistor; fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and as shown in fig. 4, the pixel circuit includes a first light emitting control transistor T1, a driving transistor T2, a second light emitting control transistor T3, a first initialization transistor T4, a threshold compensation transistor T5, a second initialization transistor T6, a data writing transistor T7, a capacitor C1, and a light emitting diode D1, and the first light emitting control transistor T1, the driving transistor T2, the second light emitting control transistor T3, and the light emitting diode D1 form a driving current path.
When the transistors in the pixel circuit of the buffer region B are moved, for example, at least one of the data write transistor T7, the first initialization transistor T4, the threshold compensation transistor T5, and the second initialization transistor T6 is first moved to a target region; by preferentially moving the transistors which are not in the driving current path, the distance between the driving current and the light emitting diode D1 can be reduced, the wiring length can be reduced, and the reduction of the voltage drop loss is facilitated.
Alternatively, with continued reference to fig. 2, at least a portion of the transistors in the pixel circuits of the second display region C are located in the buffer region B; and/or at least part of the transistors in the pixel circuits of the second display area C are positioned in the non-display area E.
Specifically, a part of transistors of the pixel circuit in the second display area C can be moved into the non-display area E, so that the light transmittance of the second display area C is high, which is beneficial for the camera to image. Preferably, the transistor not in the driving current path may be preferentially moved into the non-display area E, and the distance from the driving current to the light emitting diode D1 may be reduced, which is beneficial to reducing the voltage drop loss.
Or, partial transistors of the pixel circuit in the second display area C may be moved into the buffer area B, so that the number of transistors in the second display area C is smaller than that of transistors in the buffer area B, the light transmittance of the second display area C is higher, and the buffer area B is closer to the second display area C, which may reduce the wiring length and reduce the voltage drop loss and cost. Preferably, at least one of the data writing transistor, the threshold compensation transistor, and the reset transistor may be preferentially moved into the buffer B, that is, a transistor that is not in a driving current path may be preferentially moved into the buffer B, so that a distance from the driving current to the light emitting diode D1 may be reduced, which is advantageous for reducing a voltage drop loss.
Alternatively, with continued reference to fig. 2, the pixel density of the second display region C is less than or equal to the pixel density of the buffer region B adjacent to the second display region C.
Specifically, when the transistor density of the second display region C is less than the transistor density of the buffer region B adjacent to the second display region C, the pixel density of the second display region C may be equal to the pixel density of the buffer region B adjacent to the second display region C; when the transistor density of the second display area C is equal to the transistor density of the buffer area B adjacent to the second display area C, the pixel density of the second display area C is smaller than the pixel density of the buffer area B adjacent to the second display area C, so that the light transmittance of the second display area C is ensured to be greater than that of the buffer area B, and the light transmittance gradually increases along the direction in which the first display area a points to the second display area C, thereby improving the problem of display edge boundary or saw tooth of the second display area C caused by light transmittance mutation.
For example, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 5, the display panel includes four buffer areas B, namely a first buffer area B1, a second buffer area B2, a third buffer area B3, and a fourth buffer area B4; the first display area a surrounds the fourth buffer area B4, the fourth buffer area B4 surrounds the third buffer area B3, the third buffer area B3 surrounds the second buffer area B2, the second buffer area B2 surrounds the first buffer area B1, and the first buffer area B1 surrounds the second display area C. The pixel circuits of the first display area a, the buffer area B and the second display area C are all the pixel circuits shown in fig. 4.
The arrangement of the transistors and pixels of the first display area a, the four buffer areas B, and the second display area C may be as shown in table 1:
TABLE 1 arrangement of transistors and pixels in each region
As can be seen from table 1, the number of transistors in one pixel circuit of the first display area a in the first display area a is 7, and the pixel density of the first display area a is N. The first initialization transistor T4 and the threshold compensation transistor T5 in each pixel circuit of the fourth buffer B4 move to the first display area a or the non-display area E, that is, 2 transistors in each pixel circuit of the fourth buffer B4 are not placed in this region, 5 transistors in one pixel circuit of the fourth buffer B4 are located in this region, and the pixel density of the fourth buffer B4 is still N. The first initialization transistor T4, the threshold compensation transistor T5, and the second initialization transistor T6 in each pixel circuit of the third buffer B3 move to the first display area a or the non-display area E, and the pixel density of the third buffer B3 is still N; the transistors in each pixel circuit of the second buffer B2 are moved to the first display area a or the non-display area E, the pixel density of the second buffer B2 is M, M < N; the first initialization transistor T4, the threshold compensation transistor T5, the second initialization transistor T6 and the data write transistor T7 of the first buffer B1 are moved to the second buffer B2, the remaining three transistors are moved to the first display area a or the non-display area E, and the pixel density of the first buffer B1 is M; four transistors (e.g., the first initialization transistor T4, the threshold compensation transistor T5, the second initialization transistor T6, and the data write transistor T7) of the second display region C are moved to the first buffer region B1, the pixel density of the second display region C is L, and L < M; the number of transistors in each pixel circuit of the fourth buffer B4 is 5 and the pixel density is N; the number of transistors in each pixel circuit of the third buffer B3 is 4, and the pixel density is N; the number of transistors of the second buffer B2 is 4, and the pixel density is M; the number of transistors of the first buffer B1 is 4, and the pixel density is M; the number of transistors in the second display area C is 3, and the pixel density is L, so that the light transmittance is ensured to be gradually increased along the direction in which the first display area a points to the second display area C.
For example, fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 6, the display panel includes five buffer areas B, namely, a first buffer area B1, a second buffer area B2, a third buffer area B3, a fourth buffer area B4, and a fifth buffer area B5; the first display area a surrounds the fifth buffer area B5, the fifth buffer area B5 surrounds the fourth buffer area B4, the fourth buffer area B4 surrounds the third buffer area B3, the third buffer area B3 surrounds the second buffer area B2, the second buffer area B2 surrounds the first buffer area B1, and the first buffer area B1 surrounds the second display area C. The pixel circuits of the first display area a, the buffer area B and the second display area C are all the pixel circuits shown in fig. 4, and the arrangement of the transistors and the pixels of the first display area a, the five buffer areas B and the second display area C is shown in table 2:
TABLE 2 arrangement of transistors and pixels in each region
As can be seen from table 2, the number of transistors in the pixel circuit of the first display area a located in the first display area a is 7, and the pixel density of the first display area a is N; two transistors in each pixel circuit of the fifth buffer B5 move to the first display area a or the non-display area E with a pixel density of N; moving three transistors in each pixel circuit of the fourth buffer B4 to the first display area a or the non-display area E with a pixel density of N; moving four transistors in each pixel circuit of the third buffer B3 to the first display area a or the non-display area E with a pixel density of N; moving one transistor in each pixel circuit of the second buffer B2 to the third buffer B3, moving four transistors in each pixel circuit of the second buffer B2 to the first display area a or the non-display area E, with a pixel density of N; two transistors in each pixel circuit of the first buffer B1 are moved to the second buffer B2, and one transistor in each pixel circuit of the first buffer B1 is moved to the first displayDisplay area A or non-display area E with pixel density of
The four transistors of the second display region C are moved to the first buffer region B1 with the pixel density of
The number of transistors in each pixel circuit of the fifth buffer B5 is 5, the pixel density is N, and the transistor density is 5; the number of transistors in each pixel circuit of the fourth buffer B4 is 4, the pixel density is N, and the transistor density is 4; the number of transistors in each pixel circuit of the third buffer B3 is 4, the pixel density is N, and the transistor density is 4; the number of transistors in each pixel circuit of the second buffer B2 is 4, the pixel density is N, and the transistor density is 4; the number of transistors in each pixel circuit of the first buffer B1 was 8, and the pixel density was
Transistor density of
The number of transistors in each pixel circuit of the second display region C is 3, and the pixel density is
Transistor density of
It is possible to ensure that the light transmittance gradually increases in a direction in which the first display area a is directed toward the second display area C. Note that the transistor density shown in table 2 is relative density, for example, the pixel density in the first display area a is N, the number of transistors per pixel is 7, and the transistor density is, for example, 7; the pixel density in the fifth buffer area B5 is N, the transistor number of each pixel is 5, and the transistor density is 5 relative to the first display area a; the first buffer B1 has a pixel density of
The transistor density is 8 for each pixel
Fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 7, the display device includes a display panel according to any embodiment of the present invention, and the display device may be a mobile phone, a tablet, a display, a smart watch, an MP3, an MP4, or other wearable devices.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A display panel, comprising: the display device comprises a first display area, a buffer area and a second display area; the light transmittance of the first display area is smaller than that of the second display area; the first display area surrounds the buffer area, the buffer area surrounds the second display area, the number of the buffer areas is multiple, and for two adjacent buffer areas, one buffer area is surrounded by the other buffer area; the display panel further comprises a pixel circuit for driving the pixels of the first display area, the buffer area and the second display area to emit light, the pixel circuit comprising at least one transistor;
in the direction in which the first display area points to the second display area, the transistor density of m buffer areas in the plurality of buffer areas is reduced, and the pixel density of the m buffer areas is unchanged; and the pixel density of n of the plurality of buffers is reduced, and the transistor density of the n buffers is unchanged, m and n are integers greater than 1, and m and n are less than the total number of the buffers.
2. The display panel according to claim 1, wherein the m buffers comprise adjacent buffers, and/or wherein the n buffers comprise adjacent buffers.
3. The display panel according to claim 1,
at least some of the transistors in the pixel circuits of the buffer region are located in one or more target regions, the target regions including at least one of: the display panel comprises a buffer area at the periphery of the buffer area, the first display area and a non-display area of the display panel.
4. The display panel according to claim 3,
in the direction that the first display area points to the second display area, the number of transistors located in the target area in the pixel circuits of at least two buffer areas is increased, so that the transistor density of at least two buffer areas is reduced.
5. The display panel according to claim 3,
the plurality of buffer areas comprise a first buffer area and a second buffer area surrounding the first buffer area, a part of transistors in pixel circuits of the first buffer area are positioned in the first display area or the non-display area, and the other part of transistors are positioned in the second buffer area.
6. The display panel according to claim 3,
the transistors in the target area in the pixel circuits of the buffer area at least comprise one or more of the following items: a data writing transistor, a threshold compensation transistor, and a reset transistor.
7. The display panel according to any one of claims 1 to 6, wherein the display panel satisfies at least one of:
the single pixel circuit of each of the buffer regions has the same number of transistors;
the number of transistors of a single pixel circuit of the buffer area is the same as that of transistors of a single pixel circuit of the first display area;
the number of transistors of a single pixel circuit of the buffer area is the same as the number of transistors of a single pixel circuit of the second display area.
8. The display panel according to any one of claims 1 to 6,
at least part of transistors in the pixel circuits of the second display area are positioned in the buffer area;
and/or the presence of a gas in the gas,
at least part of transistors in the pixel circuits of the second display area are positioned in the non-display area.
9. The display panel according to any one of claims 1 to 6, wherein a pixel density of the second display region is less than or equal to a pixel density of the buffer region adjacent to the second display region.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085766A (en) * | 2019-04-28 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof, display device |
| CN110648622A (en) * | 2019-10-31 | 2020-01-03 | Oppo广东移动通信有限公司 | Display device and electronic apparatus |
| CN110767099A (en) * | 2018-11-07 | 2020-02-07 | 云谷（固安）科技有限公司 | Display panel and display terminal |
| CN111028692A (en) * | 2019-12-26 | 2020-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| WO2020173060A1 (en) * | 2019-02-28 | 2020-09-03 | 云谷（固安）科技有限公司 | Display substrate, display panel and display apparatus |
| CN111627341A (en) * | 2020-06-30 | 2020-09-04 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111724732A (en) * | 2020-06-17 | 2020-09-29 | Oppo广东移动通信有限公司 | Electronic device and control method of display device |
| WO2020259473A1 (en) * | 2019-06-25 | 2020-12-30 | 华为技术有限公司 | Display screen and terminal |
| CN112634809A (en) * | 2020-12-24 | 2021-04-09 | 昆山国显光电有限公司 | Display panel and display device |
| CN113394258A (en) * | 2021-06-07 | 2021-09-14 | 昆山国显光电有限公司 | Display panel and display device |
-
2022
- 2022-04-26 CN CN202210447450.XA patent/CN114783305B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110767099A (en) * | 2018-11-07 | 2020-02-07 | 云谷（固安）科技有限公司 | Display panel and display terminal |
| WO2020173060A1 (en) * | 2019-02-28 | 2020-09-03 | 云谷（固安）科技有限公司 | Display substrate, display panel and display apparatus |
| CN110085766A (en) * | 2019-04-28 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof, display device |
| WO2020259473A1 (en) * | 2019-06-25 | 2020-12-30 | 华为技术有限公司 | Display screen and terminal |
| CN110648622A (en) * | 2019-10-31 | 2020-01-03 | Oppo广东移动通信有限公司 | Display device and electronic apparatus |
| CN111028692A (en) * | 2019-12-26 | 2020-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| CN112562518A (en) * | 2019-12-26 | 2021-03-26 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111724732A (en) * | 2020-06-17 | 2020-09-29 | Oppo广东移动通信有限公司 | Electronic device and control method of display device |
| CN111627341A (en) * | 2020-06-30 | 2020-09-04 | 武汉天马微电子有限公司 | Display panel and display device |
| CN112634809A (en) * | 2020-12-24 | 2021-04-09 | 昆山国显光电有限公司 | Display panel and display device |
| CN113394258A (en) * | 2021-06-07 | 2021-09-14 | 昆山国显光电有限公司 | Display panel and display device |
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|---|---|
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