CN114779569A - Photoetching plate and application and chip thereof - Google Patents
Photoetching plate and application and chip thereof Download PDFInfo
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- CN114779569A CN114779569A CN202210240914.XA CN202210240914A CN114779569A CN 114779569 A CN114779569 A CN 114779569A CN 202210240914 A CN202210240914 A CN 202210240914A CN 114779569 A CN114779569 A CN 114779569A
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- Prior art keywords
- daughter board
- light transmission
- chip
- plate
- transmission region
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- 238000001259 photo etching Methods 0.000 title claims abstract description 26
- 230000003647 oxidation Effects 0.000 claims abstract description 27
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 27
- 238000002360 preparation method Methods 0.000 claims abstract description 8
- 230000005540 biological transmission Effects 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 19
- 238000000206 photolithography Methods 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 239000012788 optical film Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 238000004528 spin coating Methods 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- 238000003491 array Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention relates to the technical field of chip manufacturing, in particular to a photoetching plate and application and a chip thereof. According to the photoetching plate, by designing the layout of the photoetching plate, a regular circular oxidation pattern can be obtained on the premise of not influencing photoelectric performance and the original design size of a chip, and the performance of the chip obtained by subsequent preparation is ensured to a certain extent.
Description
Technical Field
The invention relates to the technical field of chip manufacturing, in particular to a photoetching plate and application thereof as well as a chip.
Background
A VCSEL (vertical cavity surface emitting laser) generally includes a P-DBR, an oxide layer, a quantum well, and an N-DBR, wherein in a VCSEL manufacturing process, the oxide layer needs to be oxidized to form an oxidized via, so as to achieve a purpose of limiting an optical signal, and a shape of the oxidized via affects a chip performance, and if the oxidized via is irregular, a divergence angle of a far field is affected, so as to affect a device performance.
At present, the oxidation process of VCSEL mostly etches the epitaxial structure to the N-DBR, from bottom to top, the N-DBR, the active layer, the oxide layer, and the P-DBR are exposed in sequence, and then the oxide layer is oxidized to regular patterns by the oxidation process, but most of the photolithography boards used in etching in the prior art are circular structures arranged regularly in multiple groups, as shown in fig. 1, the positions of the chip light emitting holes (oxidized holes) corresponding to the circular regions, and the remaining white regions are the positions of the chips that need to be etched to form trenches, after photolithography and etching are performed on the chips by using the photolithography boards with such structures, when oxidation is performed, the adjacent circular regions use common oxidized trenches, that is, after water vapor enters from the trenches during oxidation, the water vapor can diffuse to the adjacent light emitting holes, and then oxidize, because the uniformity of the diffusion of the water vapor to the periphery is uncontrollable, therefore, differential oxidation is caused, so that the oxidized shape obtained by oxidation is irregular, and the performance of a chip obtained by subsequent preparation is affected.
Disclosure of Invention
In view of this, the present invention provides a photolithography mask, and an application and a chip thereof, in which a layout of the photolithography mask is designed, so that a regular circular oxidation pattern can be obtained on the premise of not affecting photoelectric performance and an original chip design size, and performance of a chip obtained by subsequent preparation is ensured to a certain extent.
The invention solves the technical problems by the following technical means:
the utility model provides a photoetching plate, includes first daughter board, second daughter board and third daughter board, all be provided with the photoetching territory that a plurality of arrays were arranged on first daughter board, second daughter board and the third daughter board, the photoetching territory includes a plurality of mutually independent light transmission area territories, and is a plurality of light transmission area territory align to grid is on same circumference, figure on the regional photoetching board of first piece light transmission and the figure size on the regional photoetching board of second piece light transmission are the same, and crisscross the setting, the position of figure on the regional photoetching board of third piece light transmission and the figure on the regional photoetching board of first piece light transmission is corresponding, and the figure on the regional photoetching board of third piece light transmission is less than the size of the figure on the regional photoetching board of first piece light transmission.
Further, one of the lithographic layouts includes 4-10 light-transmitting regions.
Further, the shape of the light-transmitting area is a sector.
The fan-shaped structure of the light-transmitting area enables the shape of the etched groove to be fan-shaped, the fan-shaped structure of the groove has certain inductivity on water vapor generated in oxidation, the water vapor can be diffused inwards in a fan shape to be oxidized, and therefore the regularity of oxidized holes obtained through oxidation can be guaranteed to a certain extent.
In addition, the invention also discloses application of the photoetching plate in a VCSEL chip.
Further, the photoetching plate is used for the oxidation etching process of the VCSEL chip.
Further, the application method of the photolithography plate specifically comprises the following steps:
s1: taking a full-structure epitaxial wafer, spin-coating a layer of photoresist on the epitaxial wafer, then using a first sub-plate for exposure, plating a metal material after development to obtain a P-ohmic contact discontinuous metal ring, and removing the photoresist;
s2: spin-coating photoresist on the surface of the epitaxial wafer obtained in the step S1, exposing by using a second sub-plate, and after developing, etching downwards to form a step until an N-DBR layer is formed by dry etching to expose an oxide layer;
s3: oxidizing the oxide layer by using a wet oxidation process to form an oxidized hole and define a light emitting area;
s4: after the oxidation is finished, depositing an optical film on the surface of the epitaxial wafer obtained in the step S3;
s5: spin-coating photoresist on the surface of the optical film, exposing by using a third sub-plate, and etching the optical film by using dry etching after developing to obtain a longitudinal channel; then carrying out subsequent conventional preparation procedures.
Further, the metal material in the steps S1 and S5 is one or more of titanium, chromium, tungsten, gold, platinum and antimony.
Furthermore, the epitaxial wafer with the full structure sequentially comprises a single crystal substrate, an N-DBR, a quantum well active layer, an oxidation layer and a P-DBR.
Furthermore, the invention also discloses a VCSEL chip prepared by using the photoetching plate.
The invention has the beneficial effects that:
(1) according to the photoetching plate, the layout of the photoetching plate is designed, and during oxidation, each oxidation hole is oxidized by using a single Trench, so that the problem of differential oxidation caused by the fact that the traditional photoetching plate uses the Trench commonly is solved, the shape of the oxidation hole is ensured to a certain extent, the divergence angle of a VCSEL is further improved, and the performance of a chip is ensured.
(2) The photoetching plate is applied to the oxidation process of the VCSEL chip, and the oxidation shape can be improved on the premise of not influencing the photoelectric performance and the original design size of the chip.
Drawings
FIG. 1 is a prior art reticle;
FIG. 2 is a schematic diagram of a first daughter board of the present invention;
FIG. 3 is a schematic diagram of a second daughter board of the present invention;
FIG. 4 is a schematic diagram of a third daughter board of the present invention;
FIG. 5 is a schematic view (partial) of a wafer structure obtained in step S1 according to the embodiment of the present invention;
FIG. 6 is a schematic view of the wafer structure obtained in step S2 according to the embodiment of the present invention;
FIG. 7 is a sectional view taken along the line A-A in FIG. 6;
FIG. 8 is a schematic diagram of a wafer structure obtained in step S5 of this embodiment of the present invention (for clarity, the optical film on the surface of the P-DBR is not labeled);
FIG. 9 is a cross-sectional view taken in the direction B-B of FIG. 8;
FIG. 10 is an infrared microscope image of oxidized pores obtained after oxidation using a conventional reticle;
FIG. 11 is an infrared microscope photograph of oxidized wells obtained after oxidation using a reticle of the present invention;
the structure comprises a first sub-board 1, a second sub-board 2, a third sub-board 3, a light-transmitting region 4, a substrate 5, an N-DBR6, a quantum well active layer 7, an oxide layer 8, a P-DBR9, a P-ohmic contact metal ring 10, a step 11, an optical film 12 and a channel 13.
Detailed Description
The present invention will be described in detail with reference to specific examples below:
examples
As shown in fig. 2 to 4, a photolithography mask of the present invention includes a first sub-board 1, a second sub-board 2, and a third sub-board 3, where the first sub-board 1, the second sub-board 2, and the third sub-board 3 are all provided with a plurality of photolithography layouts arranged in a rectangular array, each photolithography layout includes a plurality of light transmission regions 4 independent from each other, the plurality of light transmission regions 4 are uniformly arranged on the same circumference, a specific photolithography layout includes 4 to 10 light transmission regions 4, the light transmission regions 4 are fan-shaped, the light transmission regions on the first sub-board 1 and the light transmission regions 4 on the second sub-board 2 are the same in size and are arranged in a staggered manner, the light transmission regions on the third sub-board 3 correspond to the light transmission regions on the first sub-board 1, and the light transmission regions on the third sub-board 3 are smaller in size than the light transmission regions on the first sub-board 1.
Specifically, the method for applying the photolithography mask in the oxidation process of VCSEL chip preparation comprises the following steps:
s1: taking a full-structure epitaxial wafer, wherein the full-structure epitaxial wafer sequentially comprises a single crystal substrate 5, an N-DBR6, a quantum well active layer 7, an oxidation layer 8, a P-DBR9 and the like, the single crystal substrate of the embodiment is a gallium arsenide substrate, the gallium arsenide substrate is cleaned and dried, a layer of photoresist is coated on the epitaxial wafer in a spin mode by the prior art, then a first sub-board 1 is used for exposure, after development, one or more metal materials of titanium, chromium, tungsten, gold, platinum and antimony are plated to obtain a P-ohmic contact metal ring 10, and the photoresist is removed, as shown in figure 5;
s2: spin-coating a photoresist on the surface of the epitaxial wafer obtained in the step S1, exposing the epitaxial wafer by using the second sub-board 2, and after developing, etching down to the N-DBR6 layer by dry etching to form a step 11 and expose the oxide layer 8, as shown in fig. 6-7;
s3: oxidizing the oxide layer 8 by using a wet oxidation process to form an oxidation hole and define a light emitting area;
s4: after the oxidation is finished, depositing an optical film 12 on the surface of the epitaxial wafer obtained in the step S3;
s5: spin-coating photoresist on the surface of the optical film 12, exposing by using the third sub-plate 3, and after developing, etching the optical film 12 by using dry etching to obtain a longitudinal channel 13, as shown in fig. 8 and 9;
s6: the VCSEL chip is obtained by plating one or more metal materials of titanium, chromium, tungsten, gold, platinum and antimony in the channel 13 by using a metal sputtering process to form metal interconnection of a p surface, and then performing subsequent conventional preparation procedures including M2 photoetching, electroplating, grinding, back ohmic contact gold plating, testing and the like.
As can be seen from a comparison of fig. 10 and 11, the oxidized pores obtained by oxidation using the reticle of the present invention are more regular and rounded in shape.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.
Claims (9)
1. The utility model provides a photoetching plate, its characterized in that, includes first daughter board, second daughter board and third daughter board, all be provided with the photoetching territory that a plurality of arrays were arranged on first daughter board, second daughter board and the third daughter board, the photoetching territory includes a plurality of mutually independent light transmission regions, and is a plurality of light transmission region align to grid is on same circumference, light transmission region on the first daughter board is the same with the size of the light transmission region on the second daughter board, and sets up in a staggered way, the position of light transmission region on the third daughter board and the light transmission region on the first daughter board is corresponding, and the size of the light transmission region on the third daughter board is less than the size of light transmission region on the first daughter board.
2. A reticle according to claim 1, wherein one of the lithographic layouts comprises 4-10 light transmitting areas.
3. A reticle according to claim 2, wherein the light transmitting areas are fan shaped.
4. Use of a reticle according to any one of claims 1-3 in a VCSEL chip.
5. Use of the photolithography plate according to claim 4 in VCSEL chips, wherein the photolithography plate is used in an oxide etching process for VCSEL chips.
6. The use of the photolithography plate according to claim 5 in a VCSEL chip, wherein the method of using the photolithography plate is specifically:
s1: taking a full-structure epitaxial wafer, spin-coating a layer of photoresist on the epitaxial wafer, then using a first sub-plate for exposure, plating a metal material after development to obtain a P-ohmic contact metal ring, and removing the photoresist;
s2: spin-coating photoresist on the surface of the epitaxial wafer obtained in the step S1, exposing by using a second sub-plate, and etching downwards to form a step until the N-DBR layer is formed by dry etching after developing to expose the oxide layer;
s3: oxidizing the oxide layer by using a wet oxidation process to form an oxidized hole and define a light emitting area;
s4: after the oxidation is finished, depositing an optical film on the surface of the epitaxial wafer obtained in the step S3;
s5: spin-coating photoresist on the surface of the optical film, exposing by using a third sub-plate, and etching the optical film by using dry etching after developing to obtain a longitudinal channel;
s6: and plating a metal material in the electrode tank by utilizing a metal sputtering process to form metal interconnection of a p surface, and then carrying out subsequent conventional preparation procedures.
7. The use of the photolithography plate of claim 6 in VCSEL chips, wherein the metal material in the steps S1 and S6 is at least one of titanium, chromium, tungsten, gold, platinum and antimony.
8. Use of a reticle in a VCSEL chip according to claim 7, wherein said fully structured epitaxial wafer comprises in order a single crystal substrate, an N-DBR, a quantum well active layer, an oxide layer, a P-DBR.
9. A chip, characterized in that the photolithography plate according to any one of claims 1 to 3 is used in the preparation of said chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210240914.XA CN114779569A (en) | 2022-03-10 | 2022-03-10 | Photoetching plate and application and chip thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210240914.XA CN114779569A (en) | 2022-03-10 | 2022-03-10 | Photoetching plate and application and chip thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114779569A true CN114779569A (en) | 2022-07-22 |
Family
ID=82423214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210240914.XA Pending CN114779569A (en) | 2022-03-10 | 2022-03-10 | Photoetching plate and application and chip thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114779569A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN107132726A (en) * | 2016-02-29 | 2017-09-05 | 上海微电子装备（集团）股份有限公司 | A kind of graphic structure and exposure method of sapphire pattern substrate mask plate |
| CN207636924U (en) * | 2017-05-10 | 2018-07-20 | 天津三安光电有限公司 | It is a kind of to be easy to light shield version of the protection using area |
| CN108598866A (en) * | 2018-05-21 | 2018-09-28 | 湖北光安伦科技有限公司 | A kind of VCSEL chip array structures and preparation method thereof |
| CN111682401A (en) * | 2020-08-14 | 2020-09-18 | 江西铭德半导体科技有限公司 | VCSEL chip and manufacturing method thereof |
| CN112626472A (en) * | 2020-10-26 | 2021-04-09 | 威科赛乐微电子股份有限公司 | Preparation method of VCSEL array chip P-surface connecting metal |
| CN112864798A (en) * | 2021-01-26 | 2021-05-28 | 威科赛乐微电子股份有限公司 | Preparation method of VCSEL chip metal film electrode |
| CN113659434A (en) * | 2021-06-24 | 2021-11-16 | 威科赛乐微电子股份有限公司 | Method for manufacturing VCSEL chip without Mesa |
-
2022
- 2022-03-10 CN CN202210240914.XA patent/CN114779569A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412462A (en) * | 2013-07-26 | 2013-11-27 | 北京京东方光电科技有限公司 | Mask plate and liquid crystal panel |
| CN103576440A (en) * | 2013-10-11 | 2014-02-12 | 西安神光安瑞光电科技有限公司 | Quincuncial mask plate and method for making patterned substrate by utilizing same |
| CN107132726A (en) * | 2016-02-29 | 2017-09-05 | 上海微电子装备（集团）股份有限公司 | A kind of graphic structure and exposure method of sapphire pattern substrate mask plate |
| CN207636924U (en) * | 2017-05-10 | 2018-07-20 | 天津三安光电有限公司 | It is a kind of to be easy to light shield version of the protection using area |
| CN108598866A (en) * | 2018-05-21 | 2018-09-28 | 湖北光安伦科技有限公司 | A kind of VCSEL chip array structures and preparation method thereof |
| CN111682401A (en) * | 2020-08-14 | 2020-09-18 | 江西铭德半导体科技有限公司 | VCSEL chip and manufacturing method thereof |
| CN112626472A (en) * | 2020-10-26 | 2021-04-09 | 威科赛乐微电子股份有限公司 | Preparation method of VCSEL array chip P-surface connecting metal |
| CN112864798A (en) * | 2021-01-26 | 2021-05-28 | 威科赛乐微电子股份有限公司 | Preparation method of VCSEL chip metal film electrode |
| CN113659434A (en) * | 2021-06-24 | 2021-11-16 | 威科赛乐微电子股份有限公司 | Method for manufacturing VCSEL chip without Mesa |
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