CN114779546A - Array substrate, preparation method thereof, liquid crystal display panel and display device - Google Patents
Array substrate, preparation method thereof, liquid crystal display panel and display device Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 194
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 239000010408 film Substances 0.000 claims abstract description 114
- 239000010409 thin film Substances 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 78
- 230000008569 process Effects 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 8
- 238000004380 ashing Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 4
- YJCCSLGGODRWKK-NSCUHMNNSA-N 4-Acetamido-4'-isothiocyanostilbene-2,2'-disulphonic acid Chemical compound OS(=O)(=O)C1=CC(NC(=O)C)=CC=C1\C=C\C1=CC=C(N=C=S)C=C1S(O)(=O)=O YJCCSLGGODRWKK-NSCUHMNNSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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Abstract
The application provides an array substrate, a preparation method of the array substrate, a liquid crystal display panel and a display device. The preparation method of the array substrate comprises the following steps: providing a substrate; forming a gate electrode of a thin film transistor on a substrate; forming an active layer film and a first mask film covering the active layer film on one side of the grid electrode, which is far away from the substrate, wherein the orthographic projection of the active layer film on the substrate covers the substrate; carrying out graphical processing on the first mask film to obtain a first mask layer; etching the area of the active layer film which is not covered by the first mask layer to obtain an active layer of the thin film transistor; forming a first electrode film, covering the substrate with an orthographic projection of the first electrode film on the substrate, and etching the first electrode film to obtain a first electrode; removing the first mask layer; forming a second electrode, and a first electrode and a second electrode of the thin film transistor; one of the first electrode and the second electrode is a pixel electrode, the other one is a common electrode, and the pixel electrode is electrically connected with the first electrode.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for manufacturing the array substrate, a liquid crystal display panel, and a display device.
Background
Liquid crystal displays have the characteristics of small size, low power consumption, no radiation and the like, and are rapidly developed in recent years. The liquid crystal display can be classified into a twisted nematic display mode, a flat switching display mode, and an ADS (Advanced Super Dimension Switch) display mode, etc., according to a display mode.
With the development of liquid crystal display, an iads (exchange Advanced Super Dimension switch) display mode has been developed on the basis of the ADS display mode. The process cost of the display panel of the IADS display mode is high.
Disclosure of Invention
The application provides an array substrate, a preparation method of the array substrate, a liquid crystal display panel and a display device.
According to a first aspect of embodiments of the present application, there is provided a method for manufacturing an array substrate, including:
providing a substrate;
forming a gate electrode of a thin film transistor on the substrate;
forming an active layer film and a first mask film, wherein the active layer film is positioned on one side, away from the substrate, of the grid electrode, and the first mask film covers the active layer film, and the orthographic projection of the active layer film on the substrate covers the substrate;
carrying out graphical processing on the first mask film to obtain a first mask layer;
etching the area of the active layer film which is not covered by the first mask layer to obtain an active layer of the thin film transistor;
forming a first electrode film, covering the substrate with an orthographic projection of the first electrode film on the substrate, and etching the first electrode film to obtain a first electrode;
removing the first mask layer;
forming a second electrode, and a first electrode and a second electrode of the thin film transistor; one of the first electrode and the second electrode is a pixel electrode, the other one is a common electrode, and the pixel electrode is electrically connected with the first electrode.
In one embodiment, the etching the first electrode thin film to obtain a first electrode includes:
forming a second mask film covering the second electrode film on one side of the first electrode film, which is far away from the substrate, and carrying out graphical processing on the second mask film to obtain a second mask layer;
etching away the area of the first electrode film which is not covered by the second mask layer to obtain the first electrode;
after the area of the first electrode film not covered by the second mask layer is etched away to obtain the first electrode, the preparation method of the array substrate further comprises: removing the second mask layer; the step of removing the first mask layer and the step of removing the second mask layer are performed simultaneously.
In one embodiment, the first electrode is the pixel electrode; the first electrode overlaps the first electrode.
In one embodiment, the first electrode and the active layer are located on the same layer, and the first pole and the second pole are respectively overlapped with the active layer.
In one embodiment, the forming the second electrode and the first and second electrodes of the thin film transistor includes:
forming a first pole and a second pole of the thin film transistor;
forming an insulating layer on one side of the first pole and the second pole, which faces away from the substrate, wherein the insulating layer covers the first pole, the second pole and the first electrode; the thickness range of the insulating layer is 1000-10000 angstrom;
and forming a second electrode on one side of the insulating layer, which faces away from the substrate.
In one embodiment, the material of the first mask film is photoresist;
the removing the first mask layer includes: and removing the first mask layer by adopting an ashing process.
In one embodiment, the material of the pixel electrode and/or the common electrode is a transparent conductive material.
According to a second aspect of the embodiments of the present application, there is provided an array substrate, which is prepared by the above preparation method; the array substrate includes:
a substrate;
a gate electrode of a thin film transistor on the substrate;
the active layer and the first electrode are positioned on one side, away from the substrate, of the grid electrode;
a first electrode and a second electrode of the thin film transistor at least partially on a side of the active layer facing away from the substrate;
an insulating layer covering the first electrode, the second electrode, and the first electrode;
the second electrode is positioned on one side, away from the substrate, of the insulating layer; one of the first electrode and the second electrode is a pixel electrode, the other one of the first electrode and the second electrode is a common electrode, and the pixel electrode is electrically connected with the first electrode; the thickness of the part of the insulating layer, which is positioned on one side of the active layer, which is far away from the substrate is the same as that of the part of the insulating layer, which is positioned between the first electrode and the second electrode.
According to a third aspect of the embodiments of the present application, a liquid crystal display panel is provided, where the liquid crystal display panel includes the array substrate, a color film substrate located on a side of the array substrate away from the substrate, and a liquid crystal layer located between the array substrate and the color film substrate.
According to a fourth aspect of embodiments of the present application, there is provided a display device including the liquid crystal display panel described above.
In one embodiment, the display device further includes a backlight source, and the backlight source is disposed opposite to the light incident surface of the liquid crystal display panel.
According to the array substrate and the preparation method thereof, the liquid crystal display panel and the display device, when the array substrate is prepared, the first mask layer formed in the active layer forming process is not immediately removed after the active layer is formed, but is removed after the first electrode is formed, the active layer can be protected by the first mask layer in the first electrode forming process, the active layer is prevented from being etched in the first electrode film etching process, and the first mask layer is a film layer generated in the active layer forming process, so that the complexity of a preparation process and the process cost cannot be increased due to the formation and removal of the first mask layer. Therefore, the method for manufacturing the array substrate provided by the embodiment of the application can avoid etching the active layer in the process of forming the first electrode, and cannot cause increase of process cost.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an exemplary embodiment of the present disclosure;
fig. 2 is a partial cross-sectional view of a first intermediate structure of an array substrate provided in an exemplary embodiment of the present application;
FIG. 3 is a partial cross-sectional view of a second intermediate structure of an array substrate provided in an exemplary embodiment of the present application;
FIG. 4 is a partial cross-sectional view of a third intermediate structure of an array substrate provided in an exemplary embodiment of the present application;
fig. 5 is a partial cross-sectional view of a fourth intermediate structure of an array substrate according to an exemplary embodiment of the present application;
FIG. 6 is a partial cross-sectional view of a fifth intermediate structure of an array substrate provided in an exemplary embodiment of the present application;
FIG. 7 is a partial cross-sectional view of a sixth intermediate structure of an array substrate provided in an exemplary embodiment of the present application;
fig. 8 is a partial cross-sectional view of a seventh intermediate structure of an array substrate according to an exemplary embodiment of the present application;
fig. 9 is a partial cross-sectional view of an eighth intermediate structure of an array substrate provided in an exemplary embodiment of the present application;
FIG. 10 is a partial cross-sectional view of a ninth intermediate structure of an array substrate according to an exemplary embodiment of the present application;
FIG. 11 is a partial cross-sectional view of a tenth intermediate structure of an array substrate provided in an exemplary embodiment of the present application;
fig. 12 is a partial cross-sectional view of an array substrate provided in an exemplary embodiment of the present application;
fig. 13 is a schematic structural diagram of a liquid crystal display panel according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if," as used herein, may be interpreted as "at … …" or "when … …" or "in response to a determination," depending on the context.
As described in the background art, the process cost of the display panel of the IADS display mode is high. The inventor finds out that the reason is as follows: in the preparation process of the display panel of the IADS display mode, the active layer of the thin film transistor is formed first, and then the pixel electrode is formed, but the active layer is etched in the process of forming the pixel electrode by using an etching process. In order to avoid this problem, a passivation layer for protecting the active layer may be formed after the active layer is formed and before the pixel electrode is formed. The formation of the passivation layer increases the number of masks, and increases the process cost and the process time.
The embodiment of the application provides an array substrate, a preparation method thereof, a liquid crystal display panel and a display device, and can solve the technical problems. The array substrate, the method for manufacturing the array substrate, the liquid crystal display panel and the display device in the embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the embodiments described below may complement or be combined with each other without conflict.
The embodiment of the application provides a preparation method of an array substrate. Referring to fig. 1, the method for manufacturing the array substrate includes the following steps 110 to 180.
In step 110, a substrate is provided.
In step 120, a gate of a thin film transistor located on the substrate is formed.
In step 130, an active layer film and a first mask film are formed on the side of the gate electrode away from the substrate, wherein the orthographic projection of the active layer film on the substrate covers the substrate.
In step 140, a first mask layer is obtained by patterning the first mask film.
In step 150, etching away a region of the active layer film not covered by the first mask layer to obtain an active layer of the thin film transistor.
In step 160, a first electrode thin film is formed, an orthographic projection of the first electrode thin film on the substrate covers the substrate, and the first electrode thin film is etched to obtain a first electrode.
In step 170, the first mask layer is removed.
In step 180, forming a second electrode, and a first and a second pole of the thin film transistor; one of the first electrode and the second electrode is a pixel electrode, the other one of the first electrode and the second electrode is a common electrode, and the pixel electrode is electrically connected with the first electrode.
According to the preparation method of the array substrate, the first mask layer formed in the active layer forming process is not removed immediately after the active layer is formed, but is removed after the first electrode is formed, the active layer can be protected by the first mask layer in the first electrode forming process, the active layer is prevented from being etched in the first electrode thin film etching process, the first mask layer is a film layer generated in the active layer forming process, and the complexity and the process cost of the preparation process are not increased due to the formation and the removal of the first mask layer. Therefore, the method for manufacturing the array substrate provided by the embodiment of the application can avoid etching the active layer in the process of forming the first electrode, and cannot cause the increase of the process cost.
The following describes in detail each step of the method for manufacturing an array substrate provided in the embodiments of the present application. The following is a description of the fabrication process of the array substrate. The "patterning process" described in the embodiments of the present application includes a series of processes of depositing a film, coating a photoresist, mask exposing, developing, etching, and stripping the photoresist. The deposition may employ any one or more selected from sputtering, evaporation and chemical vapor deposition, and the etching may employ any one or more selected from dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. When the "thin film" is subjected to a patterning process throughout the fabrication process, the "thin film" is referred to as a "thin film" before the patterning process, and the "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".
In step 110, a substrate is provided.
In one embodiment, the substrate may be a flexible substrate or a rigid substrate. The material of the flexible substrate may include one or more of polyimide, polyethylene terephthalate, and polycarbonate. The material of the rigid substrate may be glass, silicon, etc.
In step 120, a gate of a thin film transistor on the substrate is formed.
A first intermediate structure as shown in fig. 2 is obtained, via step 120. As shown in fig. 2, the gate 21 is located on the substrate 10.
In one embodiment, the step 120 of forming a gate electrode of a thin film transistor on the substrate includes the following processes:
firstly, a gate film is deposited on a substrate, and the orthographic projection of the gate film on the substrate can cover the substrate.
And then, patterning the gate thin film through a patterning process to obtain a gate.
In one embodiment, the step of patterning the gate thin film through a patterning process may include the steps of:
forming a third mask film covering the gate film on the gate film, and performing patterning processing on the third mask film to obtain a third mask layer, wherein the third mask layer has the same pattern as a gate layer to be formed (the gate layer includes a gate and a gate line), and corresponds to the gate layer in a direction perpendicular to the substrate 10; etching the area of the grid film which is not covered by the third mask layer by using the third mask layer as a shield, wherein the part of the grid film which is not etched is a grid layer; and finally, removing the third mask layer to expose the gate layer comprising the gate.
In one embodiment, the third mask film is made of photoresist, and may be patterned by exposure and development processes, and may be removed by an ashing process. The process for forming the third mask film by using the photoresist material is mature, and the process for removing the third mask layer is easy to operate.
In one embodiment, the material of the third mask film may be a positive photoresist or a negative photoresist.
In one embodiment, after step 120, the method for manufacturing an array substrate further includes: and forming a gate insulating layer on one side of the gate, which is far away from the substrate, wherein the orthographic projection of the gate insulating layer on the substrate can cover the substrate.
By this step a second intermediate structure as shown in fig. 3 is obtained. As shown in fig. 3, the gate insulating layer 30 covers the gate electrode 21 and the exposed substrate 10. The material of the gate insulating layer 30 may include at least one of silicon nitride and silicon oxide.
In step 130, an active layer film and a first mask film are formed, wherein the active layer film is located on one side, away from the substrate, of the gate electrode, and the first mask film covers the active layer film, and the orthographic projection of the active layer film on the substrate covers the substrate.
A third intermediate structure as shown in fig. 4 may be obtained, via step 130. As shown in fig. 4, the orthographic projections of the active layer film 22 and the first mask film 41 on the substrate 10 both cover the substrate 10.
In one embodiment, the material of the active layer film may be an oxide, for example, a metal oxide. The oxide is used as the material of the active layer, so that the thin film transistor has the advantages of high charging speed, good voltage holding characteristic and the like, the preparation temperature of the oxide active layer is low, the size uniformity is good, the size of the thin film transistor can be reduced, the thin film transistor is suitable for high-resolution products, the frame size of the array substrate can be reduced, the aperture opening ratio of pixels is improved, and the power consumption of the array substrate can be reduced.
In one embodiment, the material of the first mask film is photoresist. The process of forming the first mask film by using the photoresist material is mature, and the subsequent removal process is easy to operate. The material of the first mask film can be positive photoresist or negative photoresist.
In step 140, the first mask film is patterned to obtain a first mask layer.
In an embodiment, when the first mask film is made of a photoresist, the first mask film may be exposed and developed, and a partial region of the first mask film is removed to obtain a first mask layer. The first mask layer is the same as the pattern of the active layer to be formed and corresponds to the active layer in a direction perpendicular to the substrate 10.
In step 150, etching away a region of the active layer film not covered by the first mask layer to obtain an active layer of the thin film transistor.
A fourth intermediate structure as shown in fig. 5 may be obtained, via step 150. As shown in fig. 5, an orthographic projection of the first mask layer 411 on the substrate 10 coincides with an orthographic projection of the active layer 23 on the substrate 10.
In one embodiment, the active layer film may be etched using a wet etch process.
In step 160, a first electrode film is formed, an orthographic projection of the first electrode film on the substrate covers the substrate, and the first electrode film is etched to obtain a first electrode.
In one embodiment, after the step of forming the first electrode thin film, a fifth intermediate structure as shown in fig. 6 is obtained. As shown in fig. 6, an orthographic projection of the first electrode film 50 on the substrate 10 covers the substrate 10, that is, the first electrode film 50 covers the first mask layer 411 and the exposed gate insulating layer 30.
In an embodiment, the step of etching the first electrode film to obtain the first electrode may include:
firstly, forming a second mask film covering the second electrode film on one side of the first electrode film, which is far away from the substrate, and carrying out graphical processing on the second mask film to obtain a second mask layer.
By this step a sixth intermediate structure as shown in fig. 7 is obtained. As shown in fig. 7, there is no overlap area between the orthographic projection of the second mask layer 421 on the substrate 10 and the orthographic projection of the first mask layer 411 on the substrate 10. The second mask layer 421 is the same as the pattern of the first electrode to be formed and corresponds to the first electrode in a direction perpendicular to the substrate 10.
In one embodiment, the second mask film is made of photoresist, and the second mask film may be patterned by exposure and development processes.
In one embodiment, the material of the second mask film may be a positive photoresist or a negative photoresist.
And etching away the area of the first electrode film which is not covered by the second mask layer to obtain the first electrode.
By this step a seventh intermediate structure as shown in fig. 8 is obtained. As shown in fig. 8, an orthogonal projection of the first electrode 61 on the substrate 10 coincides with an orthogonal projection of the second mask layer 421 on the substrate 10.
In one embodiment, the first electrode thin film may be etched using a wet etching process.
In an embodiment, after the step of etching away a region of the first electrode film not covered by the second mask layer to obtain the first electrode, the method for manufacturing an array substrate further includes: and removing the second mask layer. After the second mask layer 421 is removed, the first electrode 61 is exposed.
In one embodiment, the second mask layer may be removed using an ashing process.
In step 170, the first mask layer is removed.
In one embodiment, when the material of the first mask film is a photoresist, the removing the first mask layer includes: and removing the first mask layer by adopting an ashing process.
In one embodiment, the step of removing the first mask layer is performed simultaneously with the step of removing the second mask layer. Therefore, the first mask layer and the second mask layer can be removed simultaneously in one process step, and compared with a scheme that the first mask layer and the second mask layer are removed by adopting separate steps, the scheme is beneficial to simplifying the preparation process of the array substrate and reducing the process complexity.
In one embodiment, the first mask layer and the second mask layer are made of photoresist, and the first mask layer and the second mask layer can be removed simultaneously by adopting an ashing process.
In one embodiment, after the first mask layer and the second mask layer are removed, an eighth intermediate structure as shown in fig. 9 can be obtained. As shown in fig. 9, both the active layer 23 and the first electrode 61 are exposed.
In step 180, forming a second electrode, and a first and a second pole of the thin film transistor; one of the first electrode and the second electrode is a pixel electrode, the other one is a common electrode, and the pixel electrode is electrically connected with the first electrode.
In one embodiment, the step 180 of forming the second electrode and the first and second electrodes of the thin film transistor comprises the following processes:
first, a first pole and a second pole of the thin film transistor are formed.
By this step, the ninth intermediate structure shown in fig. 10 can be obtained. As shown in fig. 10, the first and second electrodes 24 and 25 of the thin film transistor 20 are electrically connected to the active layer 23, respectively. One of the first and second poles 24 and 25 is a source and the other is a drain. In forming the first and second poles, signal lines such as data lines may be formed simultaneously.
Subsequently, an insulating layer is formed on the side of the first pole, which faces away from the substrate, and covers the first pole, the second pole and the first electrode.
A tenth intermediate structure as shown in fig. 11 can be obtained by this step. As shown in fig. 11, an orthogonal projection of the insulating layer 70 on the substrate 10 covers the substrate 10. That is, the insulating layer 70 covers the first and second electrodes 24 and 25, the exposed active layer 23, the first electrode 61, and the exposed gate insulating layer 30.
Subsequently, a second electrode is formed on the side of the insulating layer facing away from the substrate.
Through this step, an array substrate as shown in fig. 12 may be obtained. As shown in fig. 12, the second electrode 62 is disposed opposite to the first electrode 61, and the insulating layer 70 insulates the second electrode 62 from the first electrode 61.
In one embodiment, the step of forming the second electrode on the side of the insulating layer facing away from the substrate may be achieved by:
forming a second electrode film on one side of the insulating layer, which is far away from the substrate, wherein the orthographic projection of the second electrode film on the substrate covers the substrate; forming a fourth mask film covering the second electrode film on the second electrode film, and carrying out patterning treatment on the fourth mask film to obtain a fourth mask layer, wherein the fourth mask layer has the same pattern as the second electrode to be formed and corresponds to the second electrode in the direction vertical to the substrate; etching the region of the second electrode film, which is not covered by the fourth mask layer, by using the fourth mask layer as a shield, wherein the part of the second electrode film, which is not etched, is the second electrode; and finally, removing the fourth mask layer to expose the second electrode.
In an embodiment, the fourth mask film is made of a photoresist, and may be patterned by an exposure and development process, and may be removed by an ashing process. The process for forming the fourth mask film by using the photoresist material is mature, and the process for removing the fourth mask film is easy to operate.
According to the array substrate prepared by the preparation method of the array substrate, only one insulating layer is arranged between the first electrode and the second electrode, the distance between the first electrode and the second electrode is small, the storage capacitance of pixels can be effectively improved, the anti-capacitive coupling pulling capacity is improved, and the risk of signal crosstalk between different pixels is reduced.
In one embodiment, as shown in fig. 12, the first electrode 61 is the pixel electrode, and the second electrode 62 is a common electrode; the first pole 24 overlaps the first electrode 61. That is, the first pole 24 is directly contacted with the first electrode 61, and compared with a scheme that the first pole 24 is electrically connected with the first electrode 61 through the connecting electrode and the via hole, the space occupied by the via hole and the connecting electrode does not need to be reserved, and the pixel aperture ratio and the transmittance of the array substrate can be improved.
In one embodiment, as shown in fig. 12, the first electrode 61 and the active layer 23 are located at the same layer, and the first pole 24 and the second pole 25 respectively overlap with the active layer 23. Where the first electrode 61 is located at the same layer as the active layer 23, it means that both are in direct contact with the same film layer. In the embodiment shown in fig. 12, the first electrode 61 and the active layer 23 are both in direct contact with the gate insulating layer 30. Since the first electrode 61 and the active layer 23 are located on the same layer, no insulating layer is disposed between the first electrode 24 and the first electrode 61, and the first electrode 24 is directly connected to the first electrode 61, the first electrode 24 and the second electrode 25 can also be directly connected to the active layer 23, which facilitates electrical connection between the first electrode 24 and the active layer 23 and between the second electrode 25 and the active layer 23.
In one embodiment, the thickness of the insulating layer 70 ranges from 1000 angstroms to 10000 angstroms. By such arrangement, the charging rate of the array substrate can be prevented from being influenced by too small thickness of the insulating layer 70 and too large coupling capacitance between the first electrode and the second electrode and other conductive structures, and the phenomenon that too small storage capacitance of a pixel and signal crosstalk occur among different pixels are also prevented from being caused by too large thickness of the insulating layer 70. In some embodiments, the insulating layer 70 has a thickness of, for example, 1000 angstroms, 3000 angstroms, 5000 angstroms, 7000 angstroms, 9000 angstroms, 10000 angstroms, or the like.
In one embodiment, the material of the insulating layer 70 includes at least one of silicon nitride and silicon oxide.
In one embodiment, the material of the pixel electrode and/or the common electrode is a transparent conductive material. By such arrangement, the transmittance of the array substrate can be improved. In some embodiments, the pixel electrode is made of a transparent conductive material, or the common electrode is made of a transparent conductive material, or both the pixel electrode and the common electrode are made of a transparent conductive material.
In some embodiments, the transparent conductive material may include at least one of indium zinc oxide and indium tin oxide.
In one embodiment, the pixel electrode is a plate electrode, and the common electrode is a strip electrode; or, the pixel electrode is a strip electrode, and the common electrode is a plate electrode.
The embodiment of the application also provides an array substrate, and the array substrate is prepared by adopting the preparation method of any one of the embodiments. As shown in fig. 12, the array substrate includes a substrate 10, a thin film transistor 20 on the substrate 10, a first electrode 61, a second electrode 62, and an insulating layer 70. The thin film transistor 20 includes a gate electrode 21, an active layer 23, a first electrode 24, and a second electrode 25; one of the first and second poles 24 and 25 is a source and the other is a drain. One of the first electrode 61 and the second electrode 62 is a pixel electrode, and the other is a common electrode. The pixel electrode is electrically connected to the first electrode 24.
A gate 21 is located on the substrate 10. The active layer 23 and the first electrode 61 are located on a side of the gate electrode 21 facing away from the substrate 10. The first pole 24 and the second pole 25 are at least partly located on a side of the active layer 23 facing away from the substrate 10. An insulating layer 70 covers the first pole 24, the second pole 25, and the first electrode 61. The second electrode 62 is located on a side of the insulating layer 70 facing away from the substrate 10. An orthographic projection of the insulating layer 70 on the substrate 10 covers the substrate 10. The thickness of the portion of the insulating layer 70 above the active layer 23 is the same as the thickness of the portion of the insulating layer 70 between the first electrode 61 and the second electrode 62. Here, the portion of the insulating layer 70 above the active layer 23 refers to a portion of the insulating layer 70 corresponding to the active layer 23 in a direction perpendicular to the substrate 10. The thickness of the portion of the insulating layer 70 above the active layer 23 is the same as the thickness of the portion of the insulating layer 70 between the first electrode 61 and the second electrode 62, which means that the thickness of the portion of the insulating layer 70 above the active layer 23 is substantially the same as the thickness of the portion of the insulating layer 70 between the first electrode 61 and the second electrode 62, including the case where the thicknesses are the same and the difference in the thicknesses is small. That is, a portion of the insulating layer 70 above the active layer 23 and a portion of the insulating layer 70 between the first electrode 61 and the second electrode 62 are simultaneously formed.
In the array substrate provided by the embodiment of the application, since the orthographic projection of the insulating layer 70 on the substrate 10 covers the substrate 10, and the thickness of the part of the insulating layer 70 above the active layer 23 is the same as the thickness of the part of the insulating layer 70 between the first electrode 61 and the second electrode 62, the insulating layer 70 is formed in one process step, and no other insulating layer is formed after the active layer is formed and before the insulating layer is formed; according to the preparation method of the array substrate, the first mask layer formed in the process of forming the active layer can protect the active layer in the process of forming the first electrode, the active layer is prevented from being etched in the process of etching the first electrode film, and the complexity and the process cost of the preparation process are not increased due to the formation and removal of the first mask layer. Therefore, the array substrate provided by the embodiment of the application does not cause increase of process cost in the preparation process.
In one embodiment, as shown in fig. 12, the array substrate further includes a gate insulating layer 30, the gate insulating layer 30 is located on a side of the gate 21 facing away from the substrate 10, and the active layer 23 and the first electrode 61 are both located on a side of the gate insulating layer 30 facing away from the substrate 10.
In one embodiment, the first electrode 61 is the pixel electrode, and the second electrode 62 is a common electrode; the first pole 24 overlaps the first electrode 61.
In one embodiment, the first electrode 61 and the active layer 23 are located on the same layer, and the first pole 24 and the second pole 25 respectively overlap with the active layer 23.
In one embodiment, the thickness of the insulating layer 70 ranges from 1000 angstroms to 10000 angstroms.
In one embodiment, the material of the pixel electrode and/or the common electrode is a transparent conductive material.
In one embodiment, the pixel electrode is a plate electrode, and the common electrode is a strip electrode; or, the pixel electrode is a strip electrode, and the common electrode is a plate electrode.
The array substrate provided by the embodiment of the application can be applied to a large-size high-resolution liquid crystal display panel, for example, to liquid crystal display panels with resolutions of 16K and 18K.
Since the array substrate and the method for manufacturing the same belong to the same inventive concept, the description of the relevant details and the beneficial effects can be referred to each other, and are not repeated herein.
An embodiment of the present application further provides a liquid crystal display panel, as shown in fig. 13, where the liquid crystal display panel includes the array substrate 100 according to any of the embodiments, a color filter substrate 200 located on a side of the array substrate 100 away from the substrate, and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200.
In one embodiment, the color filter substrate 200 includes a black matrix layer 210 and a color filter 220. The black matrix layer 210 is provided with a plurality of through holes, and the color resists 220 are filled in the through holes.
Since the liquid crystal display panel includes the array substrate, the same advantages are achieved, and further description is omitted here.
The embodiment of the application also provides a preparation method of the liquid crystal display panel, and the preparation method of the liquid crystal display panel comprises the preparation method of the array substrate in any embodiment.
Since the preparation method of the liquid crystal display panel comprises the preparation method of the array substrate, the same beneficial effects are achieved, and the details are not repeated.
The embodiment of the application also provides a display device which comprises the liquid crystal display panel.
In one embodiment, the display device further includes a backlight source, and the backlight source is disposed opposite to the light incident surface of the liquid crystal display panel. The backlight may be an LED backlight. The LED backlight source is adopted, so that the display device has lower power consumption and better image color display effect.
In one embodiment, the display device further comprises a housing, and the liquid crystal display panel may be embedded in the housing.
Since the display device includes the array substrate, the same advantages are achieved, and further description is omitted here.
The application of the display device is not particularly limited, and the display device can be any product or component with a flexible display function, such as a television, a notebook computer, a tablet computer, a wearable display device, a mobile phone, a vehicle-mounted display, a navigation, an electronic book, a digital photo frame, an advertising lamp box and the like.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element can also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (11)
1. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a gate electrode of a thin film transistor on the substrate;
forming an active layer film and a first mask film, wherein the active layer film is positioned on one side, away from the substrate, of the grid electrode, and the first mask film covers the active layer film, and the orthographic projection of the active layer film on the substrate covers the substrate;
carrying out graphical processing on the first mask film to obtain a first mask layer;
etching away the area of the active layer film which is not covered by the first mask layer to obtain an active layer of the thin film transistor;
forming a first electrode film, covering the substrate by the orthographic projection of the first electrode film on the substrate, and etching the first electrode film to obtain a first electrode;
removing the first mask layer;
forming a second electrode, and a first electrode and a second electrode of the thin film transistor; one of the first electrode and the second electrode is a pixel electrode, the other one is a common electrode, and the pixel electrode is electrically connected with the first electrode.
2. The method for preparing the array substrate according to claim 1, wherein the etching the first electrode thin film to obtain the first electrode comprises:
forming a second mask film covering the second electrode film on one side of the first electrode film, which is far away from the substrate, and carrying out graphical processing on the second mask film to obtain a second mask layer;
etching away the area of the first electrode film which is not covered by the second mask layer to obtain the first electrode;
after the area of the first electrode film not covered by the second mask layer is etched away to obtain the first electrode, the preparation method of the array substrate further comprises: removing the second mask layer; the step of removing the first mask layer and the step of removing the second mask layer are performed simultaneously.
3. The method for manufacturing an array substrate according to claim 1, wherein the first electrode is the pixel electrode; the first electrode is overlapped with the first electrode.
4. The method of claim 3, wherein the first electrode and the active layer are on the same layer, and the first electrode and the second electrode are respectively overlapped with the active layer.
5. The method for manufacturing an array substrate according to claim 1, wherein the forming the second electrode and the first and second electrodes of the thin film transistor comprises:
forming a first pole and a second pole of the thin film transistor;
forming an insulating layer on the side of the first pole and the second pole facing away from the substrate, wherein the insulating layer covers the first pole, the second pole and the first electrode; the thickness range of the insulating layer is 1000-10000 angstrom;
and forming a second electrode on one side of the insulating layer, which faces away from the substrate.
6. The method for preparing the array substrate according to claim 1, wherein the first mask film is made of photoresist;
the removing the first mask layer includes: and removing the first mask layer by adopting an ashing process.
7. The method for manufacturing the array substrate according to claim 1, wherein a material of the pixel electrode and/or the common electrode is a transparent conductive material.
8. An array substrate, wherein the array substrate is prepared by the preparation method of any one of claims 1 to 7; the array substrate includes:
a substrate;
a gate electrode of a thin film transistor on the substrate;
the active layer and the first electrode are positioned on one side, away from the substrate, of the grid electrode;
a first and a second pole of the thin film transistor at least partially on a side of the active layer facing away from the substrate;
an insulating layer covering the first electrode, the second electrode, and the first electrode;
the second electrode is positioned on one side, away from the substrate, of the insulating layer; one of the first electrode and the second electrode is a pixel electrode, the other one of the first electrode and the second electrode is a common electrode, and the pixel electrode is electrically connected with the first electrode; the thickness of the part of the insulating layer, which is positioned on the side of the active layer, which is far away from the substrate is the same as that of the part of the insulating layer, which is positioned between the first electrode and the second electrode.
9. A liquid crystal display panel, comprising the array substrate of claim 8, a color filter substrate located on a side of the array substrate away from the substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.
10. A display device characterized by comprising the liquid crystal display panel according to claim 9.
11. The display device according to claim 10, further comprising a backlight source disposed opposite to the light incident surface of the liquid crystal display panel.
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