CN114758939B - Thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization and manufacturing method thereof - Google Patents
Thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization and manufacturing method thereof Download PDFInfo
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- CN114758939B CN114758939B CN202210378551.6A CN202210378551A CN114758939B CN 114758939 B CN114758939 B CN 114758939B CN 202210378551 A CN202210378551 A CN 202210378551A CN 114758939 B CN114758939 B CN 114758939B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/26—Electron or ion microscopes; Electron or ion diffraction tubes
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- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00047—Cavities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
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Abstract
The invention discloses a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization and a manufacturing method thereof, comprising a substrate chip and a top plate chip, wherein the substrate chip comprises a first silicon substrate, dielectric layers on the upper surface and the lower surface of the first silicon substrate, a contact electrode, a heating electrode, an electric field electrode and an isolation layer, wherein the contact electrode, the heating electrode, the electric field electrode and the isolation layer are deposited on the dielectric layers on the upper surface; manufacturing a first observation window on a substrate chip; the top plate chip comprises a second silicon substrate, dielectric layers on the upper surface and the lower surface of the second silicon substrate, and a second observation window on the top plate chip is manufactured. And placing the sample in an observation window area of a substrate chip, bonding the substrate chip and a top plate chip, and placing the substrate chip and the top plate chip into a matched transmission electron microscope sample rod for use. The invention can heat the sample in the sealed cavity, can synchronously apply an additional electric field locally, and is beneficial to observing the dynamic growth process of the material under the induction of the electric field in real time in the in-situ characterization process of the transmission electron microscope.
Description
Technical Field
The invention belongs to the fields of electron microscopy, micro-nano processing and MEMS devices, and particularly relates to a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization.
Background
A transmission electron microscope (Transmission Electron Microscope, abbreviated as TEM) is a tool that uses a high-energy electron beam accelerated at high pressure as an imaging light source to realize microscopic imaging of a sample in the atomic scale to micrometer scale by using an electron beam penetrating the sample. The characterization based on the transmission electron microscope is an important material characterization technology, and the in-situ characterization is a characterization method for observing the structure evolution process in the growth or chemical physical reaction process of a material sample in real time under the atomic scale through the transmission electron microscope.
Since the chamber of a transmission electron microscope is typically in a high vacuum environment (vacuum level is typically less than 10) -4 Pa), and thus the introduction of gas and thermal/electric field environments in transmission electron microscopy is often difficult, often requiring complex gas differential structures or specially tailored sample rod attachments. This results in the observation of dynamic growth processes of materials in transmission electron microscopy and failure evolution processes under operating conditions becoming very difficult. Although the Environmental Transmission Electron Microscope (ETEM) technology and the gas sample rod technology (Protochips Co., USA) have been developed internationallyAnd Denshift corporation, netherlands) technology can be introduced into a certain gas environment, but both schemes have the characteristics of complex structure, high cost and the like. In contrast, the gas, electricity and heat coupling chip structure which has simple structure, low cost and convenient use is developed and is suitable for the representation of a transmission electron microscope, and has important significance for researching the growth and evolution mechanism of materials under the atmosphere.
MEMS (Micro-Electro-Mechanical Systems) processing technology is a technology for Micro-processing materials by means of chemical corrosion and the like on nanometer and micrometer scale, can be compatible with the traditional IC technology, and is widely applied to processing of various electronic devices and material structures. MEMS processing techniques can be divided into bulk micromachining and surface micromachining techniques. The bulk micromachining technology mainly utilizes deep silicon etching, chemical etching and other technologies to carry out three-dimensional machining on materials, and the surface micromachining technology is a machining technology based on a film structure.
The in-situ chip with the airtight microcavity, the heating electrode and the electric field electrode is manufactured through MEMS technology processing, a place for bearing and chemically growing a sample can be provided by matching with a transmission electron microscope sample rod, an electric field can be introduced while heating, electric field environments with different degrees can be applied to the material, and the process of structural evolution in chemical reaction can be observed in atomic scale, so that the in-situ chip is a low-cost and convenient technical scheme capable of realizing the growth and evolution of the observed material in different working condition environments. In order to meet the high-resolution observation requirement of a transmission electron microscope and avoid the safety risk caused by directly using an external gas source, the in-situ chip needs to meet the following conditions: (1) Two independent heating zones, one for heating and evaporating the solid source, and the other for temperature control of the reaction zone and forming a temperature difference with the other heating zone so that the evaporating gas flows to the reaction zone. (2) The film thickness at the window for transmission electron microscope viewing needs to meet the requirements of transmission electron microscope high resolution imaging. (3) a relatively closed microcavity is used to restrict the gas flow. (4) And (3) carrying out external connection with a port of a control measurement circuit in cooperation with the sample rod. (5) The observation window area needs to be provided with an electrode pair for realizing local electric field loading, so that the growth process of materials in the electric field can be observed conveniently.
At present, no in-situ chip product is provided with a closed microcavity, two discrete heating sources and an externally-applied multi-field strength electric field at the same time, and the invention not only can realize heating of a sample in the closed cavity and externally-applied multi-field strength electric field, but also can observe the complex process of growth and reaction of a material under the induction of the electric field in real time in the in-situ characterization process of a transmission electron microscope, thereby filling the gap of the market.
Disclosure of Invention
Technical problems: the invention aims to provide a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization and a manufacturing method thereof. The chip can provide a high-pressure atmosphere reaction environment for materials, provide conditions for complex processes such as material growth, and induce material change through an electric field. Meanwhile, a process flow method for chip batch manufacturing is provided.
The technical scheme is as follows: in order to achieve the above purpose, the thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization comprises a substrate chip and a top plate chip;
the substrate chip comprises a first silicon substrate, a first lower surface dielectric layer, a first upper surface dielectric layer, a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolation layer;
the first lower surface dielectric layer and the first upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the first silicon substrate; the substrate chip contact electrode, the substrate chip heating electrode, the substrate chip electric field electrode and the substrate chip isolation layer are respectively positioned on the surface of the first upper surface dielectric layer; the substrate chip contact electrode is respectively connected with the substrate chip heating electrode and the substrate chip electric field electrode and is used for electric introduction;
the substrate chip further comprises a first hollow area penetrating through the first silicon substrate and the first lower surface dielectric layer, and the first upper surface dielectric layer positioned on the first hollow area is used as a first observation window; the first hollowed-out area covers a first observation window area, and the areas where the substrate chip heating electrode and the substrate chip electric field electrode are located correspond to the area where the first observation window is located;
the substrate chip isolation layer is used for preventing sublimate gas from losing and supporting the top plate chip;
the top plate chip comprises a second silicon substrate, a second lower surface dielectric layer and a second upper surface dielectric layer, wherein the second lower surface dielectric layer and the second upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the second silicon substrate; the top plate chip further comprises a second hollowed-out area penetrating through the second silicon substrate and the dielectric layer on the lower surface of the second silicon substrate, and a second observation window is constructed by etching the dielectric layer on the second upper surface;
further, the substrate chip heating electrode is located around the substrate chip electric field electrode.
The sample or/and the catalyst are placed on the upper surface of the substrate chip and cover the substrate chip heating electrode, the upper surface of the top plate chip faces the substrate chip, the first hollowed-out area and the second hollowed-out area correspond to each other in the direction perpendicular to the surface of the first silicon substrate, the edge of the junction of the top plate chip and the substrate chip is bonded through the adhesive, a closed microcavity is formed between the upper surface of the top plate chip and the substrate chip, and the sample or/and the catalyst are located in the closed microcavity. The adhesive material is epoxy resin, silver colloid, ITO, indium or vacuum silicone grease.
Further, the substrate chip heating electrode comprises a first substrate chip heating electrode and a second substrate chip heating electrode, the area where the first substrate chip heating electrode is located is a high-temperature heating area, the area where the second substrate chip heating electrode is located is a temperature control area, and the second substrate chip heating electrode is arranged around the substrate chip electric field electrode.
Further, the electric field electrode of the substrate chip comprises two parallel polar plates, the two polar plates have the same structure, and the surfaces of the polar plates are stepped so as to ensure that the distance between the two polar plates has a plurality of values, and different distances correspond to different electric fields; thereby realizing the growth of the material under the induction of different electric fields. Three different distances are arranged between two parallel polar plates.
Further, a first lower surface dielectric layer and a first upper surface dielectric layerThe mass layer, the second lower surface dielectric layer and the second upper surface dielectric layer are all silicon oxide SiO 2 Silicon carbide SiC, silicon nitride Si 3 N 4 Alumina Al 2 O 3 The dielectric layer thickness of the insulating material of any one or more material combinations can be below 200nm.
Further, the substrate chip contact electrode, the substrate chip heating electrode and the substrate chip electric field electrode are made of any one or a combination of more of nickel, gold, copper, platinum, aluminum, tungsten, polysilicon and doped silicon, and the thickness of the electrode can be set below 100nm according to requirements.
Further, the substrate chip isolation layer material is nickel, gold, copper, platinum, aluminum, tungsten, polysilicon, silicon oxide SiO 2 Silicon carbide SiC, silicon nitride Si 3 N 4 Alumina Al 2 O 3 Any one or more of the above combinations, and the thickness is 100nm or less in accordance with the thickness of the electrode.
The manufacturing method of the thermal and electric field coupling type sealed cavity chip for the transmission electron microscope characterization is characterized by comprising the following steps of:
step 1, preparing a substrate chip
Step 1.1, depositing a first upper surface dielectric layer on the upper surface of a first silicon substrate, and depositing a first lower surface dielectric layer on the lower surface of the first silicon substrate;
step 1.2, depositing a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolation layer on the first upper surface dielectric layer;
step 1.3, forming a first hollowed-out area penetrating through a first lower surface dielectric layer and a first silicon substrate on the lower surface of the first silicon substrate; a first upper surface dielectric layer adjacent to the first hollowed-out area is used as a first observation window;
step 2, preparing a top plate chip
Step 2.1, depositing a second upper surface dielectric layer on the upper surface of a second silicon substrate, and depositing a second lower surface dielectric layer on the lower surface of the second silicon substrate;
step 2.2, etching the upper surface of the dielectric layer on the second lower surface to form a second observation window; forming a second hollow area penetrating through the second lower surface dielectric layer and the second silicon substrate on the lower surface of the second silicon substrate; the position of the second observation window corresponds to the second hollowed-out area;
and placing a sample or/and a catalyst on the surface of the substrate chip, and covering the substrate chip heating electrode.
Step 3, bonding the substrate chip and the top plate chip
The first observation window and the second observation window are aligned, and the edge of the junction of the top plate chip and the substrate chip is coated with adhesive for bonding, so that the substrate chip and the top plate chip are bonded.
The beneficial effects are that:
the invention provides a thermal and electric field coupling type sealed cavity chip suitable for transmission electron microscope characterization and a manufacturing method thereof, wherein a microcavity for reaction is provided in the transmission electron microscope, and two discrete heating areas and three discrete electric field areas are provided, so that the operations of independent temperature control, external application of electric fields with different field strengths and the like can be realized. The structure is utilized to heat and externally apply an electric field in the sealed cavity, and simultaneously, atomic level real-time observation of complicated reaction processes such as nano material growth and the like can be realized in the transmission electron microscope, and the influence of different electric field intensities on the reaction can be observed.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a top plate chip structure according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a substrate chip structure according to an embodiment of the present invention.
FIG. 3 is a schematic view of a structure in which a substrate chip and a top plate chip are combined
Fig. 4 is an enlarged schematic view of the upper surface of the substrate chip.
Fig. 5 is an enlarged view of a portion of the substrate chip heating electrode and the substrate chip electric field electrode in the observation window region.
The drawings are as follows: 1. a first silicon substrate; 2. a first lower surface dielectric layer; 3. a first upper surface dielectric layer; 4. a substrate chip contact electrode; 5. heating the electrode by the substrate chip; 51. a first substrate chip heating electrode; 52. a second substrate chip heating electrode; 6. a substrate chip electric field electrode; 7. the substrate chip isolation layer, 8 and the first hollow area; 9. a second silicon substrate; 10. a second lower surface dielectric layer; 11. a second upper surface dielectric layer; 12. a second hollow region; 13. an adhesive; 14. a first viewing window; 15. and a second viewing window.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization comprises a substrate chip and a top plate chip;
as shown in fig. 2, the substrate chip includes a first silicon substrate 1, a first lower surface dielectric layer 2, a first upper surface dielectric layer 3, a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7; wherein, the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are respectively positioned on the lower surface and the upper surface of the first silicon substrate 1; the substrate chip contact electrode 4, the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip isolation layer 7 are respectively positioned on the surface of the first upper surface dielectric layer 3; as shown in fig. 4, the substrate chip contact electrode 4 is connected to the substrate chip heating electrode 5 and the substrate chip electric field electrode 6, respectively, for electrical introduction.
The substrate chip further comprises a first hollow area 8 penetrating through the first silicon substrate 1 and the first lower surface dielectric layer 2, the first upper surface dielectric layer 3 adjacent to the first hollow area 8 is a first observation window 14, and the first hollow area 8 covers the area where the first observation window 14 is located. The areas of the substrate chip heating electrode 5 and the substrate chip electric field electrode 6 are corresponding to the areas of the first observation window 14.
As shown in fig. 5, the substrate chip heating electrode 5 includes a first substrate chip heating electrode 51 and a second substrate chip heating electrode 52, where the area where the first substrate chip heating electrode 51 is located is a high temperature heating area, and the second substrate chip heating electrode 52 for heating and evaporating the sample is disposed around the substrate chip electric field electrode 6, and is used for temperature-controlled growth of the material under electric field induction. The sample is heated and sublimated by the first chip heating electrode 51 and then is diffused to the temperature control area, so that the growth of the sample is observed under the condition of electric and thermal coupling.
The substrate chip electric field electrode 6 comprises two parallel polar plates, the two polar plates have the same structure, and the surfaces of the polar plates are stepped so as to ensure that the distance between the two polar plates has a plurality of values, and different distances correspond to different electric fields; thereby realizing the growth of the material under the induction of different electric fields. As shown in fig. 5, there are three pitch values between two parallel plates in fig. 5.
The substrate chip isolation layer 7 serves to prevent loss of sublimated gas and support the top plate chip.
As shown in fig. 1, the top plate chip includes a second silicon substrate 9, a second lower surface dielectric layer 10 and a second upper surface dielectric layer 11, where the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are respectively located on the lower surface and the upper surface of the second silicon substrate 9; the top plate chip further comprises a second hollow area 12 penetrating through the second silicon substrate 9 and the dielectric layer on the lower surface of the second silicon substrate 9, a second observation window 15 is constructed by etching the dielectric layer 11 on the second upper surface, and the second hollow area 12 covers the area where the second observation window 15 is located.
The sample or/and the catalyst is placed on the surface of the substrate chip, the first substrate chip heating electrode 51 is covered, the sample or/and the catalyst is heated, the upper surface of the top plate chip is opposite to the substrate chip, as shown in fig. 2, the first observation window 14 and the second observation window 15 are aligned, the edge of the junction between the top plate chip and the substrate chip is coated with the adhesive 13 for adhesion, so that the sample or/and the catalyst is in the airtight microcavity, and the first hollowed-out area 8 and the second hollowed-out area 12 correspond to each other in the direction perpendicular to the surface of the first silicon substrate 1. The adhesive 13 is made of epoxy resin, silver colloid, ITO, indium or vacuum silicone grease.
The first lower surface dielectric layer 2, the first upper surface dielectric layer 3, the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are all silicon oxide SiO 2 Silicon carbide SiC, silicon nitride Si 3 N 4 Alumina Al 2 O 3 The dielectric layer thickness of the insulating material of any one or more material combinations can be below 200nm.
The substrate chip contact electrode 4, the substrate chip heating electrode 5 and the substrate chip electric field electrode 6 are made of any one or a combination of more of nickel, gold, copper, platinum, aluminum, tungsten, polysilicon and doped silicon, and the thickness of the electrodes can be set below 100nm according to requirements.
The substrate chip isolation layer 7 is made of nickel, gold, copper, platinum, aluminum, tungsten, polysilicon and silicon oxide SiO 2 Silicon carbide SiC, silicon nitride Si 3 N 4 Alumina Al 2 O 3 Any one or more of the above combinations, and the thickness is 100nm or less in accordance with the thickness of the electrode.
A manufacturing method of a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization comprises the following steps:
step 1, preparing a substrate chip
Step 1.1, depositing a first upper surface dielectric layer 3 on the upper surface of a first silicon substrate 1, and depositing a first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
step 1.2, depositing a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3;
step 1.3, forming a first hollow area 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1 on the lower surface of the first silicon substrate 1; the first upper surface dielectric layer 3 adjacent to the first hollow region 8 is a first viewing window 14.
Step 2, preparing a top plate chip
Step 2.1, depositing a second upper surface dielectric layer 11 on the upper surface of the second silicon substrate 9, and depositing a second lower surface dielectric layer 10 on the lower surface of the second silicon substrate 9;
step 2.2, etching the upper surface of the second silicon substrate 9 to form a second observation window 15; forming a second hollowed-out area 12 penetrating through a dielectric layer on the lower surface of the second silicon substrate 9 and the second silicon substrate 9 on the lower surface of the second silicon substrate 9;
a sample or/and a catalyst is placed on the substrate chip surface, covering the first substrate chip heating electrode 51.
Step 3, bonding the substrate chip and the top plate chip
The first viewing window 14 and the second viewing window 15 are aligned, and the adhesive 13 is coated on the edge of the junction between the top plate chip and the substrate chip to bond the substrate chip to the top plate chip.
The following description is given by way of example of the material composition, the size ranges of the respective portions of the base plate chip and the top plate chip, and the material composition of the adhesive 13, and the following description is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art will understand that modifications and substitutions are included in the scope of the present invention, and therefore, the scope of the present invention shall be defined by the scope of the claims.
Example 1
A thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization is shown in fig. 1 and 2, and comprises a substrate chip and a top plate chip.
The substrate chip comprises a first silicon substrate 1, a first lower surface dielectric layer 2, a first upper surface dielectric layer 3, a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7; the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are respectively positioned on the lower surface and the upper surface of the first silicon substrate 1; the substrate chip contact electrode 4, the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip isolation layer 7 are respectively positioned on the surface of the first upper surface dielectric layer 3;
the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are made of silicon nitride, and the thickness is 100nm;
the materials of the substrate chip contact electrode 4, the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip isolation layer 7 are gold, and the thickness is 100nm;
the substrate chip further comprises a first hollow area 8 penetrating through the first silicon substrate 1 and the first lower surface dielectric layer 2, the first upper surface dielectric layer 3 adjacent to the first hollow area 8 is a first observation window 14, and the first hollow area 8 covers the area where the first observation window 14 is located.
The top plate chip comprises a second silicon substrate 9, a second lower surface dielectric layer 10 and a second upper surface dielectric layer 11, wherein the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are respectively positioned on the lower surface and the upper surface of the second silicon substrate 9; the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are made of silicon nitride, and the thickness is 200nm;
a second hollow area 12 penetrating through the second silicon substrate 9 and the dielectric layer on the lower surface of the second silicon substrate 9 is constructed, the second upper surface dielectric layer 11 is etched to construct a second observation window 15, and the second hollow area 12 covers the area where the second observation window 15 is located.
As shown in fig. 3, the first hollowed-out area 8 corresponds to the second hollowed-out area 12 in a direction perpendicular to the surface of the first silicon substrate 1, and covers the first observation window 14 and the second observation window 15 between the electric field electrode and the heating electrode.
The top plate chip is brought into contact with the substrate chip with the first viewing window 14 and the second viewing window 15 aligned, and the adhesive 13 is applied to bond the edges of the junction of the top plate chip and the substrate chip.
The manufacturing method of the thermal and electric field coupling type sealed cavity chip for the transmission electron microscope characterization specifically comprises the following steps:
step 1, preparing a substrate chip
Step 1.1, depositing a first upper surface dielectric layer 3 on the upper surface of a first silicon substrate 1, and depositing a first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
specifically, a Low Pressure Chemical Vapor Deposition (LPCVD) is used to form an upper surface dielectric layer on the upper surface of the first silicon substrate 1, and a first lower surface dielectric layer 2 is formed on the lower surface, and the material is silicon nitride Si 3 N 4 The thickness was 100nm.
Step 1.2, depositing a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3;
specifically, a metal stripping (Lift-off) process is used to form patterns of a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3, the patterns are made of gold, the thickness of the patterns is 100nm, and the substrate chip isolation layer 7 is not in contact with the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip contact electrode 4, so that short circuit is avoided.
Step 1.3, forming a first hollow area 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1 on the lower surface of the first silicon substrate 1;
specifically, the first silicon substrate 1 and the first lower surface dielectric layer 2 are wet etched by using a potassium hydroxide etching solution, so as to form a first hollowed-out area 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1.
Step 2, preparing a top plate chip
Step 2.1, depositing a second upper surface dielectric layer 11 on the upper surface of the second silicon substrate 9, and depositing a second lower surface dielectric layer 10 on the lower surface of the second silicon substrate 9;
specifically, a Low Pressure Chemical Vapor Deposition (LPCVD) is used to form a dielectric layer on the upper surface of the second silicon substrate 9, and a dielectric layer on the lower surface of the second silicon substrate 9 is formed on the lower surface of the second silicon substrate 9, and the material is silicon nitride Si 3 N 4 The thickness was 200nm.
In step 2.2, the second observation window 15 is formed by etching on the upper surface of the second silicon substrate 9, specifically, the second observation window 15 is formed on the upper surface of the second silicon substrate 9 by Reactive Ion Etching (RIE) with an etching depth of 100nm.
Forming a second hollowed-out area 12 penetrating through a dielectric layer on the lower surface of the second silicon substrate 9 and the second silicon substrate 9 on the lower surface of the second silicon substrate 9; specifically, the second silicon substrate 9 and the second lower surface dielectric layer 10 are wet etched by using a potassium hydroxide etching solution, so as to form a second hollowed-out area 12 penetrating through the second lower surface dielectric layer 10 and the second silicon substrate 9.
A sample or/and a catalyst is placed on the substrate chip surface, covering the first substrate chip heating electrode 51.
Step 3, bonding the substrate chip and the top plate chip
The substrate chip is opposed to the top surface of the top plate chip such that the first viewing window 14 and the second viewing window 15 are aligned and the edge at the interface of the substrate chip and the top plate chip is bonded by the adhesive coating 13. Specifically, epoxy is used to coat the edges at the interface of the substrate chip and the top plate chip.
Example 2
A thermal, electric field coupling type sealed cavity chip for transmission electron microscope characterization, as shown in fig. 1 and 2, comprises a substrate chip and a top plate chip.
The substrate chip comprises a first silicon substrate 1, a first lower surface dielectric layer 2 positioned on the lower surface of the first silicon substrate 1, and a first upper surface dielectric layer 3 positioned on the upper surface of the first silicon substrate 1; the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are made of silicon nitride, and the thickness is 50nm; the first upper surface dielectric layer 3 is also provided with a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7, wherein the materials are platinum, and the thickness is 100nm; a first hollow 8 is constructed through the first silicon substrate 1 and the first lower surface dielectric layer 2, the first hollow 8 covering the first viewing window 14.
The top plate chip comprises a second silicon substrate 9, a second lower surface dielectric layer 10 positioned on the lower surface of the second silicon substrate 9 and a second upper surface dielectric layer 11 positioned on the upper surface of the second silicon substrate 9, wherein the materials of the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are silicon nitride, and the thickness is 100nm; constructing a second observation window 15 on the upper surface of the second silicon substrate 9; a second hollow region 12 is constructed through the second silicon substrate 9 and the second lower surface dielectric layer 10, the second hollow region 12 covering the second viewing window 15.
As shown in fig. 3, the first hollowed-out area 8 corresponds to the second hollowed-out area 12 in a direction perpendicular to the surface of the first silicon substrate 1, and covers the first observation window 14 and the second observation window 15 between the electric field electrode and the heating electrode.
The top plate chip is brought into contact with the substrate chip with the first viewing window 14 and the second viewing window 15 aligned, and the adhesive 13 is used to perform adhesive closure around.
The manufacturing method of the thermal and electric field coupling type sealed cavity chip for the transmission electron microscope characterization specifically comprises the following steps:
step 1, preparing a substrate chip
Step 1.1, depositing a first upper surface dielectric layer 3 on the upper surface of a first silicon substrate 1, and depositing a first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
specifically, a first upper surface dielectric layer 3 is formed on the upper surface of a first silicon substrate 1, and a first lower surface dielectric layer 2 is formed on the lower surface thereof by Low Pressure Chemical Vapor Deposition (LPCVD) of silicon nitride Si 3 N 4 The thickness was 50nm.
Step 1.2, depositing a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3;
specifically, a metal stripping (Lift-off) process is used to form patterns of a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3, the patterns are made of platinum, the thickness of the patterns is 100nm, and the substrate chip isolation layer 7 is not in contact with the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip contact electrode 4, so that short circuit is avoided.
Step 1.3, forming a first hollow area 8 penetrating through the first silicon substrate 1 and the first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
specifically, a first hollow area 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1 is formed on the lower surface of the first silicon substrate 1 by wet etching using a potassium hydroxide etching solution.
Step 2, preparing a top plate chip
Step 2.1, depositing a second upper surface dielectric layer 11 on the upper surface of the second silicon substrate 9, and depositing a second lower surface dielectric layer 10 on the lower surface of the second silicon substrate 9;
specifically, a second upper surface dielectric layer 11 is formed on the upper surface of the second silicon substrate 9, and a second lower surface dielectric layer 10 is formed on the lower surface thereof by Low Pressure Chemical Vapor Deposition (LPCVD) of silicon nitride Si 3 N 4 The thickness was 10nm.
Step 2.2, etching a second observation window 15 in the second upper surface dielectric layer 11, and forming a second hollow area 12 penetrating through the second silicon substrate 9 lower surface dielectric layer and the second silicon substrate 9 on the lower surface of the second silicon substrate 9. The second hollow area 12 covers a second viewing window 15.
Specifically, a second observation window 15 is formed on the upper surface of the second silicon substrate 9 by Reactive Ion Etching (RIE) to an etching depth of 50nm; and wet etching the second silicon substrate 9 and the second lower surface dielectric layer 10 by using potassium hydroxide corrosive liquid to form a second hollow area 12 penetrating through the second lower surface dielectric layer 10 and the second silicon substrate 9.
Placing a sample to be tested or/and a catalyst in the first observation window 14 and the second observation window 15 according to experimental requirements;
step 3, bonding the substrate chip and the top plate chip
The substrate chip is opposed to the top surface of the top plate chip such that the first viewing window 14 and the second viewing window 15 are aligned and adhesive 13 is applied at the edge of the substrate chip that interfaces with the top plate chip. Specifically, epoxy is used to coat the edges of the interface between the substrate die and the top plate die.
Claims (10)
1. The thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization is characterized by comprising a substrate chip and a top plate chip;
the substrate chip comprises a first silicon substrate, a first lower surface dielectric layer, a first upper surface dielectric layer, a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolation layer;
the first lower surface dielectric layer and the first upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the first silicon substrate; the substrate chip contact electrode, the substrate chip heating electrode, the substrate chip electric field electrode and the substrate chip isolation layer are respectively positioned on the surface of the first upper surface dielectric layer; the substrate chip heating electrode and the substrate chip electric field electrode are respectively connected with the respective substrate chip contact electrodes;
the substrate chip further comprises a first hollow area penetrating through the first silicon substrate and the first lower surface dielectric layer, and the first upper surface dielectric layer positioned on the first hollow area is used as a first observation window;
the substrate chip isolation layer is used for preventing sublimated gas from losing and supporting the top plate chip;
the top plate chip comprises a second silicon substrate, a second lower surface dielectric layer and a second upper surface dielectric layer, wherein the second lower surface dielectric layer and the second upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the second silicon substrate; the top plate chip further comprises a second hollowed-out area penetrating through the second silicon substrate and the dielectric layer on the lower surface of the second silicon substrate, and a second observation window located on the etched second dielectric layer on the upper surface is constructed.
2. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization according to claim 1, wherein the sample and/or the catalyst is/are placed on the upper surface of the substrate chip and covers the substrate chip heating electrode, the upper surface of the top plate chip faces the substrate chip, the first hollow area and the second hollow area correspond to each other in a direction perpendicular to the surface of the first silicon substrate, the edge at the junction of the top plate chip and the substrate chip is bonded by the adhesive, a closed microcavity is formed between the upper surface of the top plate chip and the substrate chip, and the sample and/or the catalyst is/are located in the closed microcavity.
3. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization of claim 1, wherein the substrate chip heating electrode is located around the substrate chip electric field electrode.
4. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization of claim 1, wherein the substrate chip heating electrode comprises a first substrate chip heating electrode and a second substrate chip heating electrode, the area where the first substrate chip heating electrode is located is a high temperature heating area, the area where the second substrate chip heating electrode is located is a temperature control area, and the second substrate chip heating electrode is arranged around the substrate chip electric field electrode.
5. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization according to claim 1, wherein the substrate chip electric field electrode comprises two parallel plates, the two plates have the same structure, and the surfaces of the plates are stepped.
6. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization according to claim 2, wherein the adhesive material is epoxy, silver paste, ITO, indium or vacuum silicone grease.
7. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization of claim 1, wherein the first lower surface dielectric layer, the first upper surface dielectric layer, the second lower surface dielectric layer, and the second upper surface dielectric layer are all silicon oxide SiO 2 Silicon carbide SiC, silicon nitride Si 3 N 4 Alumina Al 2 O 3 An insulating material of any one or more combination of materials.
8. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization of claim 1, wherein the substrate chip contact electrode, the substrate chip heating electrode, and the substrate chip electric field electrode material are any one or more of nickel, gold, copper, platinum, aluminum, tungsten, polysilicon, and doped silicon.
9. The thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization according to claim 1, wherein the substrate chip isolation layer material is nickel, gold, copper, platinum, aluminum, tungsten, polysilicon, silicon oxide SiO 2 Silicon carbide SiC, silicon nitride Si 3 N 4 Alumina Al 2 O 3 Any one or more of the combinations of one or more of the above.
10. A method of fabricating a thermally and electrically coupled sealed cavity chip for transmission electron microscope characterization as defined in claim 1, comprising the steps of:
step 1, preparing a substrate chip
Step 1.1, depositing a first upper surface dielectric layer on the upper surface of a first silicon substrate, and depositing a first lower surface dielectric layer on the lower surface of the first silicon substrate;
step 1.2, depositing a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolation layer on the first upper surface dielectric layer;
step 1.3, forming a first hollowed-out area penetrating through a first lower surface dielectric layer and a first silicon substrate on the lower surface of the first silicon substrate; the first upper surface medium layer adjacent to the first hollowed-out area is a first observation window;
step 2, preparing a top plate chip
Step 2.1, depositing a second upper surface dielectric layer on the upper surface of a second silicon substrate, and depositing a second lower surface dielectric layer on the lower surface of the second silicon substrate;
step 2.2, etching the second lower surface dielectric layer to form a second observation window; forming a second hollow area penetrating through the second lower surface dielectric layer and the second silicon substrate on the lower surface of the second silicon substrate;
placing a sample or/and a catalyst on the surface of the substrate chip, and covering the substrate chip heating electrode;
step 3, bonding the substrate chip and the top plate chip
The first observation window and the second observation window are aligned, and the edge of the junction of the top plate chip and the substrate chip is coated with adhesive for bonding, so that the substrate chip and the top plate chip are bonded.
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| JP2020177915A (en) * | 2019-04-22 | 2020-10-29 | 国立大学法人電気通信大学 | Microscopic observation cell, and manufacturing method of microscopic observation cell |
| CN112837984A (en) * | 2021-01-06 | 2021-05-25 | 东南大学 | Double-temperature-zone sealed cavity chip suitable for transmission electron microscope characterization and manufacturing method thereof |
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| JP2020177915A (en) * | 2019-04-22 | 2020-10-29 | 国立大学法人電気通信大学 | Microscopic observation cell, and manufacturing method of microscopic observation cell |
| CN112837984A (en) * | 2021-01-06 | 2021-05-25 | 东南大学 | Double-temperature-zone sealed cavity chip suitable for transmission electron microscope characterization and manufacturing method thereof |
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