CN114758939A - Thermal and electric field coupling type sealing cavity chip for transmission electron microscope characterization and manufacturing method thereof - Google Patents
Thermal and electric field coupling type sealing cavity chip for transmission electron microscope characterization and manufacturing method thereof Download PDFInfo
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- CN114758939A CN114758939A CN202210378551.6A CN202210378551A CN114758939A CN 114758939 A CN114758939 A CN 114758939A CN 202210378551 A CN202210378551 A CN 202210378551A CN 114758939 A CN114758939 A CN 114758939A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
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Abstract
The invention discloses a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization and a manufacturing method thereof, wherein the chip comprises a substrate chip and a top plate chip, wherein the substrate chip comprises a first silicon substrate, dielectric layers on the upper surface and the lower surface of the first silicon substrate, a contact electrode, a heating electrode, an electric field electrode and an isolation layer, wherein the contact electrode, the heating electrode, the electric field electrode and the isolation layer are deposited on the dielectric layer on the upper surface; manufacturing a first observation window on the substrate chip; the top plate chip comprises a second silicon substrate, medium layers on the upper surface and the lower surface of the second silicon substrate, and a second observation window on the top plate chip. And placing the sample in an observation window area of the substrate chip, bonding the substrate chip and the top plate chip, and placing the substrate chip and the top plate chip into a matched transmission electron microscope sample rod for use. The invention can heat the sample in the sealed cavity, can synchronously apply an additional electric field locally, and is beneficial to observing the dynamic growth process of the material under the induction of the electric field in real time in the in-situ characterization process of the transmission electron microscope.
Description
Technical Field
The invention belongs to the field of electron microscopy, micro-nano processing and MEMS (micro-electromechanical systems) devices, and particularly relates to a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization.
Background
A Transmission Electron Microscope (TEM) is a tool that uses a high-energy Electron beam accelerated at high pressure as an imaging light source to realize microscopic imaging of a sample in a range from atomic scale to micrometer scale by using an Electron beam penetrating through the sample. The characterization based on the transmission electron microscope is an important material characterization technology, and the in-situ characterization is a characterization method for observing the growth of a material sample or the structure evolution process in the chemical and physical reaction process under the atomic scale in real time through the transmission electron microscope.
Because the chamber of the transmission electron microscope is usually in a high vacuum environment (the vacuum degree is usually less than 10)-4Pa) and therefore the introduction of gas and thermal/electric field environments into transmission electron microscopy is often difficult, often requiring complex gas differencing structures or specially tailored sample rod attachments. This makes it very difficult to observe the dynamic growth process of the material in a transmission electron microscope and the process of the failure evolution under the working conditions. Although the transmission electron microscope (ETEM) technology and the gas sample rod technology (the Protochips and the DENSSolutions in the netherlands) have been developed internationally, the two schemes have the characteristics of complex structure, high cost and the like, and a certain gas environment can be introduced. In contrast, a gas, electricity and thermal coupling type chip structure which is simple in structure, low in cost and convenient to use is developed, is suitable for transmission electron microscope representation, and has important significance for researching growth and evolution mechanisms of materials under atmosphere.
The MEMS (Micro-Electro-Mechanical Systems) processing technology is a technology for Micro-processing materials by means of chemical corrosion and the like in nano and micron scales, can be compatible with the traditional IC technology, and is widely applied to processing of various electronic devices and material structures. MEMS processing techniques can be divided into bulk micromachining and surface micromachining techniques. The bulk micromachining technology mainly uses deep silicon etching, chemical etching and other technologies to perform three-dimensional machining on materials, and the surface micromachining technology is a machining technology based on a thin film structure.
The in-situ chip which simultaneously has the closed microcavity, the heating electrode and the electric field electrode is processed and manufactured through the MEMS technology, the in-situ chip is matched with a transmission electron microscope sample rod to be used for providing a place for bearing and chemically growing a sample, an electric field can be introduced while heating, electric field environments with different degrees are applied to the material, the process of structure evolution in chemical reaction can be observed at an atomic scale, and the in-situ chip is a technical scheme which can realize the growth of the material in different working condition environments, the low cost of the evolution and the convenience. In order to meet the requirement of high-resolution observation of a transmission electron microscope and avoid the safety risk caused by directly using an external gas source, the in-situ chip needs to meet the following conditions: (1) two separate heating zones, one for solid source heating evaporation and the other for temperature control of the reaction zone and temperature differential with the other heating zone to allow the flow of the evaporation gas to the reaction zone. (2) The film thickness at the window for transmission electron microscopy needs to meet the requirements for high resolution imaging by transmission electron microscopy. (3) The relatively closed microcavities serve to restrict gas flow. (4) And the sample rod is matched to carry out an external port for controlling the measuring circuit. (5) And the observation window area needs to be provided with an electrode pair for realizing local electric field loading, so that the growth process of the material in the electric field can be observed conveniently.
At present, no in-situ chip product with a closed micro-cavity, two discrete heating sources and an external multi-field strong electric field is arranged on the market, so that the heating of a sample in the closed cavity and the external multi-field strong electric field can be realized, the complex processes of growth and reaction of materials under the induction of an electric field can be observed in real time in the in-situ characterization process of a transmission electron microscope, and the market vacancy is filled.
Disclosure of Invention
The technical problem is as follows: the invention aims to provide a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization and a manufacturing method thereof. The chip can provide a high-pressure atmosphere reaction environment for the material, provide conditions for complex processes such as material growth, and can induce material change through an electric field. Meanwhile, a process flow method for batch manufacturing of chips is provided.
The technical scheme is as follows: in order to achieve the purpose, the invention discloses a thermal and electric field coupling type sealed cavity chip for transmission electron microscope representation, which comprises a substrate chip and a top plate chip;
the substrate chip comprises a first silicon substrate, a first lower surface dielectric layer, a first upper surface dielectric layer, a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolating layer;
the first lower surface dielectric layer and the first upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the first silicon substrate; the substrate chip contact electrode, the substrate chip heating electrode, the substrate chip electric field electrode and the substrate chip isolating layer are respectively positioned on the surface of the first upper surface dielectric layer; the substrate chip contact electrode is respectively connected with the substrate chip heating electrode and the substrate chip electric field electrode and used for electric introduction;
the substrate chip also comprises a first hollow area penetrating through the first silicon substrate and the first lower surface dielectric layer, and the first upper surface dielectric layer positioned on the first hollow area is used as a first observation window; the first hollow-out area covers the first observation window area, and the areas where the substrate chip heating electrode and the substrate chip electric field electrode are located correspond to the area where the first observation window is located;
the substrate chip isolation layer is used for preventing the loss of the sublimation gas and supporting the top plate chip;
the top plate chip comprises a second silicon substrate, a second lower surface dielectric layer and a second upper surface dielectric layer, wherein the second lower surface dielectric layer and the second upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the second silicon substrate; the top plate chip also comprises a second hollow-out area which penetrates through the second silicon substrate and the lower surface dielectric layer of the second silicon substrate, and the second upper surface dielectric layer is etched to construct a second observation window;
further, the substrate chip heating electrode is positioned around the substrate chip electric field electrode.
The sample or/and the catalyst are placed on the upper surface of the substrate chip and cover the substrate chip heating electrode, the upper surface of the top plate chip faces the substrate chip, the first hollow area and the second hollow area correspond to each other in the direction perpendicular to the surface of the first silicon substrate, the edge of the junction of the top plate chip and the substrate chip is bonded through an adhesive, a closed microcavity is formed between the upper surface of the top plate chip and the substrate chip, and the sample or/and the catalyst are located in the closed microcavity. The adhesive material is epoxy resin, silver adhesive, ITO, indium or vacuum silicone grease.
Furthermore, the substrate chip heating electrodes comprise a first substrate chip heating electrode and a second substrate chip heating electrode, the area where the first substrate chip heating electrode is located is a high-temperature heating area, the area where the second substrate chip heating electrode is located is a temperature control area, and the second substrate chip heating electrode is arranged around the substrate chip electric field electrode.
Furthermore, the substrate chip electric field electrode comprises two polar plates which are arranged in parallel, the two polar plates have the same structure, the surfaces of the polar plates are in a step shape, so that the distance between the two polar plates is ensured to have a plurality of values, and different distances correspond to different electric fields; thereby realizing the growth of the material under different electric field inducements. Three different distances are arranged between the two parallel polar plates.
Furthermore, the first lower surface dielectric layer, the first upper surface dielectric layer, the second lower surface dielectric layer and the second upper surface dielectric layer are all silicon oxide SiO2Silicon carbide SiC and silicon nitride Si3N4Aluminum oxide Al2O3The dielectric layer of the insulating material may be 200nm or less.
Further, the substrate chip contact electrode, the substrate chip heating electrode and the substrate chip electric field electrode are made of any one or a combination of nickel, gold, copper, platinum, aluminum, tungsten, polycrystalline silicon and doped silicon, and the thickness of the electrode can be set to be less than 100nm according to requirements.
Further, the substrate chip isolation layer is made of nickel, gold, copper, platinum, aluminum, tungsten, polysilicon, silicon oxide SiO2Silicon carbide SiC and silicon nitride Si3N4Aluminum oxide Al2O3And (3) any one or more combinations thereof, wherein the thickness is 100nm or less in accordance with the electrode thickness.
A manufacturing method of a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization is characterized by comprising the following steps:
Step 1.1, depositing a first upper surface dielectric layer on the upper surface of a first silicon substrate, and depositing a first lower surface dielectric layer on the lower surface of the first silicon substrate;
step 1.2, depositing a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolation layer on the first upper surface dielectric layer;
step 1.3, forming a first hollow-out area penetrating through the first lower surface dielectric layer and the first silicon substrate on the lower surface of the first silicon substrate; the first upper surface dielectric layer adjacent to the first hollow-out area is used as a first observation window;
Step 2.1, depositing a second upper surface dielectric layer on the upper surface of a second silicon substrate, and depositing a second lower surface dielectric layer on the lower surface of the second silicon substrate;
step 2.2, etching the upper surface of the dielectric layer on the second lower surface to form a second observation window; forming a second hollow-out area penetrating through the second lower surface dielectric layer and the second silicon substrate on the lower surface of the second silicon substrate; the position of the second observation window corresponds to the second hollow-out area;
and placing the sample or/and the catalyst on the surface of the substrate chip to cover the substrate chip heating electrode.
And aligning the first observation window and the second observation window, coating adhesive on the edge of the junction of the top plate chip and the substrate chip for adhesion, and adhering the substrate chip and the top plate chip.
Has the advantages that:
the invention provides a thermal and electric field coupling type sealed cavity chip suitable for transmission electron microscope characterization and a manufacturing method thereof.A microcavity for reaction, two discrete heating regions and three discrete electric field regions are provided in a transmission electron microscope, and the operations of independent temperature control, external application of electric fields with different field strengths and the like can be realized. Utilize above-mentioned structure heating, plus electric field in the sealed chamber, can realize the atomic level real-time observation of complicated reaction processes such as nano-material growth simultaneously in transmission electron microscope to can observe the influence of different electric field strengths to the reaction, through the observation to its structure evolution, provide powerful support for the reaction mechanism of research this process, and then can effectively regulate and control nanostructure reaction and growth, have important meaning to electron microscopy research.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a top board chip according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a substrate chip according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a structure for bonding a substrate chip and a top plate chip
Fig. 4 is a schematic diagram of an enlarged structure of the upper surface of the substrate chip.
Fig. 5 is a partial enlarged view of the substrate-chip heating electrode and the substrate-chip electric field electrode located in the observation window region.
The figure shows that: 1. a first silicon substrate; 2. a first lower surface dielectric layer; 3. a first upper surface dielectric layer; 4. a substrate chip contact electrode; 5. a substrate chip heating electrode; 51. a first substrate chip heating electrode; 52. a second substrate chip heating electrode; 6. a substrate chip electric field electrode; 7. a substrate chip isolation layer 8 and a first hollow area; 9. a second silicon substrate; 10. a second lower surface dielectric layer; 11. a second upper surface dielectric layer; 12. a second hollowed-out area; 13. a binder; 14. a first viewing window; 15. a second viewing window.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A thermal and electric field coupling type sealing cavity chip for transmission electron microscope representation comprises a substrate chip and a top plate chip;
as shown in fig. 2, the substrate chip includes a first silicon substrate 1, a first lower surface dielectric layer 2, a first upper surface dielectric layer 3, a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7; the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are respectively positioned on the lower surface and the upper surface of the first silicon substrate 1; the substrate chip contact electrode 4, the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip isolation layer 7 are respectively positioned on the surface of the first upper surface dielectric layer 3; as shown in fig. 4, the substrate chip contact electrode 4 is connected to the substrate chip heating electrode 5 and the substrate chip electric field electrode 6, respectively, for electrical introduction.
The substrate chip further comprises a first hollowed-out area 8 penetrating through the first silicon substrate 1 and the first lower surface dielectric layer 2, the first upper surface dielectric layer 3 adjacent to the first hollowed-out area 8 is a first observation window 14, and the first hollowed-out area 8 covers the area where the first observation window 14 is located. The areas of the substrate chip heating electrode 5 and the substrate chip electric field electrode 6 correspond to the area of the first observation window 14.
As shown in fig. 5, the substrate chip heating electrode 5 includes a first substrate chip heating electrode 51 and a second substrate chip heating electrode 52, the area where the first substrate chip heating electrode 51 is located is a high temperature heating area, and the second substrate chip heating electrode 52 is disposed around the substrate chip electric field electrode 6 for heating and evaporating the sample, and is used for temperature-controlled growth of the material under the induction of the electric field. The sample is heated and sublimated by the first chip heating electrode 51 and then is diffused to the temperature control area, so that the growth of the sample is observed under the condition of electrical and thermal coupling.
The substrate chip electric field electrode 6 comprises two polar plates which are arranged in parallel, the two polar plates have the same structure, the surfaces of the polar plates are in a step shape, so that the distance between the two polar plates is ensured to have a plurality of numerical values, and different distances correspond to different electric fields; thereby realizing the growth of the material under different electric field inducements. As shown in fig. 5, there are three values of the spacing between the two parallel plates in fig. 5.
The substrate chip isolation layer 7 is used to prevent sublimation gas from running off and support the top plate chip.
As shown in fig. 1, the top plate chip includes a second silicon substrate 9, a second lower surface dielectric layer 10 and a second upper surface dielectric layer 11, where the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are respectively located on the lower surface and the upper surface of the second silicon substrate 9; the top plate chip further comprises a second hollow-out area 12 penetrating through the second silicon substrate 9 and the lower surface dielectric layer of the second silicon substrate 9, the second upper surface dielectric layer 11 is etched to construct a second observation window 15, and the second hollow-out area 12 covers the area where the second observation window 15 is located.
Placing a sample or/and a catalyst on the surface of a substrate chip, covering a first substrate chip heating electrode 51 for heating the sample or/and the catalyst, wherein the upper surface of a top plate chip is opposite to the substrate chip, as shown in fig. 2, a first observation window 14 and a second observation window 15 are aligned, and an adhesive 13 is coated on the edge of the junction of the top plate chip and the substrate chip for adhesion, so that the sample or/and the catalyst are in a closed microcavity, and a first hollow-out area 8 and a second hollow-out area 12 correspond to each other in a direction perpendicular to the surface of the first silicon substrate 1. The adhesive 13 is made of epoxy resin, silver adhesive, ITO, indium or vacuum silicone grease.
The first lower surface dielectric layer 2, the first upper surface dielectric layer 3, the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are all silicon oxide SiO2Silicon carbide SiC and silicon nitride Si3N4Aluminum oxide Al2O3The dielectric layer of the insulating material can be 200nm or less.
The substrate chip contact electrode 4, the substrate chip heating electrode 5 and the substrate chip electric field electrode 6 are made of any one or a combination of nickel, gold, copper, platinum, aluminum, tungsten, polycrystalline silicon and doped silicon, and the thickness of the electrodes can be set to be less than 100nm according to requirements.
The substrate chip isolation layer 7 is made of nickel, gold, copper, platinum, aluminum, tungsten, polysilicon, silicon oxide SiO2Silicon carbide SiC and silicon nitride Si3N4Aluminum oxide Al2O3And (3) any one or more combinations thereof, wherein the thickness is 100nm or less in accordance with the electrode thickness.
A manufacturing method of a thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization comprises the following steps:
Step 1.1, depositing a first upper surface dielectric layer 3 on the upper surface of a first silicon substrate 1, and depositing a first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
step 1.2, depositing a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3;
step 1.3, forming a first hollow-out area 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1 on the lower surface of the first silicon substrate 1; the first top dielectric layer 3 adjacent to the first hollow-out region 8 is a first viewing window 14.
Step 2.1, depositing a second upper surface dielectric layer 11 on the upper surface of a second silicon substrate 9, and depositing a second lower surface dielectric layer 10 on the lower surface of the second silicon substrate 9;
step 2.2, etching the upper surface of the second silicon substrate 9 to form a second observation window 15; forming a second hollow-out area 12 penetrating through the dielectric layer on the lower surface of the second silicon substrate 9 and the second silicon substrate 9 on the lower surface of the second silicon substrate 9;
the sample and/or the catalyst are placed on the surface of the substrate chip, covering the first substrate chip heating electrode 51.
The first viewing window 14 and the second viewing window 15 are aligned, and the adhesive 13 is coated on the edge of the interface between the top plate chip and the substrate chip to adhere the substrate chip and the top plate chip.
In the following, the material composition of the respective portions of the substrate chip and the top board chip, the size range and the material composition of the adhesive 13 are illustrated, it should be noted that the following are only specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can understand that the modifications or substitutions are included in the scope of the present invention, and therefore, the scope of the present invention should be subject to the protection scope of the claims.
Example 1
A thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization is shown in fig. 1 and 2 and comprises a substrate chip and a top plate chip.
The substrate chip comprises a first silicon substrate 1, a first lower surface dielectric layer 2, a first upper surface dielectric layer 3, a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolating layer 7; the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are respectively positioned on the lower surface and the upper surface of the first silicon substrate 1; the substrate chip contact electrode 4, the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip isolation layer 7 are respectively positioned on the surface of the first upper surface dielectric layer 3;
the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are made of silicon nitride and have the thickness of 100 nm;
the substrate chip contact electrode 4, the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip isolation layer 7 are made of gold and have the thickness of 100 nm;
the substrate chip further comprises a first hollow-out area 8 penetrating through the first silicon substrate 1 and the first lower surface dielectric layer 2, the first upper surface dielectric layer 3 adjacent to the first hollow-out area 8 is a first observation window 14, and the first hollow-out area 8 covers the area where the first observation window 14 is located.
The top plate chip comprises a second silicon substrate 9, a second lower surface dielectric layer 10 and a second upper surface dielectric layer 11, wherein the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are respectively positioned on the lower surface and the upper surface of the second silicon substrate 9; the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are made of silicon nitride and have the thickness of 200 nm;
and constructing a second hollow-out area 12 penetrating through the second silicon substrate 9 and the lower surface dielectric layer of the second silicon substrate 9, etching the second upper surface dielectric layer 11 to construct a second observation window 15, and covering the area where the second observation window 15 is located by the second hollow-out area 12.
As shown in fig. 3, the first hollow-out area 8 and the second hollow-out area 12 correspond to each other in a direction perpendicular to the surface of the first silicon substrate 1, and cover the first observation window 14 and the second observation window 15 between the electric field electrode and the heating electrode.
The top plate chip is brought into contact with the substrate chip with the first viewing window 14 and the second viewing window 15 aligned, and an adhesive 13 is applied to the edge where the top plate chip and the substrate chip are interfaced.
The manufacturing method of the thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization specifically comprises the following steps:
Step 1.1, depositing a first upper surface dielectric layer 3 on the upper surface of a first silicon substrate 1, and depositing a first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
specifically, a Low Pressure Chemical Vapor Deposition (LPCVD) is used to form an upper surface dielectric layer on the upper surface of the first silicon substrate 1 and a first lower surface dielectric layer 2 on the lower surface, wherein the material is silicon nitride Si3N4The thickness is 100 nm.
Step 1.2, depositing a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3;
specifically, patterns of a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 are formed on the first upper surface dielectric layer 3 by using a metal Lift-off (Lift-off) process, the material is gold, the thickness of the patterns is 100nm, and the substrate chip isolation layer 7 is not in contact with the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip contact electrode 4, so that a circuit short circuit is avoided.
Step 1.3, forming a first hollow-out area 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1 on the lower surface of the first silicon substrate 1;
specifically, the first silicon substrate 1 and the first lower surface dielectric layer 2 are wet-etched by using a potassium hydroxide etching solution to form a first hollow-out region 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1.
Step 2.1, depositing a second upper surface dielectric layer 11 on the upper surface of a second silicon substrate 9, and depositing a second lower surface dielectric layer 10 on the lower surface of the second silicon substrate 9;
specifically, a dielectric layer on the upper surface of the second silicon substrate 9 is formed on the upper surface of the second silicon substrate 9 by Low Pressure Chemical Vapor Deposition (LPCVD), and a dielectric layer on the lower surface of the second silicon substrate 9 is formed on the lower surface of the second silicon substrate 9 and is made of silicon nitride Si3N4And the thickness is 200 nm.
And 2.2, etching the upper surface of the second silicon substrate 9 to form a second observation window 15, specifically, forming the second observation window 15 on the upper surface of the second silicon substrate 9 by using Reactive Ion Etching (RIE), wherein the etching depth is 100 nm.
Forming a second hollow-out area 12 penetrating through the dielectric layer on the lower surface of the second silicon substrate 9 and the second silicon substrate 9 on the lower surface of the second silicon substrate 9; specifically, the second silicon substrate 9 and the second lower surface dielectric layer 10 are wet-etched by using a potassium hydroxide etchant to form a second hollow-out region 12 penetrating through the second lower surface dielectric layer 10 and the second silicon substrate 9.
The sample and/or the catalyst are placed on the surface of the substrate chip, covering the first substrate chip heating electrode 51.
The substrate chip is opposed to the top plate chip upper surface such that the first and second viewing windows 14 and 15 are aligned, and an adhesive 13 is applied to the edge of the substrate chip at the interface with the top plate chip for adhesion. Specifically, epoxy is applied to the edges of the substrate chip and the top plate chip at their interface.
Example 2
A thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization is shown in figures 1 and 2 and comprises a substrate chip and a top plate chip.
The substrate chip comprises a first silicon substrate 1, a first lower surface dielectric layer 2 positioned on the lower surface of the first silicon substrate 1 and a first upper surface dielectric layer 3 positioned on the upper surface of the first silicon substrate 1; the first lower surface dielectric layer 2 and the first upper surface dielectric layer 3 are made of silicon nitride and have the thickness of 50 nm; a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 are further arranged on the first upper surface dielectric layer 3, the materials are platinum, and the thickness is 100 nm; and constructing a first hollow-out area 8 penetrating through the first silicon substrate 1 and the first lower surface dielectric layer 2, wherein the first hollow-out area 8 covers the first observation window 14.
The top plate chip comprises a second silicon substrate 9, a second lower surface dielectric layer 10 positioned on the lower surface of the second silicon substrate 9 and a second upper surface dielectric layer 11 positioned on the upper surface of the second silicon substrate 9, wherein the second lower surface dielectric layer 10 and the second upper surface dielectric layer 11 are both made of silicon nitride and have the thickness of 100 nm; constructing a second observation window 15 on the upper surface of the second silicon substrate 9; and constructing a second hollow-out area 12 penetrating through the second silicon substrate 9 and the second lower surface dielectric layer 10, wherein the second hollow-out area 12 covers the second observation window 15.
As shown in fig. 3, the first and second hollow-out regions 8 and 12 correspond to each other in a direction perpendicular to the surface of the first silicon substrate 1, and cover the first and second observation windows 14 and 15 between the electric field electrode and the heating electrode.
The top board chip and the substrate chip are brought into contact with the first observation window 14 and the second observation window 15 aligned, and the periphery is adhesively closed with the adhesive 13.
The manufacturing method of the thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization specifically comprises the following steps:
Step 1.1, depositing a first upper surface dielectric layer 3 on the upper surface of a first silicon substrate 1, and depositing a first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
specifically, a first upper dielectric layer 3 is formed on the upper surface of a first silicon substrate 1 and a first lower dielectric layer 2 is formed on the lower surface of the first silicon substrate by Low Pressure Chemical Vapor Deposition (LPCVD), wherein the material is silicon nitride Si3N4And the thickness is 50 nm.
Step 1.2, depositing a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 on the first upper surface dielectric layer 3;
specifically, patterns of a substrate chip contact electrode 4, a substrate chip heating electrode 5, a substrate chip electric field electrode 6 and a substrate chip isolation layer 7 are formed on the first upper surface dielectric layer 3 by using a metal Lift-off (Lift-off) process, the material is platinum, the thickness of the patterns is 100nm, and the substrate chip isolation layer 7 is not in contact with the substrate chip heating electrode 5, the substrate chip electric field electrode 6 and the substrate chip contact electrode 4, so that a circuit short circuit is avoided.
Step 1.3, forming a first hollow-out area 8 penetrating through the first silicon substrate 1 and the first lower surface dielectric layer 2 on the lower surface of the first silicon substrate 1;
specifically, a potassium hydroxide etching solution is used for wet etching to form a first hollow-out region 8 penetrating through the first lower surface dielectric layer 2 and the first silicon substrate 1 on the lower surface of the first silicon substrate 1.
Step 2.1, depositing a second upper surface dielectric layer 11 on the upper surface of a second silicon substrate 9, and depositing a second lower surface dielectric layer 10 on the lower surface of the second silicon substrate 9;
specifically, a second upper dielectric layer 11 is formed on the upper surface and a second lower dielectric layer 10 is formed on the lower surface of the second silicon substrate 9 by using Low Pressure Chemical Vapor Deposition (LPCVD), the material is silicon nitride Si3N4The thickness is 10 nm.
And 2.2, etching a second observation window 15 on the second upper surface dielectric layer 11, and forming a second hollow-out area 12 penetrating through the lower surface dielectric layer of the second silicon substrate 9 and the second silicon substrate 9 on the lower surface of the second silicon substrate 9. The second hollowed-out area 12 covers the second observation window 15.
Specifically, a second observation window 15 is formed on the upper surface of the second silicon substrate 9 by Reactive Ion Etching (RIE), with an etching depth of 50 nm; and (3) etching the second silicon substrate 9 and the second lower surface dielectric layer 10 by using a potassium hydroxide etching solution through a wet process to form a second hollow-out area 12 penetrating through the second lower surface dielectric layer 10 and the second silicon substrate 9.
Placing a sample to be tested or/and a catalyst into a first observation window 14 and a second observation window 15 according to experiment requirements;
The substrate chip is opposed to the top plate chip upper surface such that the first viewing window 14 and the second viewing window 15 are aligned, and the adhesive 13 is applied at the edge where the substrate chip and the top plate chip are interfaced. Specifically, epoxy is applied at the edge where the substrate chip and the top plate chip interface.
Claims (10)
1. A thermal and electric field coupling type sealing cavity chip for transmission electron microscope characterization is characterized by comprising a substrate chip and a top plate chip;
the substrate chip comprises a first silicon substrate, a first lower surface dielectric layer, a first upper surface dielectric layer, a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolating layer;
the first lower surface dielectric layer and the first upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the first silicon substrate; the substrate chip contact electrode, the substrate chip heating electrode, the substrate chip electric field electrode and the substrate chip isolation layer are respectively positioned on the surface of the first upper surface dielectric layer; the substrate chip heating electrode and the substrate chip electric field electrode are respectively connected with respective substrate chip contact electrodes;
the substrate chip also comprises a first hollow area penetrating through the first silicon substrate and the first lower surface dielectric layer, and the first upper surface dielectric layer positioned on the first hollow area is used as a first observation window;
the substrate chip isolation layer is used for preventing the loss of the sublimation gas and supporting the top plate chip;
the top plate chip comprises a second silicon substrate, a second lower surface dielectric layer and a second upper surface dielectric layer, wherein the second lower surface dielectric layer and the second upper surface dielectric layer are respectively positioned on the lower surface and the upper surface of the second silicon substrate; the top plate chip further comprises a second hollow-out area which penetrates through the second silicon substrate and the second silicon substrate lower surface dielectric layer, and a second observation window which is located on the second silicon substrate upper surface dielectric layer in an etching mode is constructed.
2. The chip of claim 1, wherein the sample and/or the catalyst are disposed on an upper surface of the substrate chip and cover the substrate chip heating electrode, an upper surface of the top plate chip faces the substrate chip, the first hollow-out region and the second hollow-out region correspond to each other in a direction perpendicular to a surface of the first silicon substrate, an edge of a boundary between the top plate chip and the substrate chip is bonded by an adhesive, a closed microcavity is formed between the upper surface of the top plate chip and the substrate chip, and the sample and/or the catalyst are located in the closed microcavity.
3. The thermal, electric-field coupling type sealed cavity chip for transmission electron microscope characterization according to claim 1, wherein the substrate chip heating electrode is located around the substrate chip electric-field electrode.
4. The chip of claim 1, wherein the substrate chip heating electrodes comprise a first substrate chip heating electrode and a second substrate chip heating electrode, the first substrate chip heating electrode is located in a high-temperature heating area, the second substrate chip heating electrode is located in a temperature control area, and the second substrate chip heating electrode is disposed around the substrate chip electric field electrode.
5. The chip of claim 1, wherein the substrate chip comprises two parallel plates, the two plates have the same structure, and the surfaces of the plates are stepped.
6. The chip for the thermal and electric field coupling type sealed cavity for characterization of a transmission electron microscope according to claim 2, wherein the adhesive material is epoxy resin, silver paste, ITO, indium or vacuum silicone grease.
7. The chip for the TEM characterization of the thermal and electric field coupling-type sealed cavity according to claim 1, wherein the first lower surface dielectric layer, the first upper surface dielectric layer, the second lower surface dielectric layer and the second upper surface dielectric layer are all SiO2Silicon carbide SiC and silicon nitride Si3N4Aluminum oxide Al2O3An insulating material of any one or combination of materials.
8. The chip of claim 1, wherein the substrate chip contact electrode, the substrate chip heating electrode, and the substrate chip electric field electrode are made of any one or more of nickel, gold, copper, platinum, aluminum, tungsten, polysilicon, and doped silicon.
9. The chip with the sealed cavity for transmission electron microscopy characterization according to claim 1, wherein the substrate chip isolation layer is made of a material selected from the group consisting of Ni, Au, Cu, Pt, Al, W, polysilicon, SiO2Silicon carbide SiC and silicon nitride Si3N4Aluminum oxide Al2O3Any one or more of the combinations of (a).
10. The method for manufacturing the thermal and electric field coupling type sealed cavity chip for transmission electron microscope characterization according to claim 1, comprising the following steps:
step 1, preparing a substrate chip
Step 1.1, depositing a first upper surface dielectric layer on the upper surface of a first silicon substrate, and depositing a first lower surface dielectric layer on the lower surface of the first silicon substrate;
step 1.2, depositing a substrate chip contact electrode, a substrate chip heating electrode, a substrate chip electric field electrode and a substrate chip isolation layer on the first upper surface dielectric layer;
step 1.3, forming a first hollow-out area penetrating through the first lower surface dielectric layer and the first silicon substrate on the lower surface of the first silicon substrate; the first upper surface dielectric layer adjacent to the first hollow-out area is a first observation window;
step 2, preparing a top plate chip
Step 2.1, depositing a second upper surface dielectric layer on the upper surface of a second silicon substrate, and depositing a second lower surface dielectric layer on the lower surface of the second silicon substrate;
step 2.2, etching the second lower surface dielectric layer to form a second observation window; forming a second hollow-out area penetrating through the second lower surface dielectric layer and the second silicon substrate on the lower surface of the second silicon substrate;
placing a sample or/and a catalyst on the surface of a substrate chip, and covering a substrate chip heating electrode;
step 3, bonding the substrate chip and the top plate chip
And aligning the first observation window and the second observation window, coating adhesive on the edge of the junction of the top plate chip and the substrate chip for adhesion, and adhering the substrate chip and the top plate chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116973385A (en) * | 2023-07-31 | 2023-10-31 | 上海迈振电子科技有限公司 | In-situ chip for TEM characterization of magnetic material and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020177915A (en) * | 2019-04-22 | 2020-10-29 | 国立大学法人電気通信大学 | Microscopic observation cell, and manufacturing method of microscopic observation cell |
| CN112837984A (en) * | 2021-01-06 | 2021-05-25 | 东南大学 | Double-temperature-zone sealed cavity chip suitable for transmission electron microscope characterization and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020177915A (en) * | 2019-04-22 | 2020-10-29 | 国立大学法人電気通信大学 | Microscopic observation cell, and manufacturing method of microscopic observation cell |
| CN112837984A (en) * | 2021-01-06 | 2021-05-25 | 东南大学 | Double-temperature-zone sealed cavity chip suitable for transmission electron microscope characterization and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116973385A (en) * | 2023-07-31 | 2023-10-31 | 上海迈振电子科技有限公司 | In-situ chip for TEM characterization of magnetic material and preparation method thereof |
| CN116973385B (en) * | 2023-07-31 | 2024-05-28 | 上海迈振电子科技有限公司 | In-situ chip for TEM characterization of magnetic material and preparation method thereof |
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