CN1147571A - Method of manufacturing silicon wafer - Google Patents
Method of manufacturing silicon wafer Download PDFInfo
- Publication number
- CN1147571A CN1147571A CN96111023A CN96111023A CN1147571A CN 1147571 A CN1147571 A CN 1147571A CN 96111023 A CN96111023 A CN 96111023A CN 96111023 A CN96111023 A CN 96111023A CN 1147571 A CN1147571 A CN 1147571A
- Authority
- CN
- China
- Prior art keywords
- silicon chip
- symmicton
- ion
- anneal
- impurity elimination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 36
- 239000010703 silicon Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 20
- 230000008030 elimination Effects 0.000 claims description 11
- 238000003379 elimination reaction Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000012298 atmosphere Substances 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 10
- 238000005247 gettering Methods 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 238000010521 absorption reaction Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 oxonium ion Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a method of producing high purity silicon wafer, which uses non natural gettering method as ions injection and annealing to obtain high purity silicon wafer with only transitory low temperature annealing treatment.
Description
The present invention relates to a kind of method of making silicon chip, particularly relate to the method that manufacturing can improve the manufacturing silicon chip of silicon purity in the silicon chip.
The semiconducter device more and more miniaturization and integrated that becomes.In order to make MOS transistor, must in silicon chip, form N-type trap and P-type trap.By foreign ion is injected into silicon chip, form N-type trap and P-type trap, then, and by long-time High temperature diffusion technology, the foreign ion that diffusion is injected.But, in above-mentioned technology, because the size of restive each trap can not be made high density integrated circuit having.In order to overcome the problems referred to above, adopt the method that forms unconventional trap.Utilize high-energy, foreign ion is injected in the silicon chip, then,, the foreign ion that has injected is carried out the diffusion of short period of time, form unconventional trap by low temperature diffusion technology.Because annealing time is short, form the size of the easy control trap of technology of unconventional trap.But, because annealing time is short, the impurity elimination district that is difficult to utilize the inherent impurity absorption method to be formed on and forms in the silicon chip.If when not forming the silicon chip manufacturing transistor in impurity elimination district in the employing silicon chip, there is following shortcoming in then this method, promptly is difficult to make the device with high density integrated circuit having, this is because gate oxidation films has rudimentary electrical characteristic and leakage current increase in knot.Therefore, in order to make the high density integrated circuit having of tool, require to utilize the silicon chip of oxygen concn less than 10ppm in 0.3 μ m live width.
Two types of highly purified silicon chips are arranged, their commercializations, a kind of is the MCZ wafer of being made by vertical pulling (Czochralski) growing method (being made by SINETSU Co.), and another kind is the HI-wafer of being made by hydrogen annealing method (being made by TOSHIBA Co.).Can not make the MCZ wafer less than the 10ppm oxygen concn, this is because during crystal growth, can not stop inside to enter oxygen fully.Therefore in order to reduce oxygen and the metal that during crystal growth, enters wherein, require to anneal for a long time at 1100 ℃.Also require the Hi-wafer of in nitrogen atmosphere, at high temperature annealing, the oxygen concn in the wafer is reduced to below the 10ppm.Carry out annealed impurity absorption method cost height in nitrogen atmosphere, this is because it need guarantee that safety prevents the equipment of its distinctive danger, and this method productivity is low, therefore can not commercialization.
The reason that produces the poor efficiency problem is only to utilize the peculiar impurity absorption method of high temperature long term annealing to carry out the manufacturing less than the highly purified silicon chip of 10ppm except that deoxidation and metal ion.
Therefore, the purpose of this invention is to provide a kind of method of making the high purity silicon chip,, only carry out the annealing of low temperature short period of time, may obtain desirable gettering effect by adopting ion implantation and the extrinsic impurity absorption method of annealed.
For achieving the above object, according to a kind of method of making silicon chip of the present invention, comprise the following steps: that forming crystal block by ion implantation technology in silicon chip falls into the district; Annealing silicon wafer makes crystal defect region become Symmicton, and forms the impurity elimination district below Symmicton, removes Symmicton, carries out clean then.
In order to understand feature of the present invention and purpose relatively fully, be described in detail below with reference to accompanying drawing:
Figure 1A represents to illustrate the sectional view of silicon chip of making the method for silicon chip by the present invention to Fig. 1 C.
Similar portions among each figure adopts similar mark.
Be described in detail the present invention below with reference to accompanying drawing.
Figure 1A represents to illustrate the sectional view of silicon chip of making the method for silicon chip by the present invention to Fig. 1 C.
With reference to Figure 1A,, in silicon chip 1, form crystal defect region 2 by foreign ion being injected into the silicon chip 1 of the device that is used for making hope.
In above-mentioned technology, impure ion injection technology is utilized Si at least
+, Ar
+, As
+, F
+, He
+, B
+, P
+, Ge
+, Sb
+, In
+, N
2 +The ion of more than one in the ion adopts 10 to 180KeV energy, and 5.0E14 is to 1.0E16 ion/cm
2Dosage.
With reference to Figure 1B, wherein be formed with the silicon chip 1 of crystal defect region 2 by annealing, make wafer defect layer 2 become Symmicton 2A.During annealing, the oxonium ion and the metal ion that are arranged in silicon chip 1 zone darker than Symmicton 2A are captured, and therefore, form impurity elimination district 3 in Symmicton 2A bottom.
In above-mentioned technology, in constant voltage stove or vacuum oven, such as O
2, N
2+ O
2In Ar atmosphere, under 900-1100 ℃ temperature, carry out anneal, about 1 to 3 hour of time, thus, form highly purified impurity elimination district 3, wherein oxygen concn for example 7 arrives 10ppm less than 10ppm.
Except that above-mentioned technology, such as O
2, N
2+ O
2, in the atmosphere such as Ar, temperature is 1050 ℃ to 1200 ℃, anneals in rapid heating furnace about 10 to 30 minutes, then forming thickness in this case is the impurity elimination district of the high purity concentration of 10 to 30 μ m less than 10ppm.
Referring to Fig. 1 C, remove Symmicton 2A by polished finish, make highly purified silicon chip 10, oxygen concn carries out clean then less than 10ppm in this silicon chip, removes the impurity particle and the polishing slurries that produce during the polished finish.
In above-mentioned technology, should carry out polished finish, remove Symmicton 2A, so that keep the above impurity elimination district 3 of 10 μ m at least.
As mentioned above, the present invention only carries out the anneal of low temperature short period of time by adopting ion implantation and annealed extrinsic impurity absorption method, just obtains desirable gettering effect, thereby can make highly purified silicon chip.
Therefore, the present invention can improve stability and production efficiency, and this is because utilize extrinsic impurity absorption method, can easily obtain highly purified silicon chip, and be difficult to utilize the inherent impurity absorption method to obtain, because anneal in hydrogeneous atmosphere, it can eliminate the danger that brings in the impurity absorption method, and, the present invention can also improve gate oxidation films film quality and the knot in leakage current characteristic, this is because utilize the high purity silicon chip to make device, thus, may make high density integrated circuit having.
As previously mentioned, though special embodiment is narrated, that only is an explanation principle of the present invention.Should understand, the invention is not restricted to the above-mentioned preferred embodiment that discloses and illustrate.Therefore, in scope and spirit essence of the present invention, can do various suitable variations, but they are included in all among the further embodiment of the present invention.
Claims (9)
1. a method of making silicon chip comprises the following steps:
Utilize ion implantation technology in silicon chip, to form crystal defect region;
The described silicon chip of annealing makes crystal defect region become Symmicton, and forms the impurity elimination district below described Symmicton;
Remove described Symmicton, carry out clean then.
2. according to the method for claim 1, it is characterized in that: described ion implantation technology is utilized Si at least
+, Ar
+, As
+, F
+, He
+, B
+, P
+, Ge
+, Sb
+, In
+, N
2 +The ion of more than one in the ion, the energy of employing 10 to 180KeV and 5.0E14 are to 1.0E16 ion/cm
2Dosage.
3. according to the method for claim 1, it is characterized in that: such as O
2, N
2+ O
2, in the atmosphere of Ar, under 900 ℃ to 1100 ℃ temperature, in the constant voltage stove, carried out anneal about 1 to 3 hour.
4. according to the method for claim 1, it is characterized in that: such as O
2, N
2+ O
2, in the atmosphere of Ar, under 900 ℃ to 1100 ℃ temperature, in vacuum oven, carried out anneal about 1 to 3 hour.
5. according to the method for claim 1, it is characterized in that: such as O
2, N
2+ O
2, in the atmosphere of Ar, under 1050 ℃ to 1200 ℃ temperature, anneal is about 10 to 30 minutes in rapid heating furnace.
6. according to the method for claim 1, it is characterized in that: the oxygen concn in described impurity elimination district is 7 to 10ppm.
7. according to the method for claim 1, it is characterized in that: the original depth in the described impurity elimination district that is formed by described anneal is 10 to 30 μ m.
8. according to the method for claim 1, it is characterized in that:, remove described Symmicton by polished finish.
9. according to the method for claim 8, it is characterized in that: carry out described polished finish, keep the above thickness of described impurity elimination district 10 μ m at least.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR17270/95 | 1995-06-24 | ||
| KR1019950017270A KR970003671A (en) | 1995-06-24 | 1995-06-24 | Silicon Wafer Processing Method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1147571A true CN1147571A (en) | 1997-04-16 |
Family
ID=19418158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96111023A Pending CN1147571A (en) | 1995-06-24 | 1996-06-24 | Method of manufacturing silicon wafer |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR970003671A (en) |
| CN (1) | CN1147571A (en) |
| TW (1) | TW345689B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309021C (en) * | 2003-12-25 | 2007-04-04 | 北京有色金属研究总院 | Method for eliminating primary pit defects of silicon monocrystal device making area |
| CN101770942B (en) * | 2008-12-29 | 2011-08-24 | 北大方正集团有限公司 | Method and device for measuring temperature by P-type substrate silicon wafer |
| CN103632956A (en) * | 2012-08-13 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Method for preventing generation of defects in semiconductor product high temperature rapid annealing |
| CN103872180A (en) * | 2014-03-19 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Gettering method through implantation of carbon ions |
| CN104637782A (en) * | 2013-11-14 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN108660513A (en) * | 2017-03-28 | 2018-10-16 | 上海新昇半导体科技有限公司 | A kind of device and method reducing wafer defect |
| CN109524425A (en) * | 2018-10-15 | 2019-03-26 | 上海华虹宏力半导体制造有限公司 | Silicon on insulated substrate and preparation method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100580776B1 (en) * | 1999-11-04 | 2006-05-15 | 주식회사 하이닉스반도체 | Method for gettering of semiconductor device |
| KR100415629B1 (en) * | 2001-08-28 | 2004-01-24 | 프로모스 테크놀로지즈 인코포레이티드 | Method for molecular nitrogen implantation dosage monitoring |
| KR101385810B1 (en) | 2006-05-19 | 2014-04-16 | 엠이엠씨 일렉트로닉 머티리얼즈, 인크. | Controlling agglomerated point defect and oxygen cluster formation induced by the lateral surface of a silicon single crystal during cz growth |
-
1995
- 1995-06-24 KR KR1019950017270A patent/KR970003671A/en not_active Application Discontinuation
-
1996
- 1996-06-22 TW TW085107533A patent/TW345689B/en not_active IP Right Cessation
- 1996-06-24 CN CN96111023A patent/CN1147571A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309021C (en) * | 2003-12-25 | 2007-04-04 | 北京有色金属研究总院 | Method for eliminating primary pit defects of silicon monocrystal device making area |
| CN101770942B (en) * | 2008-12-29 | 2011-08-24 | 北大方正集团有限公司 | Method and device for measuring temperature by P-type substrate silicon wafer |
| CN103632956A (en) * | 2012-08-13 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Method for preventing generation of defects in semiconductor product high temperature rapid annealing |
| CN104637782A (en) * | 2013-11-14 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN103872180A (en) * | 2014-03-19 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Gettering method through implantation of carbon ions |
| CN108660513A (en) * | 2017-03-28 | 2018-10-16 | 上海新昇半导体科技有限公司 | A kind of device and method reducing wafer defect |
| CN109524425A (en) * | 2018-10-15 | 2019-03-26 | 上海华虹宏力半导体制造有限公司 | Silicon on insulated substrate and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970003671A (en) | 1997-01-28 |
| TW345689B (en) | 1998-11-21 |
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C01 | Deemed withdrawal of patent application (patent law 1993) |