CN114747004A - 集成电路封装内插器的背面互连 - Google Patents
集成电路封装内插器的背面互连 Download PDFInfo
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- CN114747004A CN114747004A CN202180006872.7A CN202180006872A CN114747004A CN 114747004 A CN114747004 A CN 114747004A CN 202180006872 A CN202180006872 A CN 202180006872A CN 114747004 A CN114747004 A CN 114747004A
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Abstract
提供了用于形成被配置用于背面附接的集成电路(IC)封装内插器的方法。多孔硅双层形成在体硅晶片上,例如,使用受控阳极化,该多孔硅双层包括具有不同孔隙率的两个多孔硅层。内插器形成在该多孔硅双层上方,该内插器包括背面触点、正面触点和延伸穿过该内插器的导电结构(例如,通孔和金属互连件),以连接所选背面触点与所选正面触点。然后将该结构在该硅双层的第一多孔硅层与第二多孔硅层之间的界面处分割,并且将包括该第二多孔硅层的内插器倒置并蚀刻,以去除该第二硅层并露出该背面触点,使得所露出的背面触点可用于背面附接该内插器与封装基板或其它结构。
Description
相关专利申请
本申请要求于2020年4月23日提交的共同拥有的美国临时专利申请号63/014,667的优先权,该申请的全部内容以引用方式并入本文以用于所有目的。
技术领域
本公开涉及集成电路(IC)封装件,更具体地,涉及用于IC封装内插器的背面键合/互连的系统和方法,例如,在没有硅通孔(TSV)的情况下形成该内插器。
背景技术
摩尔定律的概念已经更多地从纯硅(Si)工艺集成转向了裸片组件和异质裸片集成(即,从每个晶体管的成本转向每个封装晶体管的成本),例如,以便在单个封装件中提供总系统解决方案(TSS)。异质裸片集成的一个示例是多裸片封装组件,包括安装在公共封装件中的多种不同类型的裸片。一些异质多裸片封装件被形成为3维产品或2.5维产品,包括以水平(平坦)取向安装在封装基板上的多个裸片,该封装基板继而可以安装在印刷电路板(PCB)上。在一些封装件中,多个裸片通过互连彼此连接,这些互连形成于设置在裸片与多裸片封装基板之间的“内插器”结构中。例如,图1示出了Xilinx公司和台湾半导体制造有限公司(TSMC)的示例性多裸片FPGA封装件50的剖视图。
FPGA封装件50的剖视图示出了焊接安装在硅内插器56上的FPGA裸片52和存储器裸片54,该硅内插器继而焊接安装在封装基板58上。硅内插器56包括:(a)FPGA 52与存储器54之间的互连60(以及安装在硅内插器56上的其他裸片之间的类似互连),以及(b)“硅通孔”(TSV)62,其垂直延伸穿过内插器56以将FPGA 52和存储器54连接到封装基板58(以及到PCB上的电子器件,多裸片FPGA封装件50通过垂直延伸穿过封装基板58的TSV或其他连接(未示出)安装到该电子器件)。
TSV 62提供内插器56到封装基板58的背面互连。TSV背面互连构造通常昂贵且受制于处理限制和互连节距限制。
TSV背面互连构造的替代方案是互连向下正面(顶侧)引线键合到封装基板。例如,图2A和图2B分别示出了示例性混合取向多裸片(“MOMD”)封装件100的示例性俯视三维视图和示例性侧视图。示例性MOMD封装件100包括安装在水平延伸的内插器(或“裸片安装基座”)104上的多个裸片102。安装在水平延伸的内插器104上的多个裸片102可以包括多种不同类型的裸片以及每种类型裸片的一个或多个实例。此外,多个裸片102可以以至少两个不同取向安装在水平延伸的内插器104上,以限定“混合取向”封装件。例如,如图所示,MOMD封装件100可以包括:(a)水平安装的一个或多个裸片110,作为水平安装式裸片或“HMD”;和(b)垂直安装的一个或多个裸片112,作为垂直安装式裸片或“VMD”。图2A和图2B中所示的示例性MOMD封装件100包括(a)两个HMD 110a和110b以及(b)四个VMD 112a、112b、112c和112d,这四个VMD 112a、112b、112c和112d均安装到内插器104。术语“裸片”和“芯片”在本文中能够互换使用。
内插器104通过引线键合连接120正面安装在封装基板106上,并且封装基板106可以例如通过焊料连接安装到PCB或其它结构。安装在水平延伸的内插器104上的各种裸片102可以通过在水平延伸的内插器104中形成的导电互连彼此连接,并且经由引线键合连接120和垂直延伸穿过封装基板106的导体122连接到下面的PCB(或封装基板106安装到的其它装置)。在2019年8月14日提交的题为“Mixed-Orientation Multi-Die IntegratedCircuit Package with at least one Vertically-Mounted Die”的共同待决的美国专利申请序列号16/540,117中进一步详细地描述MOMD封装件100,该申请的全部内容以引用的方式并入本文以用于所有目的。例如,如所说明的MOMD封装件100中提供的引线键合是成熟的技术,但通常受到电阻和电感相关问题以及与裸片与裸片互连相关的延迟问题的影响。
发明内容
本发明的实施方案提供IC装置和形成IC装置的方法,该IC装置被配置用于在内插器与封装基板(或其它结构)之间进行背面键合或互连。例如,相对于常规硅通孔(TSV)或引线键合连接,一些实施方案提供内插器,该内插器被配置用于背面附接焊球(翻转芯片式)或直接键合(例如,用于高级应用)。相对于大得多且更昂贵的TSV连接,一些实施方案在内插器和封装基板之间提供亚微米背面互连。在一些实施方案中,内插器与封装基板之间的背面互连能够实现比常规附接设计(例如,TSV和引线键合)更高的每区域引脚计数(例如,引脚/mm2)。一些实施方案在IC封装件中提供数千或数万个低延迟背面互连。
一个方面提供了一种形成集成电路(IC)封装内插器的方法,该内插器被配置用于背面附接。该方法包括形成基底硅晶片,该基底硅晶片在体硅区域上方包括多孔硅双层,该多孔硅双层包括具有第一孔隙率的第一多孔硅层,该第一多孔硅层与具有不同于第一孔隙率的第二孔隙率的第二多孔硅层相邻。该方法还包括在多孔硅双层上方形成内插器,包括(a)内插器的背面上的背面触点,(b)内插器的正面上的正面触点;以及(c)导电结构,该导电结构延伸穿过内插器的竖直厚度,以连接所选背面触点与所选正面触点。该方法还包括分割多孔硅双层,以将第一多孔硅层与第二多孔硅层分离,去除分离的第一多孔硅层和体硅区域,并且去除至少第二硅层,以露出背面触点,所露出的背面触点被配置用于附接到封装基板或其它结构。
在一个实施方案中,该方法包括使用所露出的背面触点将IC封装内插器背面安装到封装基板或其它结构。
在一个实施方案中,该方法包括将所露出的背面触点焊接到封装基板或其它结构。
在一个实施方案中,该方法包括将所露出的背面触点直接附接到封装基板或其它结构。
在一个实施方案中,该方法包括将至少一个裸片安装到至少一个正面触点。在一个实施方案中,该方法包括将至少一个裸片安装到至少一个正面触点,并且在分割多孔硅双层之前封装至少一个所安装的裸片。在一个实施方案中,该方法包括在分割多孔硅双层之后将至少一个裸片安装到至少一个正面触点。在一个实施方案中,该方法包括在竖直取向上将至少一个裸片安装到至少一个正面VMD触点,以及在水平取向上将至少一个裸片安装到至少一个正面HMD触点。
在一个实施方案中,分割多孔硅双层以将第一多孔硅层与第二多孔硅层分离,包括使用喷水法来将第一多孔硅层与第二多孔硅层分离。
在一个实施方案中,在分割多孔硅双层之后去除至少第二硅层,包括蚀刻第二硅层,以露出背面触点。
在一个实施方案中,形成内插器包括在背面触点和正面触点之间形成多个通孔和至少一个金属层,以限定背面触点与正面触点之间的导电连接。
另一方面提供了一种形成集成电路(IC)封装内插器的方法,该内插器被配置用于背面附接。在基底硅晶片上执行阳极化工艺,以形成多层硅区域,该多层硅区域包括具有第一孔隙率的第一多孔硅层,该第一多孔硅层与具有不同于第一孔隙率的第二孔隙率的第二多孔硅层相邻。内插器形成在多层硅区域上方,内插器包括内插器的背面上的背面触点、内插器的正面上的正面触点以及导电结构,该导电结构延伸穿过内插器的竖直厚度,以连接所选背面触点与所选正面触点。至少一个裸片安装到正面触点中的至少一个正面触点。分割多层硅区域,以将第一多孔硅层与第二多孔硅层分离。在分割多层硅区域之后,去除至少第二硅层,以露出背面触点,所露出的背面触点被配置用于附接到封装基板或其它结构。
在一个实施方案中,将至少一个裸片安装到正面触点中的至少一个正面触点,包括在竖直取向上将至少一个裸片安装到至少一个正面VMD触点,以及在水平取向上将至少一个裸片安装到至少一个正面HMD触点。
另一方面提供一种集成电路(IC)封装件,包括IC封装基板和内插器。内插器包括内插器的背面上的背面接触焊盘、内插器的正面上的正面接触焊盘以及导电结构,该导电结构延伸穿过内插器的竖直厚度,以连接所选背面接触焊盘与所选正面接触焊盘。至少一个裸片安装到正面接触焊盘。内插器通过背面接触焊盘背面附接到IC封装基板。
在一些实施方案中,内插器不包括晶片基板,并且不包括硅通孔(TSV),不同于常规IC封装内插器。
附图说明
图1示出了示例性常规FPGA封装件的剖视图,该封装件包括安装在包括硅通孔的内插器上的多个半导体裸片,该硅通孔将裸片连接到下面的封装基板;
图2A和图2B分别示出了示例性已知的混合取向多裸片(MOMD)封装件的三维俯视图和侧视图,该MOMD封装件包括(a)水平安装的裸片(HMD)和(b)垂直安装的裸片(VMD);
图4A至图4P示出了根据本发明的一个示例性实施方案的用于构造IC封装内插器的示例性方法,该IC封装内插器被配置用于与封装基板背面附接,在内插器与封装基板之间没有TSV或引线键合连接;
图5A至图5Q示出了根据一个示例性实施方案的用于构造示例性MOMD封装内插器的示例性工艺,该示例性MOMD封装内插器被配置用于与封装基板背面附接,在内插器与封装基板之间没有TSV或引线键合连接;并且
图6A至图6B示出了根据一个示例性实施方案的图5A至图5Q中所示的工艺的替代方案,其中空隙形成于背面接触焊盘中,该背面接触焊盘可以促进接触焊盘与封装基板的焊球附接或直接附接。
具体实施方式
本发明的实施方案提供IC装置和形成IC装置的方法,该IC装置被配置用于在内插器和封装基板(或其它结构)之间进行背面键合/互连。例如,相对于常规硅通孔(TSV)或引线键合连接,一些实施方案提供内插器,该内插器被配置用于背面附接焊球(翻转芯片式)或直接键合(例如,用于高级应用)。相对于大得多且更昂贵的TSV连接,一些实施方案在内插器和封装基板之间提供亚微米背面互连。在一些实施方案中,内插器与封装基板之间的背面互连能够实现比常规附接设计(例如,TSV和引线键合)更高的每区域引脚计数(例如,引脚/mm2)。一些实施方案在IC封装件中提供数千或数万个低延迟背面互连。
一些实施方案提供了一种MOMD封装件,该MOMD封装件具有被配置用于背面附接(也称为“背面附接”或“背面安装”)到封装基板的内插器,例如,上面讨论的图2A至图2B中所示的MOMD封装件100的修改构造,其中相对于正面引线键合,内插器104被配置用于例如通过焊球或直接键合而背面附接到封装基板106。
一些实施方案提供一种形成被配置用于背面附接的内插器的方法,其中该方法利用封装(临时或永久)来提供结构完整性,代替载体晶片。在一些实施方案中,该方法包括执行裸片到晶片键合,然后执行晶片切割。
一些实施方案涉及在硅晶片上构造内插器并且利用晶片分割工艺来去除晶片的体硅部分,之后可以是蚀刻或其它合适的材料去除技术,以露出内插器的背面(底侧)触点(例如,导电焊盘)。然后可以使用所露出的触点来将内插器背面附接到封装基板或其它结构。根据特定实施方案或实施方式,可以在晶片分割工艺之前或之后,或在将内插器安装到封装基板或其它结构之前或之后,将一个或多个裸片安装到内插器(和/或封装在模制化合物中)。
一些实施方案允许在内插器上具有超密闭节距背面互连,没有硅通孔,用于异质裸片集成。
在一些实施方案中,晶片分割工艺可以包含由Canon公司开发的(外延层转移)绝缘体上硅(SOI)技术的方面。例如,一些实施方案提供一种方法,该方法包括:用多层多孔硅(Si)区域构造基底晶片,然后在多孔Si区域上形成背面导电焊盘,并且将裸片(直接或间接)安装在背面焊盘上,然后使用喷水法分割多孔Si层,以分割晶片以及蚀刻/去除剩余的多孔Si,以露出背面焊盘。然后,可以例如通过焊球附接或直接键合,使用背面焊盘将封装件背面安装到基板或其它结构上。
在一些实施方案中,应力消除结构可以构建在内插器中,该内插器具有至少部分开放的空隙,即,不完全填充金属间电介质(IMD)。此外,在一些实施方案中,可以在背面金属接触焊盘中产生空隙,以帮助将内插器焊接和/或直接附接到另一装置。
图3示出了由Canon公司开发的已知工艺300,商业上称为工艺300。在302处提供种子晶片。在304处,例如,通过受控阳极化工艺,在种子晶片上形成双层多孔Si层。在一个实施方式中,阳极化涉及使电流通过HF和乙醇的溶液,单晶种子晶片302作为阳极,以在单晶种子晶片的表面上形成直径为几nm的微观孔,该微观孔的密度为约1011/cm2。可以改变电流密度,以产生具有双层(或其它多层)结构的多孔层,即多孔Si双层。在一个实施方式中,使用低电流密度来形成接近单晶种子晶片的表面的多孔Si的第一层,随后,升高电流密度,以在第一层下方形成不同孔隙率的第二多孔Si层。例如,第二多孔Si层可以含有直径比第一多孔Si层高2倍到3倍的孔。由于界面处的不同孔隙率,第一多孔Si层和第二多孔Si层之间的物理界面(平面界面)具有升高的应力。
在306处,外延Si膜在多孔Si双层上生长,在308处,氧化,以形成氧化硅(SiO2)层。在310处,手柄Si晶片键合到晶片的顶部。然后,在312处,晶片结构在多孔Si双层处分割,例如,使用喷水法在第一多孔Si层与第二多孔Si层之间的界面处分割晶片。在314处,将包括多孔Si双层的第一多孔Si层的手柄晶片翻转,使得第一多孔Si层在顶部。执行蚀刻,以去除第一多孔Si层并露出下面的外延(SOI)膜。在316处,晶片可以退火,例如,通过氢气(H2)退火。可以重新要求和重复使用在312处从手柄晶片分割的原始种子晶片(包括第二多孔Si层)。
本发明的一些实施方案可以包含图3中所示的工艺300或类似的工艺的任何所选步骤或方面。例如,一些实施方案可以包含在304处开始的工艺步骤,即,形成具有不同孔隙率的第一Si层和第二Si层的双层多孔Si层。在以下论文中描述工艺300的额外详细信息:由Yonehara和Sakaguchi在Progress in SOI Structures and Devices Operating atExtreme Conditions中公布的“(SOI-Epi WaferTM)Technology”,第39-86页,2002年,可见https://doi.org/10.1007/978-94-010-0339-1,其全部内容以引用的方式并入本文以用于所有目的。
图4A至图4P示出了根据一个示例性实施方案的用于构造IC封装内插器的示例性工艺,该内插器被配置用于与封装基板背面附接,在内插器与封装基板之间没有TSV或引线键合连接。
首先,如图4A所示,基底硅晶片402由体硅区域上方的双层多孔硅(Si)404构造,例如,根据上文关于图3讨论的工艺300。双层多孔Si404可以包含具有不同孔隙率测量值的两层多孔硅,表示为(a)具有孔隙率X的Si层410和(b)具有孔隙率Y的Si层412,其限定Si层410与具有升高的应力水平的Si层412之间的平面界面414,这有助于Si层410在界面414处与Si层412分离,如下文关于图4M所讨论的。
如图4B所示,介电阻挡层420可以形成在多孔硅双层404上方,特别是在Si层412上方。在示例性实施方案中,介电阻挡层420直接形成在Si层412上。介电阻挡层420可以包括适于防止多孔Si与金属之间的相互作用的任何材料,例如,SiN、SiC或SiO2。随后可以去除介电阻挡层420,如下面关于图4O所讨论的。
如图4C所示,包括一个或多个介电层的介电区域422可以形成在介电阻挡层420上方。例如,介电区域422可以包含SiN、SiO2、SiON、SiC和/或其它合适的介电材料中的任一者的组合。
接下来参考图4D,可以在介电区域422上方形成和图案化光掩模(未示出),并且可以通过光掩模中的开口执行蚀刻,以使用已知的光刻和蚀刻技术在介电区域422中限定各种开口(空隙),这使介电阻挡层420的表面区域露出。蚀刻的介电区域开口可以包含用于形成各种类型的背面结构的开口,例如,用于形成应力消除结构的开口430、用于形成接触焊盘的开口432、用于形成裸片密封元件的开口434、用于形成加强结构的开口、应力消除空隙、焊料辅助空隙和/或用于形成任何其它合适的组件的任何开口。
接下来参考图4E,可以在结构上方沉积阻挡金属,例如,Ta/TaN或Ti/TiN,并且延伸到介电区域开口430、432、434中,以形成覆盖每个介电区域开口内的介电阻挡层420的露出表面区域的阻挡金属层438。然后,可以执行单个镶嵌工艺,以用铜或其它合适的金属填充介电区域开口430、432、434,以限定各种背面(底侧)元件,在该实例中,应力消除结构440、接触焊盘442和裸片密封元件444。可以执行化学机械平坦化(CMP),以去除阻挡金属(例如,Ta/TaN)和填充在介电区域开口430、432、434之外延伸的金属(例如,铜),从而完成单个镶嵌工艺。
如图4F所示,反向钝化区域448可以例如通过沉积氧化物450的混合物而形成,然后是化学机械平坦化(CMP),然后沉积SiON层452。
如图4G所示,可以例如使用铜或钨来形成单个镶嵌深通孔454、456,从而向下形成到在介电区域422中形成的所选背面元件,例如,接触焊盘442和裸片密封元件444。在一些实施方案中,可以形成冗余通孔,以接触公共背面元件(例如,特定接触焊盘442),以提供降低或优化的电阻。
如图4H所示,可以例如使用铝或铜技术形成再分布金属层460(“金属1”层)。再分布金属层460可以包含与如图4G所示形成的通孔454、456接触的金属元件。
如图4I所示,额外的再分布金属层470可以形成在额外介电层(例如,氧化物层和/或低k膜)之间,并且通过延伸穿过介电层的额外单个镶嵌深通孔464、456彼此连接。然后可以在结构顶部上露出的介电层(例如,SiON)468上形成(例如,使用铜或铝)正面(顶侧)焊盘474、476。正面焊盘474、476可以形成为与相应的通孔454、456接触,从而在背面元件(例如,接触焊盘442和裸片密封元件444)与相应的正面焊盘474、476之间提供导电连接。
如上所述,在图4G至图4I中所示的实施方式中,通孔454、456、金属层460、470和正面焊盘474、476可以形成为单个镶嵌结构。在其它实施方案中,这种金属结构中的一个、一些或全部金属结构可以由双镶嵌工艺形成。例如,每个相应金属层460、470或464/476可以使用双镶嵌工艺与下面的通孔454、456一起形成。
如图4J所示,焊料柱478、480可以形成在每个正面焊盘474、476上。
如图4K所示,一个或多个裸片482、484可以通过分别利用焊料柱478、480将每个裸片焊接到所选正面焊盘474、476来安装到内插器。
如图4L所示,包含裸片482、484的晶片可用树脂或其它合适的封装材料486封装,例如,使用任何已知的旋涂、气雾剂或模制技术。在一些实施方案中,封装工艺可以包括底层填料。
如图4M所示,封装结构可以倒置,并且多孔硅双层404可以例如使用上述工艺300来分割。例如,喷水法可以用于将第一多孔Si层410和体Si载体晶片402与第二多孔Si层412分离,例如,通过由第一多孔Si层410和第二多孔Si层412之间的Si孔隙率差限定的升高应力界面414(图4A中示出)促进。在一些实施方案中,在去除基底硅晶片402之后,在图4L处形成的封装486足以物理地支撑在490处指示的其余内插器结构,用于后续处理步骤,而不需要载体晶片或其它物理支撑结构。
如图4N所示,可以去除以及丢弃或再循环通过如上所述的工艺分离的多孔Si层410和体Si载体晶片402。
如图4O所示,其余多孔Si层412可以与下面的介电阻挡层420以及阻挡金属438的上部部分一起蚀刻或以其它方式去除,以露出应力消除结构440、接触焊盘442和裸片密封元件444(统称为背面焊盘)。在去除工艺以露出背面焊盘(即,应力消除结构440、接触焊盘442和裸片密封元件444)之后,内插器490现在被配置用于与封装基板或其它结构背面附接,例如,通过将背面焊盘应力消除结构440、接触焊盘442和裸片密封元件444直接连接到封装基板中的相应结构,或者通过背面焊盘应力消除结构440、接触焊盘442和裸片密封元件444处的焊球附接。
如图4P所示,安装和封装了裸片482、484的内插器结构490可以背面安装到封装基板498,例如,通过将内插器背面焊盘(即,应力消除结构440、接触焊盘442和裸片密封元件444)焊球键合499到设置在封装基板498中的相应焊盘或其它导电结构497。如上所述,内插器结构490不需要TSV。与TSV相比,背面焊盘(即,应力消除结构440、接触焊盘442和裸片密封元件444)的大小可以光刻缩放到比比TSV结构小得多的尺寸。
如上所述,在分割多孔硅双层404之前(图4M),裸片482、484安装到内插器正面触点474(图4K),并且通过封装材料486(图4L)封装。在替代实施方案中,在将裸片482、484安装到内插器正面触点474并且封装所安装的裸片482、484之前,多孔硅双层404可以例如使用本文公开的技术来分割。
图5A至图5Q示出了根据一个示例性实施方案的用于构造示例性混合取向多裸片(MOMD)封装内插器的示例性实施方案,该内插器被配置用于与封装基板背面附接,在内插器与封装基板之间没有TSV或引线键合连接。
首先,如图5A所示,例如,根据上文关于图3讨论的工艺300,在体硅区域上方用双层多孔硅(Si)504构造基底硅晶片502。双层多孔Si 504可以包含具有不同孔隙率测量值的两层多孔硅,表示为(a)具有孔隙率X的Si层510和(b)具有孔隙率Y的Si层512,其限定Si层510与具有升高的应力水平的Si层512之间的平面界面514,这有助于Si层510界面514处与Si层512分离,如下文关于图5M所讨论的。
如图5B所示,介电阻挡层520可以形成在多孔硅双层504上方。介电阻挡层520可以包括适于防止多孔Si与金属之间的相互作用的任何材料,例如,SiN、SiC或SiO2。随后可以去除介电阻挡层520,如下面关于图5P所讨论的。
如图5C所示,衬垫金属叠层523形成在介电阻挡层520上方。在一个实施方案中,形成衬垫金属叠层523可以包括沉积TiN或惰性金属的基底层,然后沉积厚(例如,大于2μm)的铝焊盘。该衬垫金属叠层523也可以用作再分布层,并且可以被图案化,以形成应力消除结构。
如图5D所示,衬垫金属叠层523进行图案化和蚀刻(使用已知金属蚀刻技术),以露出介电阻挡层520的表面区域并形成金属叠层开口530,这些金属叠层开口限定多个离散金属结构,例如,包括一个或多个接触焊盘542、应力消除结构540、裸片密封结构544和/或任何其它类型的金属结构。
接下来参考图5E,可以在结构上方沉积阻挡金属,例如,Ta/TaN或Ti/TiN,并且延伸到金属叠层开口530中,以形成覆盖每个金属叠层开口530内的介电阻挡层520的所露出的表面区域的阻挡金属层538。
在沉积阻挡层538之后,可以形成反向钝化区域548。首先,可以沉积氧化物混合物522,以填充金属结构(例如,接触焊盘542、应力消除结构540和/或裸片密封结构544)之间的金属叠层开口530。在一个实施方案中,选择和/或调谐沉积的氧化物混合物522和沉积工艺,以限定或确保氧化物混合物522的非适形沉积,使得氧化物混合物522填充金属叠层开口530,但不填充相邻应力消除结构540之间的较窄金属叠层开口530,从而限定形成应力消除系统的一部分的开放空隙530A。例如,可以控制沉积室中的沉积速率(例如,高速率)和/或压力(例如,在所选范围内),以限定氧化物混合物522的不流入窄金属叠层开口530的高度非适形沉积。在一些实施方案中,金属叠层开口530(在沉积阻挡层538之后)可以具有小于200nm的开口宽度,例如,在60nm至200nm的范围内,而其它开口530和其余结构(例如,接触焊盘542)可以具有至少1μm的横向宽度,例如,在1μm至100μm的范围内。
在一些实施方案中,氧化物混合物522可以包括SiO2材料的混合物,可以使用等离子体增强CVD(PE-CVD)工艺沉积该混合物,该工艺可以涉及或可以不涉及高密度等离子体(HDP)。在一个示例性实施方案中,可以利用诸如总部在加州圣何塞的Novellus Systems公司和总部在加州菲蒙市的Lam Research公司拥有的表达CVD工艺等工艺。在一些实施方案中,可以调整或优化沉积工艺,以进一步增加沉积的非适形性质,以进一步确保形成开放空隙530A。
在沉积氧化物混合物522之后,可以执行CMP,然后沉积SiON层550,如图5E所示。在一些实施方案中,SiON层550可以较厚,例如,大于2μm,用于低应力和良好的粘附性质。氧化物混合物522和SiON层550的组合形成反向钝化区域548。
如图5E所示,如上所述形成的应力消除结构540和开放空隙530A可以共同限定应力消除系统552。
接下来,如图5F所示,单个镶嵌深通孔554、556可以通过反向钝化区域548形成,例如,使用铜或钨,向下形成到所选背面元件,例如,接触焊盘542和裸片密封元件544。在一些实施方案中,可以形成冗余通孔,以接触公共背面元件(例如,特定接触焊盘542),以提供降低或优化的电阻。
如图5G所示,MOMD封装件的第一金属层560(“金属1”层)可以形成在SiON层550上,例如,使用铝或铜技术。金属1层560可以包含与如图5F所示形成的通孔554、556接触的金属元件。
如图5H所示,可以沉积另外的氧化物层562,然后形成通孔564,并且通过通孔564形成与金属1元件560耦合的正面(顶侧)接触焊盘566A、566B(例如,包括Al-Sn合金)。另外,可以蚀刻至少一个VMD沟槽570,以接收垂直安装的裸片(VMD),如图5J所示。如图所示,VMD沟槽570可以在应力消除系统552上方对准,例如,以管理通过在VMD沟槽570中安装VMD引起的物理应力。在一些实施方案中,可以蚀刻额外的沟槽,例如,用于应力消除结构。
如图5I所示,可以形成、图案化和蚀刻聚酰亚胺层,以限定裸片支撑/引导结构574,该裸片支撑/引导结构被配置为物理地引导将一个或多个裸片安装到MOMD封装内插器和/或一旦安装,就物理地支撑此类裸片。在该示例中,聚酰亚胺结构574限定(a)在VMD沟槽570上方对准的VMD开口576A,以共同限定用于接收VMD的开口和(b)用于接收HMD的HMD开口576B。如图所示,第一正面接触焊盘566A露出在VMD开口576A中,并且第二正面接触焊盘566B露出在HMD开口576B中。
如图5J所示,VMD 580垂直地安装在VMD开口576A中并且向下延伸到VMD沟槽570,使得连接到VMD 580中的电子电路的导电触点580A与第一正面接触焊盘566A接触,该第一正面接触焊盘提供从背面接触焊盘542A到VMD 580中的电子电路的导电连接。另外,HMD582水平安装在HMD开口576B中,使得连接到HMD 582中的电子电路的导电触点582A与第二正面接触焊盘566B接触,该第二正面接触焊盘提供从背面接触焊盘542B到VMD 582中的电子电路的导电连接。在一个实施方案中,底膜585可以沉积在VMD沟槽570和HMD开口576B中,以物理地支撑或缓冲安装的VMD 580和HMD 582。
图5K示出了MOMD封装内插器500的放大晶片水平视图,包括多个VMD 580和HMD582,每个VMD 580和HMD 582通过相应的金属层结构和导电通孔导电地连接到至少一个相应的背面接触焊盘542。
接下来,如图5L所示,包含安装的VMD 580和HMD 582的MOMD封装内插器500可用聚合物或其它合适的封装材料590封装。
如图5M所示,可以例如使用上述工艺300来分割多孔硅双层504。例如,喷水法可以用于将第一多孔Si层510和体Si载体晶片502与第二多孔Si层512分离,例如,通过由第一多孔Si层510和第二多孔Si层512之间的Si孔隙率差限定的升高应力界面514(图5A中示出)促进。
如图5N所示,可以去除、丢弃或再循环通过如上所述的工艺分离的多孔Si层510和体Si载体晶片502。剩余的MOMD封装内插器500可以倒置,使得第二多孔Si层512位于结构的顶部。在一些实施方案中,倒置的MOMD封装内插器500可以安装在载体晶片或其它物理支撑结构上。在其它实施方案中,在图5L处形成的封装590足以物理地支撑剩余的MOMD封装内插器500,用于后续处理步骤,而不需要载体晶片或其它物理支撑结构。
图5O示出了倒置的MOMD封装内插器500的一部分的放大视图,第二多孔Si层512在顶部,如上所述。
如图5P所示,其余多孔Si层512可以与下面的介电阻挡层520以及阻挡金属538的上部部分一起蚀刻或以其它方式去除,以露出背面焊盘,即接触焊盘542、应力消除结构540和/或裸片密封结构544。在去除工艺以露出背面焊盘接触焊盘542、应力消除结构540和/或裸片密封结构544之后,MOMD封装内插器500现在被配置用于与封装基板或其它结构背面附接,例如,通过将背面焊盘(即接触焊盘542、应力消除结构540和/或裸片密封结构544)直接连接到封装基板中的相应结构,或者通过背面焊盘(即接触焊盘542、应力消除结构540和/或裸片密封结构544)处的焊球附接。例如,图5Q示出了形成在连接到VMD 582的所选背面接触焊盘542上的示例性焊球592。
如上所述,在分割多孔硅双层504(图5M)之前,裸片582、584安装到内插器正面接触焊盘566A、566B(图5J),并且通过封装材料590(图5L)封装。在替代实施方案中,在将裸片582、584安装到内插器正面接触焊盘566A、566B并且封装所安装的裸片582、584之前,多孔硅双层504可以例如使用本文公开的技术来分割。
图6A至图6B示出了根据一个示例性实施方案的图5A至图5Q中所示的实施方案的替代方案,其中空隙形成于背面接触焊盘中,该背面接触焊盘可以促进接触焊盘与封装基板的焊球附接或直接附接。图6A示出了MOMD封装内插器600A,类似于上面讨论的MOMD封装内插器500,但是包括在金属部分543之间形成有开放空隙545的背面接触焊盘542'。图6B示出了根据一个示例性实施方式的在背面接触焊盘542'上形成的示例性焊球592。
Claims (14)
1.一种形成被配置用于背面附接的集成电路(IC)封装内插器的方法,所述方法包括:
形成基底硅晶片,所述基底硅晶片在体硅区域上方包括多孔硅双层,所述多孔硅双层包括具有第一孔隙率的第一多孔硅层,所述第一多孔硅层与具有不同于所述第一孔隙率的第二孔隙率的第二多孔硅层相邻;
在所述多孔硅双层上方形成内插器,所述内插器包括:
所述内插器的背面上的背面触点;
所述内插器的正面上的正面触点;以及
导电结构,所述导电结构延伸穿过所述内插器的竖直厚度,以连接所选背面触点与所选正面触点;
分割所述多孔硅双层,以将所述第一多孔硅层与所述第二多孔硅层分离,以及去除所分离的第一多孔硅层和所述体硅区域;以及
在分割所述多孔硅双层之后,去除至少所述第二硅层,以露出所述背面触点,所露出的背面触点被配置用于附接到封装基板或其它结构。
2.一种形成被配置用于背面附接的集成电路(IC)封装内插器的方法,所述方法包括:
在基底硅晶片上执行阳极化工艺,以形成多层硅区域,所述多层硅区域包括具有第一孔隙率的第一多孔硅层,所述第一多孔硅层与具有不同于所述第一孔隙率的第二孔隙率的第二多孔硅层相邻;
在所述多层硅区域上方形成内插器,所述内插器包括:
所述内插器的背面上的背面触点;
所述内插器的正面上的正面触点;以及
导电结构,所述导电结构延伸穿过所述内插器的竖直厚度,以连接所选背面触点与所选正面触点;
将至少一个裸片安装到所述正面触点中的至少一个正面触点上;
分割所述多层硅区域,以将所述第一多孔硅层与所述第二多孔硅层分离;以及
在分割所述多层硅区域之后,去除至少所述第二硅层,以露出所述背面触点,所露出的背面触点被配置用于附接到封装基板或其它结构。
3.根据权利要求1至2中任一项所述的方法,还包括使用所露出的背面触点将所述IC封装内插器背面安装到所述封装基板或其它结构。
4.根据权利要求3所述的方法,还包括将所露出的背面触点焊接到所述封装基板或其它结构。
5.根据权利要求3所述的方法,还包括将所露出的背面触点直接附接到所述封装基板或其它结构。
6.根据权利要求1至5中任一项所述的方法,还包括将至少一个裸片安装到至少一个正面触点。
7.根据权利要求6所述的方法,还包括将所述至少一个裸片安装到所述至少一个正面触点,以及在分割所述多孔硅双层之前封装至少一个所安装的裸片。
8.根据权利要求6所述的方法,还包括在竖直取向取向上将至少一个裸片安装到至少一个正面VMD触点,以及在水平取向取向上将至少一个裸片安装到至少一个正面HMD触点。
9.根据权利要求1至8中任一项所述的方法,其中分割所述多层硅区域或所述多孔硅双层以将所述第一多孔硅层与所述第二多孔硅层分离,包括使用喷水法来将所述第一多孔硅层与所述第二多孔硅层分离。
10.根据权利要求1至9中任一项所述的方法,其中形成所述内插器包括在所述背面触点和所述正面触点之间形成多个通孔和至少一个金属层,以限定所述导电结构,所述导电结构延伸穿过所述内插器的所述竖直厚度,以连接所选背面触点与所选正面触点。
11.一种集成电路(IC)封装件,所述IC封装件包括:
IC封装基板;以及
内插器,所述内插器包括:
所述内插器的背面上的背面接触焊盘;
所述内插器的正面上的正面接触焊盘;以及
导电结构,所述导电结构延伸穿过所述内插器的竖直厚度,以连接所选背面接触焊盘与所选正面接触焊盘;
至少一个裸片,所述至少一个裸片安装到所述正面接触焊盘;
其中所述内插器通过所述背面接触焊盘背面附接到IC封装基板。
12.根据权利要求18所述的IC封装件,其中所述内插器不包括晶片基板。
13.根据权利要求18所述的IC封装件,其中所述内插器不包括硅通孔(TSV)。
14.一种通过根据权利要求1至10中任一项所述的方法形成的集成电路封装件。
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