CN114745072A - Ethernet clock synchronization precision measuring and calculating method, recording medium and system - Google Patents
Ethernet clock synchronization precision measuring and calculating method, recording medium and system Download PDFInfo
- Publication number
- CN114745072A CN114745072A CN202210155899.9A CN202210155899A CN114745072A CN 114745072 A CN114745072 A CN 114745072A CN 202210155899 A CN202210155899 A CN 202210155899A CN 114745072 A CN114745072 A CN 114745072A
- Authority
- CN
- China
- Prior art keywords
- measuring
- measurement
- data
- ethernet
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention belongs to the technical field of network communication, and particularly relates to a method for measuring and calculating the synchronization precision of an Ethernet clock, which comprises the following steps: the synchronous precision measuring and calculating process is divided into a measuring stage and a counting stage; and measuring by adopting an FPGA working mode, and counting by adopting a CPU working mode. The method solves the problems that in the conventional measurement and calculation, the single measurement scale is limited, the measurement universality is poor, the measurement granularity is coarse, and the clock synchronization process cannot be subjected to refined monitoring and backtracking analysis. The invention also provides a non-transient readable recording medium storing the method program and a system comprising the medium, wherein the program can be called by a processing circuit to execute the method.
Description
Technical Field
The invention belongs to the technical field of network communication, and discloses a method for measuring and calculating the synchronization precision of an Ethernet clock, a recording medium and a system which are stored with a program capable of executing the method.
Background
Because the common ethernet has the advantages of wide application, low cost, high communication rate, compatibility and intercommunication with information domains and the like, the common ethernet is widely applied to upper layers of various industrial control systems at present. But the non-scheduling best-effort transmission mechanism of the Ethernet basically has uncertainty in transmission, so that the Ethernet is difficult to be applied to the field of real-time control.
The real-time Ethernet transforms the link layer of the Ethernet, adds a time division multiplexing mechanism based on precise time slot scheduling, and ensures the certainty of the transmission delay of the real-time data frame, thereby leading the real-time Ethernet to have great potential for expanding the real-time control field. At present, the autonomous controllable real-time ethernet technology has received wide attention in the fields of aerospace, ships, industrial control, rail transit, communication and the like. Real-time ethernet has the natural advantages of merging the information domain and the control domain, and is the most potential next-generation control network technology.
The clock synchronization technology is the basis of real-time Ethernet, and the clock synchronization precision directly determines the application boundary of real-time performance. In the design, development, deployment and use of real-time ethernet, it is usually necessary to measure the accuracy of clock synchronization. The traditional measuring method usually uses an oscilloscope or a special network tester, and has the following main disadvantages: firstly, the single measurement scale is very limited, the network with the scale cannot be measured at one time, and the measurement efficiency is low; secondly, the measurement universality is poor, and if a special network tester can only measure a single clock synchronization technology; thirdly, the measurement granularity is coarse, and the fine monitoring and backtracking analysis of the clock synchronization process cannot be carried out.
Disclosure of Invention
Aiming at the problems, the invention provides a method for measuring and calculating the synchronization precision of an Ethernet clock, which comprises the following steps:
s1, decomposing a synchronous precision measuring and calculating process into a measuring stage and a statistical stage;
s2, in the measuring stage, receiving configuration and command information of synchronous precision measurement in an FPGA (field programmable gate array) working mode, carrying out synchronous precision measurement on input multi-channel second pulse data according to the configuration and command information to generate a measuring result, and periodically uploading the synchronous precision measuring result and the working state of the unit; buffering the input original pulse per second data during measurement;
s3, in the statistical stage, a CPU working mode is adopted to realize the issuing of synchronous precision measurement configuration and command information of a user, and a clock synchronous precision measurement result and the working state of a multi-channel clock synchronous precision measurement unit are periodically acquired; and reading and storing original pulse per second data from the multi-channel clock synchronization precision measurement unit, performing statistical analysis, and generating a user-defined refined statistical analysis result.
Preferably, the measurement unit implementing the step S1 and the statistical analysis unit implementing the step S2 perform data interaction via the PCIE bus.
Preferably, the data includes configuration and command information, synchronization result information, operating state information, and pulse-per-second raw data information.
Further, the second pulse original data is subjected to data interaction in a form of direct memory access.
The invention has the beneficial effects that:
1) the multi-channel high-precision real-time Ethernet clock synchronization precision measurement method can greatly improve the single measurement scale of the traditional measurement method, and further greatly improve the measurement efficiency of the synchronization precision.
2) The multi-channel high-precision real-time Ethernet clock synchronization precision measurement method has universality and can be suitable for various real-time Ethernet clock synchronization precision measurements including but not limited to IEEE1588, IEEE1588 v2, AS6802, 802.1AS-Rev and the like.
3) The multichannel high-precision real-time Ethernet clock synchronization precision measurement method can store original second pulse data in an off-line mode, can perform off-line analysis, and provides a basis for fine analysis of a clock synchronization algorithm.
Another aspect of the present invention is to provide a non-transitory readable recording medium storing one or more programs including instructions that, when executed, cause a processing circuit to perform the method for ethernet clock synchronization accuracy estimation.
Another aspect of the present invention is to provide an ethernet clock synchronization accuracy measurement and calculation system, including a processing circuit and a memory electrically coupled to the processing circuit, where the memory is configured to store at least one program, the program includes a plurality of instructions, and the processing circuit runs the program and can execute the ethernet clock synchronization accuracy measurement and calculation method.
Drawings
FIG. 1 is a schematic diagram of a system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a multi-channel pulse-per-second synchronization precision measurement unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a multi-channel pulse-per-second data statistical analysis unit according to an embodiment of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and the described embodiments are some embodiments, but not all embodiments, of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any new work, are within the scope of the present invention.
As shown in FIG. 1, the present invention provides a method for measuring the synchronization accuracy of a real-time Ethernet clock, which comprises a multi-channel pulse-per-second synchronization accuracy measuring unit and a multi-channel pulse-per-second data statistical analysis unit. The method can be used for efficiently measuring the clock synchronization precision of the real-time Ethernet in scale, and simultaneously acquiring and storing the original pulse per second data in the measurement process to perform refined statistical analysis on the clock synchronization.
And the multichannel second pulse synchronous precision measuring unit is used for receiving the configuration and command information of the multichannel second pulse data statistical analysis unit, carrying out synchronous precision measurement on the accessed multichannel second pulse data according to the configuration and command information, generating a measuring result, and periodically uploading the measuring result and the working state of the multichannel second pulse data statistical analysis unit. Meanwhile, in the measuring process, original synchronous pulse per second data are temporarily stored.
And the multichannel second pulse data statistical analysis unit is used for receiving user configuration and command input and sending the user configuration and command input to the multichannel second pulse synchronous precision measurement unit. And periodically acquiring a synchronous precision measurement result and a working state from the multichannel second pulse synchronous precision measurement unit. Meanwhile, original pulse per second data are read and stored from a multichannel pulse per second synchronous precision measuring unit in a Direct Memory Access (DMA) mode, and user-defined statistical analysis is carried out on the original pulse per second data.
As shown in fig. 2, the working flow of the multi-channel pulse-per-second synchronization precision measurement unit is as follows:
the synchronous precision measurement configuration module receives the command and the configuration information of the synchronous precision measurement and sends the command and the configuration information to the synchronous precision measurement module and the pulse per second data recording module. The synchronous precision measurement module takes the pulse per second data received by the pulse per second signal access module as input, and generates a synchronous precision measurement result according to configuration and command information, and the synchronous precision measurement result is continuously updated in the measurement process. And the synchronous precision measurement configuration module periodically acquires a synchronous precision measurement result and the working state of the unit according to the configuration information and uploads the synchronous precision measurement result and the working state to the multichannel second pulse data statistical analysis unit. The pulse per second data recording module takes pulse per second data received by the pulse per second signal access module as input, and buffers the original input data of the pulse per second according to configuration and command information.
As shown in fig. 3, the working flow of the multi-channel pulse-per-second data statistical analysis unit is as follows:
the configuration and command issuing module receives user configuration and command information and issues the command and the configuration information to the multi-channel pulse-per-second synchronous precision measuring unit. The state acquisition module periodically acquires a synchronous precision measurement result and working state information from the multichannel second pulse synchronous precision measurement unit and sends the synchronous precision measurement result and the working state information to the result output module. The pulse per second data reading module periodically reads original pulse per second data from the multichannel pulse per second synchronous precision measuring unit in a DMA mode, and writes the original pulse per second data into the nonvolatile memory through the pulse per second data storage module. And the synchronous statistical analysis module reads the original pulse per second data from the nonvolatile memory, performs offline custom statistical analysis and generates a synchronous statistical analysis result.
Those not described in detail in this specification are within the skill of the art.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computers, usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.), and having computer-usable program code embodied therein.
The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The technical scheme of the invention is that the method steps are compiled into a program and then the program is stored in a hard disk or other non-transient storage media to form the non-transient readable recording medium; the storage medium is electrically connected with a computer processor, and the Ethernet clock synchronization precision measurement and calculation can be completed through data processing, so that the technical scheme of the Ethernet clock synchronization precision measurement and calculation system is formed.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described above, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A method for measuring and calculating the synchronization precision of Ethernet clocks is characterized by comprising the following steps:
s1, decomposing a synchronous precision measuring and calculating process into a measuring stage and a statistical stage;
s2, in the measuring stage, receiving configuration and command information of synchronous precision measurement in an FPGA (field programmable gate array) working mode, carrying out synchronous precision measurement on input multi-channel second pulse data according to the configuration and command information, generating a measuring result, and periodically uploading the synchronous precision measuring result and the working state of the unit; buffering the input original pulse per second data during measurement;
s3, in the statistical stage, a CPU working mode is adopted to realize the issuing of synchronous precision measurement configuration and command information of a user, and a clock synchronous precision measurement result and the working state of a multi-channel clock synchronous precision measurement unit are periodically acquired; and reading and storing original pulse per second data from the multi-channel clock synchronization precision measurement unit, performing statistical analysis, and generating a user-defined refined statistical analysis result.
2. The method for measuring and calculating the synchronization accuracy of the ethernet clocks according to claim 1, wherein the measurement unit implementing the step S1 and the statistical analysis unit implementing the step S2 perform data interaction via the PCIE bus.
3. The method according to claim 2, wherein the data includes configuration and command information, synchronization result information, operating status information, and pulse-per-second raw data information.
4. The method according to claim 3, wherein the raw data of the second pulse is subjected to data interaction in a form of direct memory access.
5. A non-transitory readable recording medium storing one or more programs comprising instructions which, when executed, cause a processing circuit to perform a method for ethernet clock synchronization accuracy measurement according to any one of claims 1-4.
6. An ethernet clock synchronization accuracy measurement system, comprising a processing circuit and a memory electrically coupled thereto, wherein the memory is configured to store at least one program, the program comprises a plurality of instructions, and the processing circuit executes the program to perform an ethernet clock synchronization accuracy measurement method as claimed in claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210155899.9A CN114745072A (en) | 2022-02-21 | 2022-02-21 | Ethernet clock synchronization precision measuring and calculating method, recording medium and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210155899.9A CN114745072A (en) | 2022-02-21 | 2022-02-21 | Ethernet clock synchronization precision measuring and calculating method, recording medium and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114745072A true CN114745072A (en) | 2022-07-12 |
Family
ID=82275503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210155899.9A Pending CN114745072A (en) | 2022-02-21 | 2022-02-21 | Ethernet clock synchronization precision measuring and calculating method, recording medium and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114745072A (en) |
-
2022
- 2022-02-21 CN CN202210155899.9A patent/CN114745072A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3382481B1 (en) | Controller, control program, and control system field | |
| US5896524A (en) | Off-line clock synchronization for multiprocessor event traces | |
| JP6374466B2 (en) | Sensor interface device, measurement information communication system, measurement information communication method, and measurement information communication program | |
| CN107786368B (en) | Abnormal node detection method and related device | |
| TW201342037A (en) | Techniques for generating a trace stream for a data processing apparatus | |
| CN110535551B (en) | Method and system for synchronizing fault recording sampling data in power system | |
| CN110008247A (en) | Abnormal source determines method, apparatus, equipment and computer readable storage medium | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| CN110995388A (en) | Distributed shared clock trigger delay system | |
| CN109388370A (en) | A kind of method and device for realizing First Input First Output | |
| CN105022686A (en) | Method and apparatus for determining CPU occupancy rate of process on android platform | |
| CN114745072A (en) | Ethernet clock synchronization precision measuring and calculating method, recording medium and system | |
| CN107273322B (en) | Parallel data output method and device | |
| CN107003691B (en) | Techniques for synchronously sampling counters based on global clock | |
| CN108599758A (en) | The algorithm and device of high-precision trigger pulse are generated based on GPS | |
| CN106708167A (en) | Clock adjustment method and controller | |
| CN112702231A (en) | Network delay measuring method and system | |
| CN103561360A (en) | Device and method for serially processing cost of OTN | |
| CN115902571B (en) | Quantum measurement and control system and quantum computer | |
| WO2008075702A1 (en) | Signal measuring device, and signal measuring method | |
| CN115629371A (en) | Transmission delay control method, device, controller, chip and ultrasonic system | |
| CN114839905A (en) | Quantum measurement and control method and system | |
| CN114528998A (en) | Multi-board-card signal synchronization method, device and medium for quantum measurement and control system | |
| JP6653088B1 (en) | Industrial equipment data collection system and motor control device | |
| US11581972B1 (en) | Reporting clock value of network interface controller for timing error analysis |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |