CN114743518B - Double-path symmetrical slope type analog pixel driving circuit and driving method thereof - Google Patents

Double-path symmetrical slope type analog pixel driving circuit and driving method thereof Download PDF

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CN114743518B
CN114743518B CN202210517668.8A CN202210517668A CN114743518B CN 114743518 B CN114743518 B CN 114743518B CN 202210517668 A CN202210517668 A CN 202210517668A CN 114743518 B CN114743518 B CN 114743518B
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negative
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slope
analog
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CN114743518A (en
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代永平
代玉
张俊
刘艳艳
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Nankai University
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A dual-path symmetrical slope type analog pixel driving circuit and a driving method thereof belong to the technical field of integrated circuits, and comprise a digital signal latch, a counter, an enabling digital signal comparator, a positive slope signal amplifier, a positive slope signal transmission gate, a pixel positive addressing storage circuit, a positive analog display amplifier, a positive analog display transmission gate, a negative slope signal amplifier, a negative slope signal transmission gate, a pixel negative addressing storage circuit, a negative analog display amplifier, a negative analog display transmission gate, a pixel output electrode circuit, a connected signal wire and a driving method comprising a dual-path symmetrical four-section wave type slope signal.

Description

Double-path symmetrical slope type analog pixel driving circuit and driving method thereof
Technical Field
The invention belongs to the field of silicon-based display chip circuit application of integrated circuit technology, and particularly relates to the field of a double-path symmetrical slope type analog pixel silicon-based display driving circuit.
Background
The technology for manufacturing a single Crystal silicon planar device is respectively fused with active or passive Display technologies such as a Liquid Crystal Display (LCD) technology, an Organic Light-Emitting Diode (OLED) technology and the like to generate various silicon-based displays, for example, a silicon-based-Liquid Crystal-glass sandwich structure device technology generated by combining the Liquid Crystal Display technology. In practice, an electric field is established between the level on the pixel output electrode and the level on the liquid crystal pixel common electrode, so that the level output to the pixel output electrode by each pixel unit circuit on the silicon substrate is modulated, thereby controlling the intensity (gray scale) of the reflected light amplitude by the liquid crystal material to realize image display. (Chris Chinnock. "Microdisplays and Manufacturing Infrastructure matrix at SID2000" Information Display, 9/2000, P18).
In general, a pixel cell circuit of a Chip active addressing matrix is composed of 1N-channel Metal Oxide Semiconductor (NMOS) transistor AND 1 capacitor connected in series (r.ishii, s.katayama, h.oka, s.yamazaki, s.lino "u.efron, i.david, v.silicon nikov, b.ap" a CMOS/LCOS Image transmitter Chip FOR rt Smart applications "[ IEEE transmission semiconductors circuit AND SYSTEMS FOR VIDEO testing technique ], volume 14, no. 2, 2004, month 2, P269), wherein the gate of the NMOS transistor is connected to a row scanner addressing signal output terminal. However, when a single NMOS transistor transmits a high level, not only is there a threshold voltage loss, but also the transient characteristics of the transmission process are not ideal (chen gui lu et al, CMOS integrated circuit design, seian university press, 1999.9, P110).
Disclosure of Invention
The invention provides a two-way symmetrical slope type analog pixel driving circuit which is composed of a digital signal latch, a counter, an enabling digital signal comparator, a positive slope signal amplifier, a positive slope signal transmission gate, a pixel positive addressing storage circuit, a positive analog display amplifier, a positive analog display transmission gate, a negative slope signal amplifier, a negative slope signal transmission gate, a pixel negative addressing storage circuit, a negative analog display amplifier, a negative analog display transmission gate, a pixel output electrode circuit, a display digital signal input bus, a comparator reset signal line, a positive slope signal line, a negative slope signal line, a slope bias voltage supply line, a row addressing signal line, a positive bias voltage supply line, a negative bias voltage supply line, a global positive display positive phase signal line, a global negative slope signal line, a column display positive analog signal line, a column display negative analog signal line, a 2 nd connecting line, a 5 th connecting line, a 6 th connecting line, a reset connecting line and a 1 st control line together and a driving method comprising four sections of slope signals, the driving method comprises a two-way symmetrical four-section wave mode ramp signal and a driving circulation method thereof, the action of addressing and sampling an analog signal level in the same pixel circuit and the action of displaying and driving an output analog signal level are distributed at different time intervals, and the phenomenon of mutual interference of electric signals caused by conflict between the two actions is avoided in time sequence, and can alternately output a pair of analog levels.
The technical scheme of the invention is as follows:
the two-way symmetrical slope type analog pixel driving circuit is composed of a digital signal latch, a counter, an enable digital signal comparator, a positive slope signal amplifier, a positive slope signal transfer gate, a pixel positive addressing storage circuit, a positive analog display amplifier, a positive analog display transfer gate, a negative slope signal amplifier, a negative slope signal transfer gate, a pixel negative addressing storage circuit, a negative analog display amplifier, a negative analog display transfer gate, a pixel output electrode circuit, and a display digital signal input bus, a comparator reset signal line, a positive slope signal line, a negative slope signal line, a slope bias voltage supply line, a row addressing signal line, a positive bias voltage supply line, a negative bias voltage supply line, a global positive display positive phase signal line, a global positive display inverse phase signal line, a global negative display positive phase signal line, a global negative display inverse phase signal line, a column display positive analog signal line, and a column display negative analog signal line, and the positive slope signal line, the positive slope signal amplifier, the positive slope signal transmission gate, the column display positive analog signal line, the pixel positive addressing storage circuit, the positive analog display amplifier, the positive analog display transmission gate are electrically connected in series to form a functional circuit to process the positive slope signal constructed by four sections of waveforms connected in series, and the negative slope signal line, the negative slope signal amplifier, the negative slope signal transmission gate, the column display negative analog signal line, the pixel negative addressing storage circuit, the negative analog display amplifier, the negative analog display transmission gate are electrically connected in series to form another functional circuit to process the negative slope signal constructed by four sections of waveforms connected in series, and the positive analog display transmission gate and the negative analog display transmission gate both output level signals to the pixel output electrode circuit, and the digital signal latch has the same number of bits as the counter, and is further configured with: a 2 nd connection line, a 5 th connection line, a 6 th connection line, a reset connection line, a 1 st control line, a power supply line, a ground line, and the digital signal latch receives and stores a multi-bit digital signal transmitted by the display digital signal input bus through the 2 nd connection line, and the enable digital signal comparator receives a multi-bit count digital signal transmitted by the counter through the 5 th connection line, receives a multi-bit storage digital signal transmitted by the digital signal latch through the 6 th connection line, receives a reset level signal transmitted by the comparator reset signal line through the reset connection line, transmits a control level signal to the positive slope signal transmission gate and the negative slope signal transmission gate through the 1 st control line,
wherein the positive slope signal amplifier is configured with a positive slope amplification bias terminal, a positive slope amplification input terminal, a positive slope amplification output terminal, and the positive slope signal transmission gate is configured with a positive slope transmission control terminal, a positive slope transmission input terminal, a positive slope transmission output terminal, and the pixel positive addressing storage circuit is configured with a pixel positive addressing control terminal, a pixel positive storage input terminal, a pixel positive storage output terminal, and the positive analog display amplifier is configured with a positive display amplification bias terminal, a positive display amplification input terminal, a positive display amplification output terminal, and the positive analog display transmission gate is configured with a positive display transmission inverted control terminal, a positive display transmission input terminal, a positive display transmission output terminal, and a negative display transmission output terminal, and the negative slope signal amplifier is configured with a negative slope amplification bias terminal, a negative slope amplification input terminal, a negative slope amplification output terminal, and the negative slope signal transmission gate is configured with a negative slope transmission control terminal, a negative slope transmission input terminal, a negative slope transmission output terminal, and the pixel negative slope signal transmission storage circuit is configured with a negative pixel amplification bias terminal, a negative slope amplification control terminal, a negative slope amplification output terminal, and the negative display output terminal, and the negative slope signal transmission gate is configured with a negative pixel negative amplification control terminal, a negative amplification output terminal, a negative amplification electrode, and the negative display output terminal,
and the enable digital signal comparator is provided with a high level output to the 1 st control line when the rising edge of the enable signal transmitted on the comparator reset signal line is received through the reset connecting line to trigger, and a low level output to the 1 st control line when the digital signal received from the digital signal latch through the 6 th connecting line is compared with the digital signal received from the counter through the 5 th connecting line and when the two digital signals are the same;
on one hand, the positive slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P-type amplifier offset end as the positive slope amplification offset end, a P-type amplifier input end as the positive slope amplification input end and a P-type amplifier output end as the positive slope amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N-type amplifier offset end as the positive slope amplification offset end, an N-type amplifier input end as the positive slope amplification input end and an N-type amplifier output end as the positive slope amplification output end, the positive slope amplification offset end is connected with the slope bias voltage supply line, and the positive slope amplification input end is connected with the positive slope signal line,
wherein the PMOS type dual-transistor common-drain amplifier comprises a 1 st PMOS transistor at least comprising a 1 st PMOS gate, a 1 st PMOS source and a 1 st PMOS drain, and a 2 nd PMOS transistor at least comprising a 2 nd PMOS gate, a 2 nd PMOS source and a 2 nd PMOS drain, and is characterized in that the 1 st PMOS gate serves as the bias terminal of the P type amplifier, the 2 nd PMOS gate serves as the input terminal of the P type amplifier, the 1 st PMOS drain is connected with the 2 nd PMOS source to form the output terminal of the P type amplifier, the 1 st PMOS source is connected to the power supply line, and the 2 nd PMOS drain is connected to the ground line,
wherein the NMOS type dual-transistor common-drain amplifier is composed of a 1-NMOS transistor at least including a 1-NMOS gate, a 1-NMOS drain and a 1-NMOS source, and a 2-NMOS transistor at least including a 2-NMOS gate, a 2-NMOS drain and a 2-NMOS source, and is characterized in that the 2-NMOS gate serves as the bias terminal of the N-type amplifier, the 1-NMOS gate serves as the input terminal of the N-type amplifier, the 2-NMOS drain is connected with the 1-NMOS source to constitute the output terminal of the N-type amplifier, the 1-NMOS drain is connected to the power supply line, and the 2-NMOS source is connected to the ground line,
and the positive slope signal transmission gate is composed of a 1 st analog signal transmission gate which adopts a 1 st analog transmission gate control end as the positive slope transmission control end, a 1 st analog transmission gate input end as the positive slope transmission input end and a 1 st analog transmission gate output end as the positive slope transmission output end, the positive slope transmission input end is connected with the positive slope amplification output end, the positive slope transmission output end is connected with the column display positive analog signal line,
wherein the 1 st analog signal transmission gate is composed of a 3 rd PMOS transistor at least comprising a 3 rd PMOS gate, a 3 rd PMOS drain and a 3 rd PMOS source, a 3 rd NMOS transistor at least comprising a 3 rd NMOS gate, a 3 rd NMOS drain and a 3 rd NMOS source, a 4 th PMOS transistor at least comprising a 4 th PMOS gate, a 4 th PMOS drain and a 4 th PMOS source, and a 4 th NMOS transistor at least comprising a 4 th NMOS gate, a 4 th NMOS drain and a 4 th NMOS source, and is further configured with: a power supply line and a ground line, and is characterized in that the 4 th-NMOS gate, the 4 th-PMOS gate and the 3 rd-NMOS gate are connected to form a control terminal of the 1 st analog transmission gate, the 4 th-NMOS source, the 4 th-PMOS drain and the 3 rd-PMOS gate are connected to each other, the 4 th-PMOS source is connected to the power supply line, the 4 th-NMOS drain is connected to the ground line, the 3 rd-PMOS drain and the 3 rd-NMOS source are connected to form an input terminal of the 1 st analog transmission gate, the 3 rd-PMOS source and the 3 rd-NMOS drain are connected to form an output terminal of the 1 st analog transmission gate,
and the pixel positive addressing storage circuit is composed of one of a P-type switch capacitor control end serving as the pixel positive addressing control end, a P-type switch capacitor input end serving as the pixel positive storage input end, a P-type switch capacitor output end serving as a PMOS-type switch capacitor of the pixel positive storage output end or an N-type switch capacitor control end serving as the pixel positive addressing control end, an N-type switch capacitor input end serving as the pixel positive storage input end, and an N-type switch capacitor output end serving as an NMOS-type switch capacitor of the pixel positive storage output end, and the pixel positive addressing control end is connected with the row addressing signal line, and the pixel positive storage input end is connected with the column display positive analog signal line,
wherein the PMOS type switch capacitor is composed of a 6 th PMOS transistor comprising at least a 6 th-PMOS gate, a 6 th-PMOS drain, and a 6 th-PMOS source, and a MIM capacitor comprising at least a MIM capacitor upper plate and a MIM capacitor lower plate, and characterized in that the 6 th-PMOS gate serves as the P type switch capacitor control terminal, the 6 th-PMOS source serves as the P type switch capacitor input terminal, the 6 th-PMOS drain is connected to the MIM capacitor upper plate to constitute the P type switch capacitor output terminal, and the MIM capacitor lower plate is connected to the ground line,
wherein the NMOS type switch capacitor is composed of a 6-NMOS transistor at least comprising a 6-NMOS gate, a 6-NMOS drain and a 6-NMOS source, and a MIM capacitor at least comprising a MIM capacitor upper plate and a MIM capacitor lower plate, and is characterized in that the 6-NMOS gate serves as the N type switch capacitor control terminal, the 6-NMOS drain serves as the N type switch capacitor input terminal, the 6-NMOS source is connected with the MIM capacitor upper plate to form the N type switch capacitor output terminal, and the MIM capacitor lower plate is connected to the ground line,
and the positive analog display amplifier is composed of one of a PMOS type dual-transistor common-drain amplifier which adopts a P-type amplifier bias terminal as the positive display amplification bias terminal, a P-type amplifier input terminal as the positive display amplification input terminal, and a P-type amplifier output terminal as the positive display amplification output terminal, or an NMOS type dual-transistor common-drain amplifier which adopts an N-type amplifier bias terminal as the positive display amplification bias terminal, an N-type amplifier input terminal as the positive display amplification input terminal, and an N-type amplifier output terminal as the positive display amplification output terminal, and the positive display amplification input terminal is connected with the pixel positive storage output terminal, and the positive display amplification bias terminal is connected with the positive bias voltage supply line,
and the positive analog display transmission gate is composed of a 2 nd analog signal transmission gate which adopts a 2 nd analog transmission gate positive phase control end as the positive display transmission positive phase control end, a 2 nd analog transmission gate reverse phase control end as the positive display transmission reverse phase control end, a 2 nd analog transmission gate input end as the positive display transmission input end, a 2 nd analog transmission gate output end as the positive display transmission output end, wherein the positive display transmission input end is connected with the positive display amplification output end, the positive display transmission positive phase control end is connected with the global positive display positive phase signal line, the positive display transmission reverse phase control end is connected with the global positive display reverse phase signal line,
the 2 nd analog signal transmission gate is composed of a 5 th-PMOS tube at least comprising a 5 th-PMOS grid electrode, a 5 th-PMOS drain electrode and a 5 th-PMOS source electrode and a 5 th-NMOS tube at least comprising a 5 th-NMOS grid electrode, a 5 th-NMOS drain electrode and a 5 th-NMOS source electrode, and is characterized in that the 5 th-PMOS drain electrode and the 5 th-NMOS source electrode are connected to form an input end of the 2 nd analog transmission gate, the 5 th-NMOS drain electrode and the 5 th-PMOS source electrode are connected to form an output end of the 2 nd analog transmission gate, the 5 th-PMOS gate serves as an inverted control end of the 2 nd analog transmission gate, and the 5 th-NMOS gate serves as a non-inverted control end of the 2 nd analog transmission gate;
on the other hand, the negative slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier using a P-type amplifier bias terminal as the negative slope amplification bias terminal, a P-type amplifier input terminal as the negative slope amplification input terminal, and a P-type amplifier output terminal as the negative slope amplification output terminal, or an NMOS type double-tube common-drain amplifier using an N-type amplifier bias terminal as the negative slope amplification bias terminal, an N-type amplifier input terminal as the negative slope amplification input terminal, and an N-type amplifier output terminal as the negative slope amplification output terminal, and the negative slope amplification bias terminal is connected to the slope bias voltage supply line, and the negative slope amplification output terminal is connected to the negative slope signal line,
and the negative slope signal transmission gate is composed of a 1 st analog signal transmission gate which adopts a 1 st analog transmission gate control end as the negative slope transmission control end, a 1 st analog transmission gate input end as the negative slope transmission input end and a 1 st analog transmission gate output end as the negative slope transmission output end, the negative slope transmission input end is connected with the negative slope amplification output end, the negative slope transmission output end is connected with the column display negative analog signal line,
and the pixel negative addressing storage circuit is composed of one of a PMOS type switch capacitor which adopts a P type switch capacitor control end as the pixel negative addressing control end, a P type switch capacitor input end as the pixel negative storage input end and a P type switch capacitor output end as the pixel negative storage output end, or an NMOS type switch capacitor which adopts an N type switch capacitor control end as the pixel negative addressing control end, an N type switch capacitor input end as the pixel negative storage input end and an N type switch capacitor output end as the pixel negative storage output end, and the pixel negative addressing control end is connected with the row addressing signal line, the pixel negative storage input end is connected with the column display negative analog signal line,
and the negative analog display amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P type amplifier bias end as the negative display amplification bias end, a P type amplifier input end as the negative display amplification input end and a P type amplifier output end as the negative display amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N type amplifier bias end as the negative display amplification bias end, an N type amplifier input end as the negative display amplification input end and an N type amplifier output end as the negative display amplification output end, wherein the negative display amplification input end is connected with the pixel negative storage output end, and the negative display amplification bias end is connected with the negative bias voltage supply line,
and the negative analog display transmission gate is composed of a 2 nd analog signal transmission gate which adopts a 2 nd analog transmission gate positive phase control end as the negative display transmission positive phase control end, a 2 nd analog transmission gate reverse phase control end as the negative display transmission reverse phase control end, a 2 nd analog transmission gate input end as the negative display transmission input end and a 2 nd analog transmission gate output end as the negative display transmission output end, the negative display transmission input end is connected with the negative display amplification output end, the negative display transmission positive phase control end is connected with the global negative display positive phase signal line, the negative display transmission reverse phase control end is connected with the global negative display reverse phase signal line,
and the pixel output electrode circuit is constructed by an output electrode parasitic capacitor formed between the pixel analog signal output electrode and a conductor which is close to the periphery but does not make contact and is connected to the ground line, and is characterized in that the pixel analog signal output electrode serves as one electrode plate of the output electrode parasitic capacitor, the ground line serves as the other electrode plate of the output electrode parasitic capacitor,
the pixel analog signal output electrode is respectively connected with the negative display transmission output end and the positive display transmission output end;
the driving method of the double-path symmetrical slope type analog pixel driving circuit is characterized in that any one display period is formed by adjacent positive field display periods and negative field display periods, each of the positive field display periods and the negative field display periods is formed by an addressing line period which can enable the pixel positive addressing storage circuit and the pixel negative addressing storage circuit to generate input on-state and at least one display line period which always enables the pixel positive addressing storage circuit and the pixel negative addressing storage circuit to keep input off-state, the addressing line period is the same as the display line period in duration, is connected with the display line period in time and is commonly called as a line period, and the positive slope signal amplifier and the negative slope signal amplifier are configured to be in effective working states by bias levels transmitted on the slope bias voltage supply lines in each line period,
and the negative analog display transmission gate is in an off state and the negative analog display amplifier is in an inactive operating state in all display line periods of the positive field display period and the address line period of the negative field display period adjacent thereto, and the positive analog display transmission gate is in an off state and the positive analog display amplifier is in an inactive operating state in all display line periods of the negative field display period and the address line period of the positive field display period adjacent thereto,
each line period is divided into four time periods T1, T2, T3 and T4, two positive slope signals and two negative slope signals which are respectively constructed by connecting four wave forms are configured, and the waveform is characterized in that the highest levels of the positive slope signals and the negative slope signals are the highest level of a slope, the central levels are the central level of the slope, and the lowest levels are the lowest level of the slope, in addition, in each line period, the positive slope signals jump from the highest level of the slope to the central level of the slope in the T1 time period, simultaneously, the negative slope signals jump from the lowest level of the slope to the central level of the slope, in each line period, the positive slope signals and the negative slope signals are fixed to the central level of the slope in the T2 time period, in the T3 time period, the positive slope signals jump from the central level of the slope to the lowest level of the slope, simultaneously, the negative slope signals jump from the central level of the slope to the highest level of the slope, in the T4 time period, the positive slope signals start to carry out incremental change from the lowest level of the slope until the highest level of the slope, and the negative slope signals start to carry out the incremental change from the lowest level of the lowest slope until the lowest level of the negative slope;
first, in the address line period of the positive field display period,
in the T1 period: a positive ramp signal transmitted on the positive ramp signal line transitions from a ramp highest level to a ramp center level while a negative ramp signal transmitted on the negative ramp signal line transitions from a ramp lowest level to a ramp center level,
and the comparator reset signal line has a rising edge signal triggering the enabling digital signal comparator to output a high level, and the positive ramp signal transmission gate and the negative ramp signal transmission gate are respectively made to be in an on state through the positive ramp transmission control terminal and the negative ramp transmission control terminal so as to respectively make the analog signal transmitted on the column display positive analog signal line follow the positive ramp signal transmitted on the positive ramp signal line, the analog signal transmitted on the column display negative analog signal line follow the negative ramp signal transmitted on the negative ramp signal line, and the row addressing signal line has an inactive level such that the pixel positive addressing storage circuit and the pixel negative addressing storage circuit respectively with the column display positive analog signal line and the column display negative analog signal line are in an input off state to continuously maintain the level stored at the end of the previous display period, and the analog signal transmitted on the negative bias voltage supply line configures the negative analog display amplifier to be in an active working state, and the analog negative display transmission gate is configured by the global pulse signal transmitted on the global display inverted signal line and the negative ramp signal transmission line to be in an output state and the analog signal output capacitor of the negative ramp signal transmitted on the global display negative ramp signal line to cause the pixel positive ramp signal line to be in an off state,
and during a period T2: the level of the positive ramp signal transmitted on the positive ramp signal line and the level of the negative ramp signal transmitted on the negative ramp signal line are continuously and fixedly maintained as a ramp signal center level,
and the pulse wave signals received by the positive ramp transmission control end and the negative ramp transmission control end continuously keep the level state of the last time period, so that the analog signals transmitted on the column display positive analog signal line continuously follow the positive ramp signals transmitted on the positive ramp signal line, the analog signals transmitted on the column display negative analog signal line continuously follow the negative ramp signals transmitted on the negative ramp signal line, the pixel positive addressing storage circuit and the pixel negative addressing storage circuit continuously keep the input off state and make the respective level states continuously stored and output, and the negative analog display amplifier continuously keeps the effective working state, and the pulse wave signals transmitted on the global negative display inverted signal line and the pulse wave signals transmitted on the global negative display positive signal line change to enable the negative analog display transmission gate to be in the on state, and also cause the level stored by the pixel negative addressing storage circuit to drive and enhance the pixel analog signal output electrode in real time through the negative analog display amplifier and keep the parasitic capacitor of the output electrode,
and during a period T3: a positive ramp signal transmitted on the positive ramp signal line transitions from a ramp center level to a ramp lowest level while a negative ramp signal transmitted on the negative ramp signal line transitions from a ramp center level to a ramp highest level,
and the pulse wave signals received by the positive ramp transmission control terminal and the negative ramp transmission control terminal are kept at the level state for a previous period of time so as to make the analog signals transmitted on the column display positive analog signal line continuously follow the positive ramp signals transmitted on the positive ramp signal line and the analog signals transmitted on the column display negative analog signal line continuously follow the negative ramp signals transmitted on the negative ramp signal line respectively, and the change of the effective transmission level on the row addressing signal line makes the pixel positive addressing storage circuit and the pixel negative addressing storage circuit respectively in an on-state with the column display positive analog signal line and the column display negative analog signal line, and respectively makes the analog signals transmitted on the column display positive analog signal line stored in the pixel positive addressing storage circuit in real time, the analog signals transmitted on the column display negative analog signal line stored in the pixel negative addressing storage circuit in real time, and the pulse wave signals transmitted on the global negative display inverted signal line and the pulse wave signals transmitted on the global negative display negative analog signal line changed so that the negative ramp signal transmitted on the negative ramp transmission line is in an off state again, and the analog display gate signal output in an off-state, and the negative ramp signal output amplifier is configured to make the analog signal output in an off state again, and the negative ramp signal output in the negative ramp signal output state, and the negative ramp signal output amplifier, and the analog display positive ramp signal line is supplied to the negative ramp signal line,
and during a period T4: at the beginning, the counter is reset to zero to start counting, a positive slope signal transmitted on the positive slope signal line is synchronously and incrementally changed from a slope lowest level to a slope highest level along with the counting speed of the counter, a negative slope signal transmitted on the negative slope signal line is synchronously and decrementally changed from the slope highest level to the slope lowest level along with the counting speed of the counter, pulse wave signals received by the positive slope transmission control end and the negative slope transmission control end are continuously kept in a level state of a last time period, so that an analog signal transmitted on the column display positive analog signal line is continuously followed by the positive slope signal transmitted on the positive slope signal line, and an analog signal transmitted on the column display negative analog signal line is continuously followed by the negative slope signal transmitted on the negative slope signal line respectively,
and when the number generated by the counter is equal to the number stored by the digital signal latch, the enable digital signal comparator is triggered to output a low level, and the positive slope signal transmission gate and the negative slope signal transmission gate are both in an open circuit state, so that the analog signal transmitted on the column display positive analog signal line is not changed in real time along with the positive slope signal level transmitted on the positive slope signal line and is kept at a fixed level until the positive slope signal transmission gate is in an on state again, and the analog signal transmitted on the column display negative analog signal line is not changed in real time along with the negative slope signal level transmitted on the negative slope signal line and is kept at a fixed level until the negative slope signal transmission gate is in an on state again,
and the pixel positive addressing storage circuit and the pixel negative addressing storage circuit keep the state of input path, and respectively make the analog signal transmitted on the column display positive analog signal line drive the analog signal update of the pixel positive storage output end, and make the analog signal transmitted on the column display negative analog signal line drive the analog signal update of the pixel negative storage output end,
when the voltage of the positive slope signal transmitted on the positive slope signal line is increased to the highest level of the slope signal, the voltage of the negative slope signal transmitted on the negative slope signal line is decreased to the low level of the slope signal, the counter also counts to reach a full value, the negative analog display amplifier continues to keep an invalid working state, and the negative analog display transmission gate continues to keep a turn-off state, so that the analog signal output on the pixel analog signal output electrode continues to be in a voltage state for a previous period of time;
then, in a display line period of the positive field display period,
in four time periods of T1, T2, T3 and T4: the positive slope signal transmitted on the positive slope signal line, the negative slope signal transmitted on the negative slope signal line, the pulse wave signal transmitted on the comparator reset signal line and the pulse wave signals received by the positive slope transmission control end and the negative slope transmission control end in the previous three time periods are all repeatedly transmitted in the waveform state in the previous line period, and the analog signal transmitted on the column display positive analog signal line is made to continuously follow the positive slope signal transmitted on the positive slope signal line and the analog signal transmitted on the column display negative analog signal line is made to continuously follow the negative slope signal transmitted on the negative slope signal line,
and the row addressing signal line transmits an invalid level so that the pixel positive addressing storage circuit and the pixel negative addressing storage circuit always keep inputting an off state to cause respective level states at the end of a previous row period to be continuously stored and output respectively, and the pulse wave signal transmitted on the global positive display reverse phase signal line and the pulse wave signal transmitted on the global positive display positive phase signal line firstly configure the positive analog display transmission gate to an off state in a T1 time period to cause an analog signal output on the pixel analog signal output electrode to continue a level state in a previous time period, then the positive analog display transmission gate is configured to be in an on state in a T2 time period and the positive analog display amplifier is configured to be in an active working state to cause a level output by the pixel positive addressing storage circuit to drive the pixel analog signal output electrode to be updated in real time and to be kept at the output electrode parasitic capacitor,
and when the number generated by the counter is equal to the number stored by the digital signal latch in the T4 time period, the enable digital signal comparator is triggered to output a low level, so that the positive slope signal transmission gate and the negative slope signal transmission gate are both in an off state, and the analog signals respectively transmitted on the column display positive analog signal line and the column display negative analog signal line are both kept at a fixed level until the positive slope signal transmission gate and the negative slope signal transmission gate are in an on state again,
when the counter is stopped, the level of the positive slope signal transmitted on the positive slope signal line is increased to the highest level of the slope signal, the level of the negative slope signal transmitted on the negative slope signal line is decreased to the low level of the slope signal, and the counter also counts to reach a full value;
then, in the address line period of the negative field display period,
in four time periods of T1, T2, T3 and T4: the positive ramp signal transmitted on the positive ramp signal line, the negative ramp signal transmitted on the negative ramp signal line, the pulse wave signal transmitted on the comparator reset signal line, the pulse wave signal transmitted on the positive bias voltage supply line, the pulse wave signal transmitted on the negative bias voltage supply line, the pulse wave signal transmitted on the global positive display positive phase signal line, the pulse wave signal transmitted on the global positive display reverse phase signal line, the pulse wave signal transmitted on the global negative display positive phase signal line, and the pulse wave signal transmitted on the global negative display reverse phase signal line are all repeatedly transmitted in a waveform state transmitted in a display line period of an adjacent positive field display period, and the pulse wave signals received by the positive ramp transmission control terminal and the negative ramp transmission control terminal are all repeatedly transmitted in a waveform state in the previous line period in the previous three periods and respectively cause the analog signal transmitted on the column display positive analog signal line to continuously follow the positive ramp signal transmitted on the positive ramp signal line, and the analog signal transmitted on the column display negative ramp signal line to continuously follow the negative ramp signal transmitted on the negative ramp signal line,
and in the time periods T1 and T2: the pixel positive addressing storage circuit and the pixel negative addressing storage circuit are both configured to keep an input off state so that the level state of each in the last period of time continues to be stored and output, respectively, and the pulse wave signal transmitted on the global positive display inverted phase signal line and the pulse wave signal transmitted on the global positive display positive phase signal line configure the positive analog display transfer gate to an off state for a period of time T1 causing the analog signal output on the pixel analog signal output electrode to continue to the level state for the last period of time, and configure the positive analog display transfer gate to an on state for a period of time T2 and the positive analog display amplifier to an active operating state causing the level output by the pixel positive addressing storage circuit to drive the pixel analog signal output electrode in real time and keep the parasitic capacitor at the output electrode,
and the transmission of an active level on the row addressing signal line during the time periods T3, T4 such that both the pixel positive addressing storage circuit and the pixel negative addressing storage circuit re-enter and maintain the on-state will result in an update of the analog signals at the pixel positive storage output and the pixel negative storage output, respectively,
and when the number generated by the counter equals the number stored by the digital signal latch during the period T4, the enable digital signal comparator is triggered to output a low level, which results in that the positive ramp signal transmission gate and the negative ramp signal transmission gate are both in an off state, and further the analog signals transmitted on the column display positive analog signal line and the column display negative analog signal line are respectively kept at a fixed level until the positive ramp signal transmission gate and the negative ramp signal transmission gate are in an on state again,
and the level of the positive slope signal transmitted on the positive slope signal line is increased to the highest level of the slope signal at the termination and the level of the negative slope signal transmitted on the negative slope signal line is decreased to the low level of the slope signal, the counter also counts up to the full value,
then, in a display line period of the negative field display period,
in time periods T1, T2, T3, T4: a positive ramp signal transmitted on the positive ramp signal line, a negative ramp signal transmitted on the negative ramp signal line, a pulse wave signal transmitted on the comparator reset signal line, a pulse wave signal transmitted on the positive bias voltage supply line, a pulse wave signal transmitted on the negative bias voltage supply line, a pulse wave signal transmitted on the global positive display positive phase signal line, a pulse wave signal transmitted on the global positive display reverse phase signal line, a pulse wave signal transmitted on the global negative display positive phase signal line, and a pulse wave signal transmitted on the global negative display reverse phase signal line are all repeatedly transmitted in a waveform state transmitted in an addressing row period of an adjacent positive field display period, and pulse wave signals received by the positive ramp transmission control terminal and the negative ramp transmission control terminal are all repeatedly transmitted in a waveform state in the previous row period in the previous three periods, and respectively make the analog signal transmitted on the column display positive analog signal line continuously follow the positive ramp signal transmitted on the positive ramp signal line, and the analog signal transmitted on the column display negative ramp signal continuously follow the negative ramp signal transmitted on the negative ramp signal line,
and the transmission of an invalid level on the row addressing signal line causes both the pixel positive addressing storage circuit and the pixel negative addressing storage circuit to always keep inputting an off state, resulting in respective level states at the end of a previous row cycle continuing to be stored and output, and the configuration of the negative analog display transfer gate to the off state in a T1 period of time causes the analog signal output on the pixel analog signal output electrode to continue to the level state for a previous period of time, and the configuration of the negative analog display transfer gate to the on state in a T2 period of time and the configuration of the negative analog display amplifier to the active state will cause the level output by the pixel negative addressing storage circuit to drive the pixel analog signal output electrode in real time to update and hold the output electrode parasitic capacitor,
and when the number generated by the counter equals the number stored by the digital signal latch during the period T4, the enable digital signal comparator is triggered to output a low level, which results in that the positive ramp signal transmission gate and the negative ramp signal transmission gate are both in an off state, and further the analog signals transmitted on the column display positive analog signal line and the column display negative analog signal line are respectively kept at a fixed level until the positive ramp signal transmission gate and the negative ramp signal transmission gate are in an on state again,
when the counter is stopped, the level of the positive slope signal transmitted on the positive slope signal line is increased to the highest level of the slope signal, the level of the negative slope signal transmitted on the negative slope signal line is decreased to the low level of the slope signal, and the counter also counts to reach a full value;
as a result, the analog signal waveform outputted on the pixel analog signal output electrode is characterized by being divided into a positive field display section composed of a portion generated in a line display period of a positive field display period and a portion generated in a line address period of an adjacent negative field display period and a portion in a line display period T1 period of the negative field display period, a negative field display section composed of a portion generated in a line display period of a negative field display period and a portion generated in a line address period of an adjacent positive field display period and a portion in a line display period T1 period of the positive field display period,
the driving method further includes: the four time periods T1, T2, T3 and T4 in each row period are performed sequentially and then circulate, so that each display period can output a pair of analog levels corresponding to the numbers stored by the digital signal latch in the row addressing period of the current display period at the pixel analog signal output electrode.
The invention has the beneficial effects that: compared with the prior art, the invention has three advantages: the double-tube common-drain amplifier is configured on both the column display positive analog signal lines and the column display negative analog signal lines, and can objectively isolate electric signal crosstalk between the column display positive analog signal lines and between the column display negative analog signal lines; the driving method comprises a two-path symmetrical four-section wave type slope signal and a time-period sequential circulation method of the two-path symmetrical four-section wave type slope signal T1, T2, T3 and T4, so that the phenomenon of signal crosstalk between an addressing sampling behavior and a display behavior in the same pixel circuit is avoided; and thirdly, the driving method comprises the step of combining two-way symmetrical four-section wave type slope signals and the positive field display period and the negative field display period thereof into one display period, and the method can alternately output a pair of analog levels.
Drawings
Fig. 1 is a schematic diagram of a two-way symmetric ramp type analog pixel driving circuit, in which 1: control line 1, 2: 2 nd connecting line, 3: positive ramp signal amplifier, 4: positive slope amplification bias end, 5: 5 th connecting line, 6: 6 th connecting line, 7: positive slope amplification output, 8: counter, 9: connecting wire resets, 10: negative ramp amplification input, 11: digital signal latch, 12: enable digital signal comparator, 13: positive slope amplification input, 14: negative ramp signal amplifier, 15: positive slope transmission control terminal, 16: display digital signal input bus, 17: positive slope signal line, 18: ramp bias voltage supply line, 19: comparator reset signal line, 21: positive display amplification output, 22: positive display transmission input, 23: positive analog display transmission gate, 24: row address signal line, 25: positive display transmission output, 26: pixel analog signal output electrode, 27: negative ramp amplification output, 28: positive bias voltage supply line, 29: global positive display positive phase signal line, 30: pixel output electrode circuit, 31: global negative display inverted signal line, 32: positive display transmission inverting control terminal, 33: global negative display positive phase signal line, 34: positive display transmission positive control terminal, 35: negative ramp amplification bias, 36: negative slope transmission control terminal, 37: zoom bias terminal is shown, 38: negative ramp transmission input, 39: positive display amplification input, 40: negative ramp signal transmission gate, 41: negative slope transmission output, 42: pixel positive storage output, 43: pixel positive storage input, 44: column shows positive analog signal lines, 45: column shows negative analog signal line, 46: pixel positive addressing storage circuit, 47: pixel positive address control terminal, 48: pixel negative address control terminal, 49: positive analog display amplifier, 51: positive slope transmission output, 52: positive slope signal transmission gate, 53: positive slope transmission input, 57: negative bias voltage supply line, 58: global positive display inverted signal line, 59: pixel negative storage input, 60: pixel negative address storage circuit, 69: negative analog display transmission gate, 70: negative analog display amplifier, 71: negative display transmission output, 72: negative display transmission positive control terminal, 78: negative display transmission inverting control terminal, 79: negative ramp signal line, 80: negative display transmission input, 89: negative display amplification output, 90: negative display amplification bias terminal, 91: negative display amplification input, 92: a pixel negative storage output;
fig. 2 is a schematic diagram of a PMOS type dual-transistor common-drain amplifier circuit, in which 77: power supply line, 85: 1 st-PMOS gate, 86: 1 st-PMOS source, 87: 1 st-PMOS drain, 88: 1 st-PMOS tube, 93: 2-PMOS tube, 94: 2 nd-PMOS gate, 95: 2 nd-PMOS source, 96: 2-PMOS drain, 97: p-type amplifier input, 98: p-type amplifier output, 99: p-type amplifier bias terminal, 135: a ground line;
fig. 3 is a schematic diagram of an NMOS type dual-transistor common-drain amplifier circuit, in which 77: power supply line, 101: 1 st-NMOS transistor, 102: 1 st-NMOS gate, 103: 1 st-NMOS drain, 104: 1 st-NMOS source, 105: 2 nd-NMOS transistor, 106: 2 nd-NMOS gate, 107: 2 nd-NMOS drain, 108: 2 nd-NMOS source, 109: n-type amplifier bias terminal, 110: n-type amplifier input, 111: n-type amplifier output, 135: a ground line;
fig. 4 is a schematic diagram of a 1 st analog signal transmission gate circuit, in which 54: analog transmission gate control terminal 1, 55: 1 st analog transmission gate output, 56: 1 st analog transmission gate input, 61: 3 rd-PMOS gate, 62: 3-PMOS drain, 63: 3 rd-PMOS source, 64: 3 rd-PMOS tube, 65: 3-NMOS source, 66: 3 rd-NMOS gate, 67: 3-NMOS drain, 68: 3-NMOS tube, 73: 4-PMOS tube, 74: 4 th-PMOS gate, 75: 4 th-PMOS source, 76: 4-PMOS drain, 77: power supply line, 81: 4-NMOS gate, 82: 4-NMOS source, 83: 4-NMOS transistor, 84: 4-NMOS drain, 135: a ground line;
fig. 5 is a schematic diagram of a PMOS type switched capacitor circuit, in which 112: p-type switched capacitor control terminal, 113: MIM capacitor bottom plate, 115: MIM capacitor, 116: MIM capacitor upper plate, 117: p-type switched capacitor input, 118: p-type switched capacitor output, 121: 6 th-PMOS source, 123: 6 th-PMOS gate, 124: 6 th-PMOS drain, 125: 6 th-PMOS tube, 135: a ground line;
fig. 6 is a schematic diagram of an NMOS type switched capacitor circuit, in which 113: MIM capacitor bottom plate, 114: n-type switched capacitor control terminal, 115: MIM capacitor, 116: MIM capacitor upper plate, 119: n-type switched capacitor input, 120: n-type switched capacitor output, 126: 6 th-NMOS drain, 127: 6 th-NMOS gate, 128: 6 th-NMOS source, 129: 6 th-NMOS transistor, 135: a ground line;
fig. 7 is a schematic diagram of a 2 nd analog signal transmission gate circuit, in which 130: input of 2 nd analog transmission gate, 131: 2 nd analog transmission gate output, 132: positive control terminal of 2 nd analog transmission gate, 133: 2 nd analog transmission gate inverting control terminal, 141: 5 th-PMOS gate, 142: 5-PMOS drain, 143: 5 th-PMOS source, 145: 5 th-PMOS tube, 146: 5 th-NMOS source, 147: 5 th-NMOS gate, 148: 5-NMOS drain, 149: a 5 th NMOS transistor;
fig. 8 is a schematic diagram of a pixel output electrode circuit, in which 20: output electrode parasitic capacitor, 26: pixel analog signal output electrode, 135: a ground line;
fig. 9 is a waveform diagram of a two-way symmetric four-segment waveform ramp signal of one of the application scenarios of the two-way symmetric ramp type analog pixel driving circuit, wherein:
srp _ p: the positive ramp signal transmitted on the positive ramp signal line 17,
srp _ n: the negative ramp signal transmitted on the negative ramp signal line 79,
v1: the lowest level of the ramp is set to,
v2: the center level of the ramp is set to be,
v3: the highest level of the ramp is set to be,
VD: the power supply line 77 is at a level which,
VG: the ground line is 135 level;
fig. 10 is a summary of signal waveforms driven by one of the application scenarios of the dual-path symmetric slope-type analog pixel driving circuit, where:
srp _ p: the positive ramp signal transmitted on the positive ramp signal line 17,
srp _ n: the negative ramp signal transmitted on the negative ramp signal line 79,
v1: the lowest level of the ramp signal is set,
v2: the center level of the ramp signal is set,
v3: the highest level of the ramp signal is set to,
vbp: the ramped positive bias level carried on the ramped bias voltage supply line 18,
vbn: the ramp negative bias level carried on the ramp bias voltage supply line 18,
RST: the comparator resets the pulse wave signal transmitted on the signal line 19,
and (2) ENC: the positive slope signal transmission gate 52 enables the pulse wave signal received by the control terminal,
SDi _ p: the columns show the analog signals being transmitted on the analog signal line 44,
SDi _ n: the columns show the analog signals transmitted on the negative analog signal line 45,
sgp: an addressing positive pulse wave signal transmitted on the row addressing signal line 24,
sgn: the addressing negative pulse wave signal transmitted on the row addressing signal line 24,
vsc _ p: the pixel is storing the analog signal output at output 42,
vsc _ n: the pixel negatively stores the analog signal output by output 92,
vbp2p: a P pulse wave signal transmitted on the positive bias voltage supply line 28,
vbn2p: the N pulse wave signal transmitted on the positive bias voltage supply line 28,
vbp2n: a P pulse wave signal transmitted on the negative bias voltage supply line 57,
vbn2n: an N pulse wave signal transmitted on the negative bias voltage supply line 57,
SNp: the global positive display is the N pulse wave signal transmitted on the positive phase signal line 29,
SPp: the global positive display inverts the P-pulse wave signal transmitted on the signal line 58,
SNn: the global negative display positive phase signal line 33 transmits the N pulse wave signal,
SPn: the P-pulse wave signal transmitted on the global negative display inversion signal line 31,
vout: an analog signal output on the pixel analog signal output electrode 26;
Detailed Description
First, the circuit structure of the dual-path symmetric ramp analog pixel of the present invention is further described with reference to fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, and fig. 8:
the two-way symmetrical ramp type analog pixel driving circuit is constituted by a digital signal latch 11, a counter 8, an enable digital signal comparator 12, a positive ramp signal amplifier 3, a positive ramp signal transfer gate 52, a pixel positive address storage circuit 46, a positive analog display amplifier 49, a positive analog display transfer gate 23, a negative ramp signal amplifier 14, a negative ramp signal transfer gate 40, a pixel negative address storage circuit 60, a negative analog display amplifier 70, a negative analog display transfer gate 69, a pixel output electrode circuit 30, and a display digital signal input bus 16, a comparator reset signal line 19, a positive ramp signal line 17, a negative ramp signal line 79, a ramp bias voltage supply line 18, a row address signal line 24, a positive bias voltage supply line 28, a negative bias voltage supply line 28, a global positive display positive phase signal line 29, a global positive display phase inverted signal line 58, a global negative display positive phase signal line 33, a global negative display phase inverted signal line 31, a column display positive analog signal line 44, and a column display analog signal line 45 in common, and the positive slope signal line 17, the positive slope signal amplifier 3, the positive slope signal transmission gate 52, the column display positive analog signal line 44, the pixel positive addressing storage circuit 46, the positive analog display amplifier 49, and the positive analog display transmission gate 23 are electrically connected in series to form a functional circuit to process the positive slope signal constructed by four-segment waveform connection, and the negative slope signal line 79, the negative slope signal amplifier 14, the negative slope signal transmission gate 40, the column display negative analog signal line 45, the pixel negative addressing storage circuit 60, the negative analog display amplifier 70, and the negative analog display transmission gate 69 are electrically connected in series to form another functional circuit to process the negative slope signal constructed by four-segment waveform connection, and the positive analog display transmission gate 23 and the negative analog display transmission gate 69 both output level signals to the pixel output electrode circuit 30, and the digital signal latch 11 has the same number of bits as the counter 8, and is further configured with: a 2 nd connection line 2, a 5 th connection line 5, a 6 th connection line 6, a reset connection line 9, a 1 st control line 1, a power supply line 77, a ground line 135, the digital signal latch 11 being connected to the display digital signal input bus 16 through the 2 nd connection line 2 and receiving and storing a multi-bit digital signal transmitted by the display digital signal input bus 16, and the enable digital signal comparator 12 being connected to the counter 8 through the 5 th connection line 5 and receiving a multi-bit count digital signal transmitted by the counter 8, connected to the digital signal latch 11 through the 6 th connection line 6 and receiving a multi-bit store digital signal transmitted by the digital signal latch 11, connected to the comparator reset signal line 19 through the reset connection line 9 and receiving a reset level signal transmitted by the comparator reset signal line 19, connected to the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 through the 1 st control line 1 and transmitting control level signals to the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36, respectively;
wherein, as shown in the schematic diagram of the two-way symmetrical slope type analog pixel driving circuit of fig. 1, the positive slope signal amplifier 3 is configured with a positive slope amplification bias terminal 4, a positive slope amplification input terminal 13, and a positive slope amplification output terminal 7, and the positive slope signal transmission gate 52 is configured with a positive slope transmission control terminal 15, a positive slope transmission input terminal 53, and a positive slope transmission output terminal 51, and the pixel positive addressing storage circuit 46 is configured with a pixel positive addressing control terminal 47, a pixel positive storage input terminal 43, and a pixel positive storage output terminal 42, and the positive analog display amplifier 49 is configured with a positive display amplification bias terminal 37, a positive display amplification input terminal 39, and a positive display amplification output terminal 21, and the positive analog display transmission gate 23 is configured with a positive display transmission inverse phase control terminal 32, a positive display transmission positive phase control terminal 34, a positive display transmission input terminal 22, and a positive display transmission output terminal 25, the negative slope signal amplifier 14 is configured with a negative slope amplification bias terminal 35, a negative slope amplification input terminal 10, a negative slope amplification output terminal 27, and the negative slope signal transmission gate 40 is configured with a negative slope transmission control terminal 36, a negative slope transmission input terminal 38, a negative slope transmission output terminal 41, and the pixel negative addressing storage circuit 60 is configured with a pixel negative addressing control terminal 48, a pixel negative storage input terminal 59, a pixel negative storage output terminal 92, and the negative analog display amplifier 70 is configured with a negative display amplification bias terminal 90, a negative display amplification input terminal 91, a negative display amplification output terminal 89, and the negative analog display transmission gate 69 is configured with a negative display transmission inverse control terminal 78, a negative display transmission positive control terminal 72, a negative display transmission input terminal 80, a negative display transmission output terminal 71, and the pixel output electrode circuit 30 is configured with a pixel analog signal output electrode 26 and a pixel analog signal output electrode 26 which is close to the periphery but not in contact with the periphery and is not in contact with the periphery and the periphery of the pixel analog signal output electrode circuit 30 The output electrode parasitic capacitor 20 formed between the conductors connected to the ground line 135,
and the enable digital signal comparator 12 is configured to output a high level to the 1 st control line 1 when a rising edge of an enable signal transmitted on the comparator reset signal line 19 is received through the reset connection line 9, and to output a low level to the 1 st control line 1 when a digital signal received from the digital signal latch 11 through the 6 th connection line 6 is compared with a digital signal received from the counter 8 through the 5 th connection line 5 and when the two digital signals are the same;
referring to fig. 2 and fig. 3 together, on one hand, the positive slope signal amplifier 3 as shown in fig. 1 is composed of a PMOS type dual-transistor common drain amplifier using a P-type amplifier bias terminal 99 as the positive slope amplification bias terminal 4, a P-type amplifier input terminal 97 as the positive slope amplification input terminal 13, and a P-type amplifier output terminal 98 as the positive slope amplification output terminal 7, or one of NMOS type dual-transistor common drain amplifiers using an N-type amplifier bias terminal 109 as the positive slope amplification bias terminal 4, an N-type amplifier input terminal 110 as the positive slope amplification input terminal 13, and an N-type amplifier output terminal 111 as the positive slope amplification output terminal 7, and the positive slope amplification bias terminal 4 is connected to the slope bias voltage supply line 18, and the positive slope amplification input terminal 13 is connected to the positive slope signal line 17,
wherein as shown in the schematic circuit diagram of the PMOS type dual transistor common drain amplifier of fig. 2, the PMOS type dual transistor common drain amplifier is composed of a 1 st PMOS transistor 88 including at least a 1 st PMOS gate 85, a 1 st PMOS source 86 and a 1 st PMOS drain 87, and a 2 nd PMOS transistor 93 including at least a 2 nd PMOS gate 94, a 2 nd PMOS source 95 and a 2 nd PMOS drain 96, and is characterized in that the 1 st PMOS gate 85 serves as the bias terminal 99 of the P-type amplifier, the 2 nd PMOS gate 94 serves as the input terminal 97 of the P-type amplifier, the 1 st PMOS drain 87 is connected to the 2 nd PMOS source 95 to form the output terminal 98 of the P-type amplifier, the 1 st PMOS source 86 is connected to the power supply line 77, and the 2 nd PMOS drain 96 is connected to the ground line 135,
wherein, as shown in the schematic circuit diagram of the NMOS type dual transistor common drain amplifier of FIG. 3, the NMOS type dual transistor common drain amplifier is composed of a 1 st NMOS transistor 101 including at least a 1 st NMOS gate 102, a 1 st NMOS drain 103 and a 1 st NMOS source 104, and a 2 nd NMOS transistor 105 including at least a 2 nd NMOS gate 106, a 2 nd NMOS drain 107 and a 2 nd NMOS source 108, and is characterized in that the 2 nd NMOS gate 106 serves as the N-type amplifier bias terminal 109, the 1 st NMOS gate 102 serves as the N-type amplifier input terminal 110, the 2 nd NMOS drain 107 is connected to the 1 st NMOS source 104 to form the N-type amplifier output terminal 111, the 1 st NMOS drain 103 is connected to the power supply line 77, and the 2 nd NMOS source 108 is connected to the ground line 135,
referring to fig. 4, the positive slope signal transmission gate 52 in fig. 1 is formed by a 1 st analog signal transmission gate using a 1 st analog transmission gate control terminal 54 as the positive slope transmission control terminal 15, a 1 st analog transmission gate input terminal 56 as the positive slope transmission input terminal 53, and a 1 st analog transmission gate output terminal 55 as the positive slope transmission output terminal 51, wherein the positive slope transmission input terminal 53 is connected to the positive slope amplification output terminal 7, the positive slope transmission output terminal 51 is connected to the column display positive analog signal line 44,
as shown in the schematic diagram of the 1 st analog signal transmission gate circuit of fig. 4, the 1 st analog signal transmission gate circuit is composed of a 3 rd PMOS transistor 64 including at least a 3 rd PMOS gate 61, a 3 rd PMOS drain 62 and a 3 rd PMOS source 63, a 3 rd NMOS transistor 68 including at least a 3 rd NMOS gate 66, a 3 rd NMOS drain 67 and a 3 rd NMOS source 65, a 4 th PMOS transistor 73 including at least a 4 th PMOS gate 74, a 4 th PMOS drain 76 and a 4 th PMOS source 75, and a 4 th NMOS transistor 83 including at least a 4 th NMOS gate 81, a 4 th NMOS drain 84 and a 4 th NMOS source 82, and is further configured with: a power supply line 77 and a ground line 135, and is characterized in that the 4 th NMOS gate 81, the 4 th PMOS gate 74 and the 3 rd NMOS gate 66 are connected to form the 1 st analog transmission gate control terminal 54, the 4 th NMOS source 82, the 4 th PMOS drain 76 and the 3 rd PMOS gate 61 are connected to each other, the 4 th PMOS source 75 is connected to the power supply line 77, the 4 th NMOS drain 84 is connected to the ground line 135, the 3 rd PMOS drain 62 and the 3 rd NMOS source 65 are connected to form the 1 st analog transmission gate input terminal 56, the 3 rd PMOS source 63 and the 3 rd NMOS drain 67 are connected to form the 1 st analog transmission gate output terminal 55,
referring to fig. 5 and 6 together, and as shown in fig. 1, the pixel positive addressing storage circuit 46 is formed by one of a PMOS type switched capacitor using a P-type switched capacitor control terminal 112 as the pixel positive addressing control terminal 47, a P-type switched capacitor input terminal 117 as the pixel positive storage input terminal 43, and a P-type switched capacitor output terminal 118 as the pixel positive storage output terminal 42, or an NMOS type switched capacitor using an N-type switched capacitor control terminal 114 as the pixel positive addressing control terminal 47, an N-type switched capacitor input terminal 119 as the pixel positive storage input terminal 43, and an N-type switched capacitor output terminal 120 as the pixel positive storage output terminal 42, and the pixel positive addressing control terminal 47 is connected to the row addressing signal line 24, and the pixel positive storage input terminal 43 is connected to the column display positive analog signal line 44,
wherein, as shown in the schematic diagram of the PMOS type switch capacitor circuit of fig. 5, the PMOS type switch capacitor is composed of a 6 th PMOS transistor 125 including at least a 6 th PMOS gate 123, a 6 th PMOS drain 124 and a 6 th PMOS source 121, and a MIM capacitor 115 including at least a MIM capacitor upper plate 116 and a MIM capacitor lower plate 113, and is characterized in that the 6 th PMOS gate 123 serves as the P type switch capacitor control terminal 112, the 6 th PMOS source 121 serves as the P type switch capacitor input terminal 117, the 6 th PMOS drain 124 is connected to the MIM capacitor upper plate 116 to form the P type switch capacitor output terminal 118, and the MIM capacitor lower plate 113 is connected to the ground line 135,
wherein as shown in the schematic diagram of the NMOS type switch capacitor circuit of fig. 6, the NMOS type switch capacitor is composed of a 6 th NMOS transistor 129 including at least a 6 th-NMOS gate 127, a 6 th-NMOS drain 126 and a 6 th-NMOS source 128, and a MIM capacitor 115 including at least a MIM capacitor upper plate 116 and a MIM capacitor lower plate 113, and is characterized in that the 6 th-NMOS gate 127 serves as the N-type switch capacitor control terminal 114, the 6 th-NMOS drain 126 serves as the N-type switch capacitor input terminal 119, the 6 th-NMOS source 128 is connected to the MIM capacitor upper plate 116 to form the N-type switch capacitor output terminal 120, and the MIM capacitor lower plate 113 is connected to the ground line 135,
and as shown in fig. 1, the positive analog display amplifier 49 is composed of one of a PMOS type dual transistor common drain amplifier using a P-type amplifier bias terminal 99 as the positive display amplification bias terminal 37, a P-type amplifier input terminal 97 as the positive display amplification input terminal 39, a P-type amplifier output terminal 98 as the positive display amplification output terminal 21, or an NMOS type dual transistor common drain amplifier using an N-type amplifier bias terminal 109 as the positive display amplification bias terminal 37, an N-type amplifier input terminal 110 as the positive display amplification input terminal 39, and an N-type amplifier output terminal 111 as the positive display amplification output terminal 21, and the positive display amplification input terminal 39 is connected to the pixel positive storage output terminal 42, and the positive display amplification bias terminal 37 is connected to the positive bias voltage supply line 28,
referring also to fig. 7, the positive analog display transmission gate 23 in fig. 1 is composed of a 2 nd analog signal transmission gate using the 2 nd analog transmission gate positive phase control terminal 132 as the positive display transmission positive phase control terminal 34, the 2 nd analog transmission gate inverse phase control terminal 133 as the positive display transmission inverse phase control terminal 32, the 2 nd analog transmission gate input terminal 130 as the positive display transmission input terminal 22, and the 2 nd analog transmission gate output terminal 131 as the positive display transmission output terminal 25, and the positive display transmission input terminal 22 is connected to the positive display amplification output terminal 21, the positive display transmission positive phase control terminal 34 is connected to the global positive display positive phase signal line 29, and the positive display transmission inverse phase control terminal 32 is connected to the global positive display inverse signal line 58,
wherein, as shown in the schematic diagram of the 2 nd analog signal transmission gate circuit of fig. 7, the 2 nd analog signal transmission gate is composed of a 5 th PMOS transistor 145 at least comprising a 5 th PMOS gate 141, a 5 th PMOS drain 142 and a 5 th PMOS source 143, and a 5 th NMOS transistor 149 at least comprising a 5 th NMOS gate 147, a 5 th NMOS drain 148 and a 5 th NMOS source 146, and is characterized in that the 5 th PMOS drain 142 and the 5 th NMOS source 146 are connected to form the 2 nd analog transmission gate input 130, the 5 th NMOS drain 148 and the 5 th NMOS source 143 are connected to form the 2 nd analog transmission gate output 131, the 5 th PMOS gate 141 serves as the 2 nd analog transmission gate inverting control terminal 133, and the 5 th NMOS gate 147 serves as the 2 nd analog transmission gate inverting control terminal 132;
on the other hand, as shown in fig. 1, the negative slope signal amplifier 14 is composed of one of a PMOS type double-transistor common-drain amplifier using a P-type amplifier bias terminal 99 as the negative slope amplification bias terminal 35, a P-type amplifier input terminal 97 as the negative slope amplification input terminal 10, and a P-type amplifier output terminal 98 as the negative slope amplification output terminal 27, or an NMOS type double-transistor common-drain amplifier using an N-type amplifier bias terminal 109 as the negative slope amplification bias terminal 35, an N-type amplifier input terminal 110 as the negative slope amplification input terminal 10, and an N-type amplifier output terminal 111 as the negative slope amplification output terminal 27, and the negative slope amplification bias terminal 35 is connected to the slope bias voltage supply line 18, and the negative slope amplification input terminal 10 is connected to the negative slope signal line 79,
and the negative slope signal transmission gate 40 is composed of the 1 st analog signal transmission gate which adopts the 1 st analog transmission gate control terminal 54 as the negative slope transmission control terminal 36, the 1 st analog transmission gate input terminal 56 as the negative slope transmission input terminal 38, and the 1 st analog transmission gate output terminal 55 as the negative slope transmission output terminal 41, and the negative slope transmission input terminal 38 is connected with the negative slope amplification output terminal 27, and the negative slope transmission output terminal 41 is connected with the column display negative analog signal line 45,
and the pixel negative addressing storage circuit 60 is composed of one of a PMOS type switched capacitor using the P-type switched capacitor control terminal 112 as the pixel negative addressing control terminal 48, the P-type switched capacitor input terminal 117 as the pixel negative storage input terminal 59, and the P-type switched capacitor output terminal 118 as the pixel negative storage output terminal 92, or an NMOS type switched capacitor using the N-type switched capacitor control terminal 114 as the pixel negative addressing control terminal 48, the N-type switched capacitor input terminal 119 as the pixel negative storage input terminal 59, and the N-type switched capacitor output terminal 120 as the pixel negative storage output terminal 92, and the pixel negative addressing control terminal 48 is connected to the row addressing signal line 24, and the pixel negative storage input terminal 59 is connected to the column display negative analog signal line 45,
and the negative analog display amplifier 70 is composed of one of a PMOS type dual-transistor common-drain amplifier using a P-type amplifier bias terminal 99 as the negative display amplification bias terminal 90, a P-type amplifier input terminal 97 as the negative display amplification input terminal 91, and a P-type amplifier output terminal 98 as the negative display amplification output terminal 89, or an NMOS type dual-transistor common-drain amplifier using an N-type amplifier bias terminal 109 as the negative display amplification bias terminal 90, an N-type amplifier input terminal 110 as the negative display amplification input terminal 91, and an N-type amplifier output terminal 111 as the negative display amplification output terminal 89, and the negative display amplification input terminal 91 is connected to the pixel negative storage output terminal 92, and the negative display amplification bias terminal 90 is connected to the negative bias voltage supply line 57,
and the negative analog display transmission gate 69 is composed of a 2 nd analog signal transmission gate which adopts a 2 nd analog transmission gate positive phase control terminal 132 as the negative display transmission positive phase control terminal 72, a 2 nd analog transmission gate negative phase control terminal 133 as the negative display transmission negative phase control terminal 78, a 2 nd analog transmission gate input terminal 130 as the negative display transmission input terminal 80, a 2 nd analog transmission gate output terminal 131 as the negative display transmission output terminal 71, and the negative display transmission input terminal 80 is connected with the negative display amplification output terminal 89, the negative display transmission positive phase control terminal 72 is connected with the global negative display positive phase signal line 33, the negative display transmission negative phase control terminal 78 is connected with the global negative display negative phase signal line 31,
and the pixel output electrode circuit 30 is constructed by the output electrode parasitic capacitor 20 formed between the pixel analog signal output electrode 26 and a conductor close to the periphery but not in contact with it and connected to the grounding line 135 as illustrated in the pixel output electrode circuit principle diagram of fig. 8, and is characterized in that the pixel analog signal output electrode 26 serves as one electrode plate of the output electrode parasitic capacitor 20, the grounding line 135 serves as the other electrode plate of the output electrode parasitic capacitor 20,
and as in fig. 1 said pixel analog signal output electrode 26 is connected to said negative display transmission output 71 and said positive display transmission output 25 respectively;
next, referring to fig. 9 and 10, a driving method of a two-way symmetrical ramp type analog pixel driving circuit according to the present invention will be described in further detail, wherein the following high level has the same voltage value as the level VD of the power supply line 77, and the following low level has the same voltage value as the level VG of the ground line 135:
any one of the display periods is formed by a positive field display period and a negative field display period which are adjacent to each other, each of the positive field display period and the negative field display period is formed by an addressing line period which enables the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 to be in an input on-state and at least one display line period which always enables the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 to be in an input off-state, the addressing line period is the same as the display line period in duration, is connected in time and is collectively referred to as a line period, and the positive ramp signal amplifier and the negative ramp signal amplifier are configured to be in an active working state by the bias level transmitted on the ramp bias voltage supply line 18 in each line period,
and the negative analog display transmission gate 69 is in an off state and the negative analog display amplifier 70 is in an inactive operation state in all display line periods of the positive field display period and the address line period of the negative field display period adjacent thereto, and the positive analog display transmission gate 23 is in an off state and the positive analog display amplifier is in an inactive operation state in all display line periods of the negative field display period and the address line period of the positive field display period adjacent thereto,
each line period is divided into four time periods T1, T2, T3 and T4, two positive slope signals and two negative slope signals which are respectively constructed by connecting four wave forms are configured, and the waveform is characterized in that the highest levels of the positive slope signals and the negative slope signals are the highest level of a slope, the central levels are the central level of the slope, and the lowest levels are the lowest level of the slope, in addition, in each line period, the positive slope signals jump from the highest level of the slope to the central level of the slope in the T1 time period, simultaneously, the negative slope signals jump from the lowest level of the slope to the central level of the slope, in each line period, the positive slope signals and the negative slope signals are fixed to the central level of the slope in the T2 time period, in the T3 time period, the positive slope signals jump from the central level of the slope to the lowest level of the slope, simultaneously, the negative slope signals jump from the central level of the slope to the highest level of the slope, in the T4 time period, the positive slope signals start to carry out incremental change from the lowest level of the slope until the highest level of the slope, and the negative slope signals start to carry out the incremental change from the lowest level of the lowest slope until the lowest level of the negative slope;
as shown in fig. 9, the two-way symmetric ramp type analog pixel driving circuit has two waveform diagrams (the shaded parts in the figure represent omitted waveforms) of four-segment waveform ramp signals in one of the application scenes where one positive field display period T _ P is adjacent to one negative field display period T _ N,
wherein the positive field display period T _ P is composed of an addressing row period TC11 and at least one display row period TP11, the negative field display period T _ N is composed of an addressing row period TC21 and at least one display row period TP21, and each row period is characterized in that the positive ramp signal Vrp _ P jumps from a ramp highest level V3 to a ramp central level V2 while the negative ramp signal Vrp _ N jumps from a ramp lowest level V1 to a ramp central level V2 for a period T1, the positive ramp signal Vrp _ P and the negative ramp signal Vrp _ N are both fixed at a ramp central level V2 for a period T2, the positive ramp signal Vrp _ P jumps from the ramp central level V2 to a ramp lowest level V1 while the negative ramp signal Vrp _ N jumps from the ramp central level V2 to a ramp highest level V3 while the positive ramp signal Vrp _ P makes an incremental change from the ramp lowest level V1 until the negative ramp highest level V3 starts to a ramp lowest level V1 while the negative ramp signal Vrp _ N makes a decrement from the ramp lowest level V3 while the negative ramp P _ P starts to the ramp lowest level V1 for a period T4;
the waveform diagrams of the driving signals of the two-way symmetrical slope type analog pixel driving circuit in one of the application scenarios that one positive field display period is adjacent to one negative field display period as shown in fig. 10 are summarized (the shaded parts in the figure represent the omitted waveforms),
first, in the positive field display period T _ P and the negative field display period T _ N,
if the positive and negative ramp signal amplifiers 3 and 14 both employ PMOS type double-transistor common-drain amplifiers, the slope negative bias level Vbn transmitted on the slope positive bias voltage supply line 18, which is lower than the voltage VD of the power supply line 77, will be input to the 1 st-PMOS gate 85 and the 1 st-PMOS transistor 88 can be made to enter the saturation region to thereby configure both the positive and negative ramp signal amplifiers 3 and 14 to the active operation state, and if the positive and negative ramp signal amplifiers 3 and 14 both employ NMOS type double-transistor common-drain amplifiers, the slope positive bias level Vbp transmitted on the slope bias voltage supply line 18, which is higher than the voltage VG of the ground line 135, will be input to the 2 nd-NMOS gate 106 and the 2 nd-NMOS transistor 105 can be made to enter the saturation region to thereby configure both the positive and negative ramp signal amplifiers 3 and 3 to the active operation state,
and only during all display line periods of the positive field display period T _ P and the addressing line period of the negative field display period adjacent thereto, if the negative analog display amplifier 70 employs a PMOS type dual-transistor common-drain amplifier, the P-pulse wave Vbp2N transmitted on the negative bias voltage supply line 28 will be inputted with a high level and the 1 st-PMOS gate 85 will be connected to the power supply line 77 level VD causing the 1 st-PMOS transistor 88 to be turned off and the negative analog display amplifier 70 to enter an inactive operating state, and if the negative analog display amplifier 70 employs an NMOS type dual-transistor common-drain amplifier, the N-pulse wave Vbn2N transmitted on the negative bias voltage supply line 28 will be inputted with a low level and the 2 nd-NMOS gate 106 will be connected to the ground line 135 level causing the 2 nd-NMOS transistor 105 to be turned off and the negative analog display amplifier 70 to remain in an inactive operating state, and the P-pulse wave signal SPn transmitted on the global negative display inverted signal line 31 will be high level causing the 5 th-NMOS gate 141 to be connected high level causing the 5 th-NMOS transistor 145 to be turned off and the pixel output signal SNN-gate 69 to be connected to the negative analog display gate electrode 33 causing the negative analog display gate 69 to be connected to be turned off and the negative analog display gate 26 to be connected to the negative analog display gate 26 to cause the negative analog display gate 69 to be connected to the negative analog display gate 19 to be disconnected,
and only in all display line periods of the negative field display period T _ P and the addressing line period of the negative field display period adjacent thereto, if the positive analog display amplifier 49 employs a PMOS type dual-transistor common-drain amplifier, the P-pulse wave Vbp2P transmitted on the positive bias voltage supply line 28 will be inputted with a high level, and the 1 st-PMOS gate 85 will be connected to the power supply line 77 level VD to cause the 1 st-PMOS transistor 88 to be turned off and the positive analog display amplifier 49 to enter an inactive operating state, and if the positive analog display amplifier 49 employs an NMOS type dual-transistor common-drain amplifier, the N-pulse wave Vbn2P transmitted on the positive bias voltage supply line 28 will be inputted with a low level, and the 2 nd-NMOS gate 106 will be connected to the ground line 135 level VG to cause the 2 nd-NMOS transistor 105 to be turned off and the positive analog display amplifier 49 to remain in an inactive operating state, and the P-pulse wave signal SPp transmitted on the global positive display inverted signal line 58 will be high level to cause the 5 th gate 141 to be connected to a high level to cause the 5 th-NMOS transistor 149 to cause the positive analog display amplifier 23 to be turned off and the N-NMOS transistor 23 to be turned off and to cause the global display pixel output signal pop to cause the gate 23 to be turned off and the gate 23 to be turned off to cause the negative analog display pixel output a global display pixel 23 to be displayed by the gate 23 to be displayed in a low level to cause the display gate 23 to be displayed;
meanwhile, in the address line period TC11 of the positive field display period T _ P,
in the T1 period: the positive ramp signal Vrp _ p transmitted on the positive ramp signal line 17 jumps from the ramp highest level V3 to the ramp center level V2 while the negative ramp signal Vrp _ n transmitted on the negative ramp signal line 79 jumps from the ramp lowest level V1 to the ramp center level V2,
and initially the pulse wave signal RST transmitted on the comparator reset signal line 19 is low and the positive ramp signal Vrp _ p transmitted on the positive ramp signal line 17 and the negative ramp signal Vrp _ n transmitted on the negative ramp signal line 79 both transition to the center level V2 and then the rising edge signal identified by ellipse 8 occurs triggering the enable digital signal comparator 12 to output a high level, as indicated by the unidirectional arrow mark line 9, to the 1 st control line 1 and causing both the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 to receive the pulse wave signal ENC as a high level identified by ellipse 9 and in turn having a high level connected to the 3 rd-NMOS gate 66 and having a low level converted by the inverter formed by the 4 th-PMOS transistor and the 4 th-NMOS transistor connected to the 3 rd-PMOS gate 61 and will cause both the positive ramp signal transmission gate 6 and the negative signal transmission gate 40 to be in a pass state and thereby causing both the column display signal transmission gate 44 and the negative signal transmission gate 40 to be in a pass state and causing the column display signal Srp-analog signal transmitted by the column display line 44 and the negative ramp signal Srp _ n to generate the negative ramp signal Srp _ n which is identified by the positive ramp signal Srp _ p _ n transmitted on the unidirectional arrow mark line 10 and the negative ramp signal sdp _ n signal line 9 and then the rising edge signal sdp _ 10 and the rising edge signal sdp _ n transmitted by the negative ramp signal sdp line 10 and the negative ramp signal sdn is identified by the negative ramp signal sdp line 10,
and if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 both employ the NMOS type switching capacitance then the low level on the row addressing signal line 24, at which the transmission addressing positive pulse wave signal Sgp output is identified by ellipse 12, will be input to the 6-NMOS gate 127 and turning off the 6-NMOS transistor 129 results in the respective employed MIM capacitor 115 being in an off state with both the column display positive analog signal line 44 and the column display negative analog signal line 45, respectively, and if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 both employ the PMOS type switching capacitance then the transmission addressing negative pulse wave signal Sgn output on the row addressing signal line 24, at which the high level is identified by ellipse 13, will be input to the 6-PMOS gate 123 and turning off the 6-PMOS transistor 125 results in the respective employed MIM capacitor 115 being in an off state with both the column display positive analog signal line 44 and the column display analog signal line 45, respectively, and turning off the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 into the respective column display positive analog signal line 44 and the pixel negative analog signal line 45, and turning on the pixel negative addressing storage circuit 14, respectively, and turning off the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 54, respectively, and turning on the pixel output storage circuit 14, and the pixel output, respectively, and the pixel positive analog storage circuit 14, the off the pixel storage circuit 14, the output, respectively, and the off the analog storage signal output, and the off state,
and if the negative analog display amplifier 70 employs a PMOS type dual-transistor common drain amplifier then the P-pulse wave Vbp2N level carried on the negative bias voltage supply line 28 is dropped from a high voltage to a level identified by ellipse 16 and the negative analog display amplifier 70 is enabled to cause the 1 st PMOS transistor 88 to enter a saturation region because the 1 st PMOS gate 85 is tied below the level of the power supply line 77 voltage VD to achieve an active operating state, and if the negative analog display amplifier 70 employs an NMOS type dual-transistor common drain amplifier then the N-pulse wave Vbn2N level carried on the negative bias voltage supply line 28 is dropped from a low level to a level identified by ellipse 17 and the negative analog display amplifier 70 is enabled to cause the 2 nd NMOS transistor 105 to enter a saturation region because the 2 nd NMOS gate 106 is tied above the ground line 135 level VG to achieve an active operating state and will result in that the level signal held by the negative addressing storage circuit 60 at the end of the previous display cycle is driven through the negative analog display amplifier 70 to the negative analog display transfer input 80,
and with the P-pulse wave signal SPn transmitted on the global negative display inverted signal line 31 being high, the 5-PMOS gate 141 is turned high, causing the 5-PMOS transistor 145 to be turned off, and with the N-pulse wave signal SNn transmitted on the global negative display positive phase signal line 33 being low, the 5-NMOS gate 147 is turned low, causing the 5-NMOS transistor 149 to be turned off, causing the negative analog display transmission gate 69 to be in an off state, and also causing the analog signal Vout output on the pixel analog signal output electrode 26 to continue to remain at the level state of the output electrode parasitic capacitor 20 at the end of the previous line period, as indicated by the ellipse 6;
and during a period T2: the level of the positive ramp signal Vrp _ p transmitted on the positive ramp signal line 17 and the level of the negative ramp signal Vrp _ n transmitted on the negative ramp signal line 79 continue to be fixedly held at the ramp signal center level V2,
and the pulse wave signal RST transmitted on the comparator reset signal line 19 continues to maintain the level state for the previous period of time, and the pulse wave signals ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 continue to maintain the level state for the previous period of time, and thus the analog signal SDi _ p transmitted on the column display positive analog signal line 44 continues to generate the corresponding level state following the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17, the analog signal SDi _ n transmitted on the column display negative analog signal line 45 continues to generate the corresponding level state following the positive ramp signal Srp _ n transmitted on the negative ramp signal line 79,
and the pixel positive address storage circuit 46 and the pixel negative address storage circuit 60 continue to maintain the input off-state because the pulse wave signal transmitted on the row address signal line 24 maintains the level state for the previous period of time, and respectively cause the level state of the analog signal Vsc _ p of the pixel positive storage output terminal 42 identified by the ellipse 14 in the previous period of time to continue to be stored and output the portion identified by the ellipse 15 as indicated by the one-way arrow line 11, the level state of the analog signal Vsc _ n of the pixel negative storage output terminal 92 identified by the ellipse 54 in the previous period of time to continue to be stored and output the portion identified by the ellipse 55 as indicated by the one-way arrow line 51,
and the negative analog display amplifier 70 continues to maintain the active operation state because the analog signal transmitted on the negative bias voltage supply line 57 maintains the level state for the previous period of time,
and the P-pulse wave signal SPn transmitted on the global negative display inverted signal line 31 transits to the low level to make the 5 th-PMOS gate 141 connected to the low level, which causes the 5 th-PMOS transistor 145 to be turned on, and at the same time, the N-pulse wave signal SNn transmitted on the global negative display positive signal line 33 transits to the high level to make the 5 th-NMOS gate 147 connected to the high level, which causes the 5 th-NMOS transistor 149 to be turned on, which causes the negative analog display transmission gate 69 to be in the on-state, and also causes the analog signal Vsc _ N level of the pixel negative storage output terminal 92 to be identified by the ellipse 55, so as to drive the analog signal Vout generated by the pixel analog signal output electrode 26 in real time through the negative analog display amplifier 70 as indicated by the one-way arrow line 12 and maintain the level state of the output electrode parasitic capacitor 20 as the level state of the ellipse 18 to strengthen the level state of the portion identified by the ellipse 6;
and during a period T3: the positive ramp signal Vrp _ p transmitted on the positive ramp signal line 17 makes a transition from the ramp center level V3 to the ramp minimum level V2 while the negative ramp signal Vrp _ n transmitted on the negative ramp signal line 79 makes a transition from the ramp center level V1 to the ramp maximum level V2,
and the pulse wave signal RST transmitted on the comparator reset signal line 19 continues to maintain the level state for the previous period of time, and the pulse wave signals ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 both continue to maintain the level state for the previous period of time so as to cause the analog signal SDi _ p transmitted on the column display positive analog signal line 44 to continue to follow the portion of the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 identified by the ellipse 7 to produce the electrical signal portion identified by the ellipse 22 as indicated by the one-way arrow line 8, the analog signal SDi _ n transmitted on the column display negative analog signal line 45 to continue to follow the portion of the positive ramp signal Srp _ n transmitted on the negative ramp signal line 79 identified by the ellipse 47 to produce the electrical signal portion identified by the ellipse 62 as indicated by the one-way arrow line 30,
and if both the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 employ the NMOS type switching capacitance then the high level on the row addressing signal line 24, which is identified by the transfer addressing positive pulse wave signal Sgp output by ellipse 20, will be input to the 6-NMOS gate 127 and cause the 6-NMOS transistor 129 to conduct and cause the respective employed MIM capacitor 115 to be in a pass state with both the column display positive analog signal line 44 and the column display negative analog signal line 45, respectively, and if both the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 employ the PMOS type switching capacitance then the low level on the row addressing signal line 24, which is identified by ellipse 21, will be input to the 6-PMOS gate 123 and cause the 6-PMOS transistor 125 to conduct and cause the respective employed MIM capacitor 115 to be in a pass state with both the column display positive analog signal line 44 and the column display negative analog signal line 45, respectively, and as a result of the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 being in the row addressing storage circuit 46 and the pixel negative addressing storage circuit 60 causing the respective employed MIM capacitor 115 to be in a pass state with the column display positive analog signal line 44 and cause the pixel negative analog signal line 13, which the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 to be identified by the transfer signal line 13, respectively, the column display positive addressing signal line 23, the row addressing circuit 44 and the row addressing circuit 60 to be in a pass state with the real-time,
and the P-pulse wave signal SPn transmitted on the global negative display inverted signal line 31 makes a transition to a high level such that the 5 th-PMOS gate 141 is turned to a high level to cause the 5 th-PMOS transistor 145 to be turned off, while the N-pulse wave signal SNn transmitted on the global negative display positive phase signal line 33 makes a transition to a low level such that the 5 th-NMOS gate 147 is turned to a low level to cause the 5 th-NMOS transistor 149 to be turned off, and thereby cause the negative analog display transmission gate 69 to be in an off state and also cause the pixel analog signal output electrode 26 to generate a level state identified by an ellipse 18 in the above period of time as indicated by a one-way arrow line 14 to continue to be transmitted as a portion identified by an ellipse 19,
if the negative analog display amplifier 70 adopts a PMOS type double-transistor common-drain amplifier, the level of the P pulse wave Vbp2N transmitted on the negative bias voltage supply line 28 jumps up to high level again, and the 1 st to PMOS gate 85 is connected to the power supply line 77 level VD to cause the 1 st to PMOS transistor 88 to turn off, thereby causing the negative analog display amplifier 70 to enter an inactive operating state, and if the negative analog display amplifier 70 adopts an NMOS type double-transistor common-drain amplifier, the level of the N pulse wave Vbn2P transmitted on the negative bias voltage supply line 28 jumps down to low level again, and the 2 nd to NMOS gate 106 is connected to the ground line 135 level VG to cause the 2 nd to NMOS transistor 105 to turn off, thereby causing the negative analog display amplifier 70 to enter an inactive operating state;
and during a period T4: and the counter 8 is reset to zero at the beginning to start counting, the positive slope signal Vrp _ p transmitted on the positive slope signal line 17 is increased from the slope lowest level V1 to the slope highest level V3 in synchronization with the counting speed of the counter 8, the negative slope signal Vrp _ n transmitted on the negative slope signal line 79 is decreased from the slope highest level V3 to the slope lowest level V1 in synchronization with the counting speed of the counter 8,
and the pulse wave signal RST transmitted on the comparator reset signal line 19 continues to maintain the level state for the previous period of time, and the pulse wave signals ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 continue to maintain the level state for the previous period of time, and thus the analog signal SDi _ p transmitted on the column display positive analog signal line 44 continues to generate the corresponding level state following the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17, the analog signal SDi _ n transmitted on the column display negative analog signal line 45 continues to generate the corresponding level state following the positive ramp signal Srp _ n transmitted on the negative ramp signal line 79,
and if the number generated by the counter 8 is equal to the number stored by the digital signal latch 11 when the Tx1 time not longer than the time length of T4 has elapsed, the enable digital signal comparator 12 will trigger to output a low level to the 1 st control line 1, and both the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 will receive the pulse wave signal ENC at the low level identified by the ellipse 24, and then have a low level input to the 3 rd-NMOS gate 66 and have a converted high level input to the 3 rd-PMOS gate 61, so that both the positive ramp signal transmission gate 6 and the negative ramp signal transmission gate 40 are in the off state, and then respectively make the analog signal SDi _ p transmitted on the column display positive analog signal line 44 no longer follow in real time the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 to remain at the fixed level identified by the ellipse 25 until the positive ramp signal transmission gate 52 is in the on state again, and the analog signal SDi _ p transmitted on the column display negative ramp signal line 45 no longer follows the positive ramp signal Srp _ p level identified by the negative ramp signal transmission line 79 until the negative ramp signal transmission gate is maintained at the fixed level 79 again,
and the pixel positive address storage circuit 46 and the pixel negative address storage circuit 60 continue to maintain the input path state because the pulse wave signal transmitted on the row address signal line 24 maintains the level state for the previous period of time, and respectively cause the analog signal SDi _ p transmitted on the column display positive analog signal line 44 to be updated by the identification portion of the ellipse 25 as the analog signal Vsc _ p that intentionally drives the pixel positive storage output terminal 42 as indicated by the one-way arrow line 15 to the fixed-level portion identified by the ellipse 26, and the analog signal SDi _ n transmitted on the column display negative analog signal line 45 to be updated by the identification portion of the ellipse 65 as the analog signal Vsc _ n that intentionally drives the pixel negative storage output terminal 92 as indicated by the one-way arrow line 55 to the fixed-level portion identified by the ellipse 66,
and the level of the positive ramp signal Vrp _ p transmitted on said positive ramp signal line 17 at the termination is incremented up to the ramp signal highest level V3 while the level of the negative ramp signal Vrp _ n transmitted on said negative ramp signal line 79 is decremented down to the ramp signal low level V1, said counter 8 also counts up to the full value,
and the negative analog display amplifier 70 maintains an inactive operation state because the pulse wave signal transmitted on the negative bias voltage supply line 28 continues to the last level state of the last period of time, the negative analog display transfer gate 69 maintains an off state because the P pulse wave signal SPn transmitted on the global negative display inverted signal line 31 and the N pulse wave signal SNn transmitted on the global negative display positive-phase signal line 33 continue to the last level state of the last period of time, and also causes the analog signal Vout output on the pixel analog signal output electrode 26 to continue to the level state identified by the ellipse 19 in the last period of time as indicated by the one-way arrow line 16 to produce the portion identified by the ellipse 27;
then, in the display line period TP11 of the positive field display period T _ P,
in time periods T1, T2, T3, T4: and the positive ramp signal Vrp _ p transmitted on the positive ramp signal line 17, the negative ramp signal Vrp _ n transmitted on the negative ramp signal line 79, and the pulse wave signal RST transmitted on the comparator reset signal line 19 are all repeatedly transmitted in the waveform state in the previous row period,
and if said pixel positive addressing storage circuit 46 and said pixel negative addressing storage circuit 60 both employ said NMOS type switching capacitance then the low level on said row addressing signal line 24 conveying addressing positive pulse wave signal Sgp output identified by ellipse 28 will be input to said 6-NMOS gate 127 and cause said 6-NMOS transistor 129 to turn off and cause said respective employed MIM capacitor 115 to be in an off state with both said column display positive analog signal line 44 and said column display negative analog signal line 45 respectively, and if said pixel positive addressing storage circuit 46 and said pixel negative addressing storage circuit 60 both employ said PMOS type switching capacitance then the high level on said row addressing signal line 24 conveying addressing negative pulse wave signal Sgn output identified by ellipse 29 will be input to said 6-PMOS gate 123 and cause said 6-PMOS transistor 125 to turn off and cause said respective employed MIM capacitor 115 to be in an off state with both said column display positive analog signal line 44 and said column display negative analog signal line 45 respectively and cause said respective employed pixel positive pulse wave signal line 46 and said pixel negative pulse wave signal line 60 to be held in an off state with said column display positive analog signal line 44 and said column display positive analog signal line 45 respectively and said column display positive analog signal line 70 and said pixel negative analog signal line 70 can be held in an off state and said row addressing storage circuit 26 continues to be held in an off state as indicated by an arrow mark T4 and an arrow line output signal line 4 and a unidirectional display signal line can be held continuously,
and during time periods T1, T2, T3: and the pulse wave signal ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 repeatedly transmits the waveform state in the previous row period, and respectively makes the analog signal SDi _ p transmitted on the column display positive analog signal line 44 continuously follow the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 to generate the corresponding level state, and makes the analog signal SDi _ n transmitted on the column display negative analog signal line 45 continuously follow the positive ramp signal Srp _ n transmitted on the negative ramp signal line 79 to generate the corresponding level state,
and during the period T1: and if the positive analog display amplifier 49 employs a PMOS type double-transistor common-drain amplifier, the level of the P-pulse wave Vbp2P transmitted on the positive bias voltage supply line 28 is dropped from a high voltage to a level identified by an ellipse 48, and the positive analog display amplifier 49 is enabled to cause the 1 st PMOS transistor 88 to enter a saturation region because the 1 st PMOS gate 85 is lower than the power supply line 77 level VD to thereby achieve an active operation state, and if the positive analog display amplifier 49 employs an NMOS type double-transistor common-drain amplifier, the level of the N-pulse wave Vbn2P transmitted on the positive bias voltage supply line 28 is dropped from a low level to a level identified by an ellipse 49, and the positive analog display amplifier 49 is enabled to cause the 2 nd NMOS transistor 105 to enter a saturation region because the 2 nd NMOS gate 106 is higher than the ground line 135 level VG to thereby achieve an active operation state, and as a result, the level signal held by the pixel positive addressing storage circuit 46 at the last cycle of the previous row is driven to the positive display transmission input terminal 22 by the positive analog display amplifier 49,
and the P pulse wave signal SPp transmitted on the global positive display inverted signal line 58 is high so that the gate 141 of the 5 th-PMOS transistor 145 is turned off, and the N pulse wave signal SNp transmitted on the global positive display positive phase signal line 29 is low so that the gate 147 of the 5 th-NMOS transistor 147 is turned low to turn off the transistor 149, and further to cause the positive analog display transmission gate 23 to be in the off state and also to cause the level portion of the analog signal Vout output from the pixel analog signal output electrode 26 identified by the ellipse 31 to continue to the level state identified by the ellipse 27 for the previous period of time as indicated by the one-way arrow line 18,
and during a period T2: the positive analog display amplifier 49 continues to maintain the active operation state because the analog signal transmitted on the positive bias voltage supply line 28 maintains the level state for the last period of time,
and the P-pulse wave signal SPp transmitted on the global positive display inverted signal line 58 transitions to a low level so that the 5 th-PMOS gate 141 is turned on so that the 5 th-PMOS transistor 145 is turned on, and the N-pulse wave signal SNp transmitted on the global positive display positive phase signal line 29 transitions to a high level so that the 5 th-NMOS gate 147 is turned on so that the 5 th-NMOS transistor 149 is turned on, and further so that the positive analog display transmission gate 23 is in an on state so that the analog signal Vsc _ P of the pixel positive storage output terminal 42 is driven by the positive analog display amplifier 49 in real time as indicated by an ellipse 30, and the analog signal Vout updating the pixel analog signal output electrode 26 is driven by the positive analog display amplifier 49 as indicated by a one-way arrow line 19 and held in the output electrode parasitic capacitor 20 as indicated by an ellipse 32,
and in time periods T3, T4: and if the positive analog display amplifier 49 is a PMOS type double-transistor common drain amplifier, the level of the P-pulse wave Vbp2P transmitted through the positive bias voltage supply line 28 is again raised to a high level, and the 1 st-PMOS gate 85 is turned on the power supply line 77 level VD to cause the 1 st-PMOS transistor 88 to turn off, thereby causing the positive analog display amplifier 49 to enter an inactive operation state, and if the positive analog display amplifier 49 is an NMOS type double-transistor common drain amplifier, the level of the N-pulse wave Vbn2P transmitted through the positive bias voltage supply line 28 is again lowered to a low level, and the 2 nd-NMOS gate 106 is turned on the ground line 135 level VG to cause the 2 nd-NMOS transistor 105 to turn off, thereby causing the positive analog display amplifier 49 to enter an inactive operation state,
and with the P pulse wave signal SPp transmitted on the global positive display inverted signal line 58 returning to the high level and with the N pulse wave signal SNp transmitted on the global positive display inverted signal line 29 returning to the low level, the positive analog display transmission gate 23 is again brought into the off state so that the level portion of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 33 continues as indicated by the one-way arrow line 20 to the level state identified by the ellipse 32 for the previous period of time,
and when the time Tx2 not exceeding the time length T4 elapses, if the number generated by the counter 8 is equal to the number stored by the digital signal latch 11, it will trigger the enable digital signal comparator 12 to output a low level to the 1 st control line 1, and make both the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 receive a low level of the pulse wave signal ENC, and in turn make the analog signal sdip transmitted on the column display positive analog signal line 44 no longer follow the level change of the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 in real time and remain as the fixed level portion identified by the ellipse 34 until the positive ramp signal transmission gate 52 is put into the on-state again, and the analog signal sdin transmitted on the column display negative analog signal line 45 no longer follow the level change of the negative ramp signal Srp _ n transmitted on the negative ramp signal line 79 in real time and remain as the fixed level portion identified by the ellipse 74 until the negative ramp signal transmission gate 40 is put into the on-state again,
and the level of the positive ramp signal Vrp _ p transmitted on the positive ramp signal line 17 at the termination is incremented to the ramp signal highest level V3 while the level of the negative ramp signal Vrp _ n transmitted on the negative ramp signal line 79 is decremented to the ramp signal low level V1, and the counter 8 also counts up to the full value;
then, in the address line period TC21 of the negative field display period T _ N,
in time periods T1, T2, T3, T4: and the positive ramp signal Vrp _ P transmitted on the positive ramp signal line 17, the negative ramp signal Vrp _ N transmitted on the negative ramp signal line 79, the pulse wave signal RST transmitted on the comparator reset signal line 19, the pulse wave signal transmitted on the positive bias voltage supply line 28, the pulse wave signal transmitted on the negative bias voltage supply line 28, the N pulse wave signal SNp transmitted on the global positive display positive-phase signal line 29, the P pulse wave signal SPp transmitted on the global positive display inverted signal line 58, the N pulse wave signal SNn transmitted on the global negative display positive-phase signal line 33, the P pulse wave signal SPn transmitted on the global negative display inverted signal line 31 are repeated to transmit the waveform state transmitted in the display line period of the adjacent positive field display period T _ P,
and during time periods T1, T2, T3: and the pulse wave signal ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 repeatedly transmits the waveform state in the previous row period, and respectively makes the analog signal SDi _ p transmitted on the column display positive analog signal line 44 continuously follow the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 to generate the corresponding level state, and makes the analog signal SDi _ n transmitted on the column display negative analog signal line 45 continuously follow the positive ramp signal Srp _ n transmitted on the negative ramp signal line 79 to generate the corresponding level state,
and in time periods T1 and T2: and when the pulse wave signal transmitted on the row addressing signal line 24 occurs in the level state of the same time period adjacent to the positive field display period T _ N addressing row period TC11, both the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 maintain the input off state and respectively cause the level state of the analog signal Vsc _ p at the pixel positive storage output 42 identified by the ellipse 30 in the previous time period to continue to be transferred for storage and output as indicated by the one-way arrow line 21 and the portion of the analog signal Vsc _ N at the pixel negative storage output 92 identified by the ellipse 70 in the previous time period to continue to be transferred for storage and output as indicated by the one-way arrow line 61 and the portion of the analog signal Vsc _ N at the pixel negative storage output 75,
and during the period T1: and the positive analog display amplifier 49 starts to enter the active operation state because the analog signal transmitted on the forward bias voltage supply line 28 remains in the level state for the previous period of time, and the positive analog display transfer gate 23 continues to be in the off state because the levels at the end of the previous period of time of the P pulse wave signal SPp transmitted on the global positive display inverted phase signal line 58 and the N pulse wave signal SNp transmitted on the global positive display normal phase signal line 29 continue to be in the off state so that the level portion of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 33 continues to remain in the level state where the output electrode parasitic capacitor 20 is identified by the ellipse 36 for the previous period of time as indicated by the one-way arrow line 22,
and during a period T2: and the positive analog display amplifier 49 continues to maintain the active operation state because the pulse wave signal transmitted on the forward bias voltage supply line 28 maintains the level state for the previous period of time, and the P pulse wave signal SPp transmitted on the global positive display inverted signal line 58 jumps to the low level while the N pulse wave signal SNp transmitted on the global positive display non-inverted signal line 29 jumps to the high level so that the on-state of the positive analog display transmission gate 23 will cause the analog signal Vsc _ P level of the pixel positive storage output terminal 42 to be identified by the ellipse 35, and the portion thereof which is indicated by the one-way arrow line 23 will drive the pixel analog signal output electrode 26 in real time through the positive analog display amplifier 49 to generate and maintain the level state of the output electrode parasitic capacitor 20 as identified by the ellipse 37 to enhance the level state of the portion identified by the ellipse 36,
and in the time period T3 and T4: and when the pulse wave signal transmitted on the row addressing signal line 24 occurs in a level state of the same time period as the addressing row period TC11 of the positive field display period T _ N, both the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 enter and remain in an on state, and respectively cause the analog signal SDi _ p transmitted on the column display positive analog signal line 44 to be updated by the analog signal Vsc _ p, indicated by the one-way arrow line 24, driving the pixel positive storage output 42 to a fixed level portion, indicated by the ellipse 39, by the identified portion of ellipse 38, the analog signal SDi _ N transmitted on the column display negative analog signal line 45 to be updated by the analog signal Vsc _ N, indicated by the one-way arrow line 56, driving the pixel negative storage output 92 to a fixed level portion, indicated by the ellipse 79,
and when the pulse wave signal transmitted on the positive bias voltage supply line 28 is in a level state of the same period of the display line period adjacent to the positive field display period T _ N, the positive analog display amplifier 49 enters an inactive state, and the P pulse wave signal SPp transmitted on the global positive display inverted signal line 58 is restored to the high level while the N pulse wave signal SNp transmitted on the global positive display normal phase signal line 29 is restored to the low level so that the positive analog display transfer gate 23 is again in the off state to cause the level portion of the analog signal Vout output from the pixel analog signal output electrode 26 identified by the ellipse 40 to continue to the level state identified by the ellipse 37 for the previous period of time as indicated by the one-way arrow line 25,
and if the number generated by the counter 8 is equal to the number stored by the digital signal latch 11 when Ty1 time not longer than the time length of T4 elapses, the enable digital signal comparator 12 will be triggered to output a low level to the 1 st control line 1 and cause the analog signal SDi _ p transmitted on the column display positive analog signal line 44 to no longer follow in real time the level change of the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 and remain at the fixed level portion identified by the ellipse 38 until the positive ramp signal transmission gate 52 is again in the on-state, the analog signal SDi _ n transmitted on the column display negative analog signal line 45 no longer follows in real time the level change of the negative ramp signal Srp _ n transmitted on the negative ramp signal line 79 and remain at the fixed level portion identified by the ellipse 78 until the negative ramp signal transmission gate 40 is again in the on-state,
and the level of the positive ramp signal Vrp _ p transmitted on the positive ramp signal line 17 at the termination is incremented to the ramp signal highest level V3 while the level of the negative ramp signal Vrp _ n transmitted on the negative ramp signal line 79 is decremented to the ramp signal low level V1, and the counter 8 also counts up to the full value;
then, in the display line period TP21 of the negative field display period T _ N,
in time periods T1, T2, T3, T4: and the positive ramp signal Vrp _ P transmitted on the positive ramp signal line 17, the negative ramp signal Vrp _ N transmitted on the negative ramp signal line 79, the pulse wave signal RST transmitted on the comparator reset signal line 19, the pulse wave signal transmitted on the positive bias voltage supply line 28, the pulse wave signal transmitted on the negative bias voltage supply line 28, the N pulse wave signal SNp transmitted on the global positive display positive-phase signal line 29, the P pulse wave signal SPp transmitted on the global positive display inverted signal line 58, the N pulse wave signal SNn transmitted on the global negative display positive-phase signal line 33, the P pulse wave signal SPn transmitted on the global negative display inverted signal line 31 are each repeatedly transmitted in a waveform state transmitted in the address row period TC11 of the preceding adjacent positive field display period T _ P,
and the transmission of the addressing positive pulse wave signal Sgp on the row addressing signal line 24 being held at the low level indicated by the ellipse 81 and the transmission of the addressing negative pulse wave signal Sgn on the row addressing signal line 24 being held at the high level indicated by the ellipse 42 will cause the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 to both always remain in the input off-state and cause the level state of the analog signal Vsc _ p at the pixel positive storage output 42 respectively identified by the ellipse 39 during the last row period T4 to continue to be stored and output as the identified portion of the ellipse 43 as indicated by the one-way arrow line 26 and the level state of the analog signal Vsc _ n at the pixel negative storage output 92 indicated by the ellipse 79 to continue to be stored and output as the identified portion of the ellipse 83 as indicated by the one-way arrow line 66,
and during periods T1, T2, T3: and the pulse wave signal ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 repeatedly transmits the waveform state in the previous row period, and respectively makes the analog signal SDi _ p transmitted on the column display positive analog signal line 44 continuously follow the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 to generate the corresponding level state, and makes the analog signal SDi _ n transmitted on the column display negative analog signal line 45 continuously follow the positive ramp signal Srp _ n transmitted on the negative ramp signal line 79 to generate the corresponding level state,
and during the period T1: and the negative analog display amplifier 70 enters an active operating state because the transfer of the active level is started on the negative bias voltage supply line 57, and the positive analog display transfer gate 23 continues to be in the off state for the end of the period of time because the level of the P pulse wave signal SPp transferred on the global positive display inverted signal line 58 and the N pulse wave signal SNp transferred on the global positive display positive phase signal line 29 continue to be in the off state so that the level portion of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 44 continues to be maintained in the level state of the output electrode parasitic capacitor 20 identified by the ellipse 40 for the last period of time as indicated by the one-way arrow line 27,
and during a period T2: and the positive analog display amplifier 49 continues to maintain the active operation state because the analog signal transmitted on the positive bias voltage supply line 28 maintains the level state for the last period of time,
and with the P-pulse wave signal SPn transmitted on the global negative display inverted signal line 31 transitioning to a low level and the N-pulse wave signal SNn transmitted on the global negative display positive signal line 33 transitioning to a high level and in turn causing the negative analog display transfer gate 69 to be in an on state causing the portion of the analog signal Vsc _ N level of the pixel negative storage output terminal 92 identified by the ellipse 83 to drive the pixel analog signal output electrode 26 in real time as indicated by the one-way arrow line 28 through the negative analog display amplifier 70 and to generate and hold the level state of the output electrode parasitic capacitor 20 as identified by the ellipse 45 to update the level state of the portion identified by the ellipse 44,
and in time periods T3, T4: the negative analog display amplifier 70 enters an inactive operating state because the transfer inactive level is restored on the negative bias voltage supply line 57,
and with the P pulse wave signal SPn transmitted on the global negative display inverted signal line 31 returning to the high level and with the N pulse wave signal SNn transmitted on the global negative display positive signal line 33 returning to the low level and thereby causing the negative analog display transmission gate 69 to be in the off state causes the level portion of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 45 to continue to the level state identified by the ellipse 46 for the previous period of time as indicated by the one-way arrow line 29,
and if the number generated by the counter 8 equals the number stored by the digital signal latch 11 when Ty2 time not exceeding the time length of T4 has elapsed, the enable digital signal comparator 12 will trigger the enable digital signal comparator 12 to output a low level to the 1 st control line 1 and cause the analog signal SDi _ p transmitted on the column display positive analog signal line 44 to no longer follow in real time the level change of the positive ramp signal Srp _ p transmitted on the positive ramp signal line 17 and remain as the fixed level portion identified by the ellipse 41 until the positive ramp signal transmission gate 52 is again in the on-state, the analog signal SDi _ n transmitted on the column display negative analog signal line 45 will no longer follow in real time the level change of the negative ramp signal Srp _ n transmitted on the negative ramp signal line 79 and remain as the fixed level portion identified by the ellipse 87 until the negative ramp signal transmission gate 40 is again in the on-state,
and the level of the positive ramp signal Vrp _ p transmitted on said positive ramp signal line 17 at the termination is incremented to the ramp signal highest level V3 while the level of the negative ramp signal Vrp _ n transmitted on said negative ramp signal line 79 is decremented to the ramp signal low level V1, said counter 8 also counts up to the full value,
as a result, the waveform of the analog signal Vout output to the pixel analog signal output electrode 26 is characterized by being divided into a positive field display section composed of a section identified by at least an ellipse 32, an ellipse 33 generated in the line display period of the positive field display period and a section identified by an ellipse 36, an ellipse 37, an ellipse 40 generated in the line address period of the adjacent negative field display period and a section identified by an ellipse 44 generated in the line display period T1 period of the negative field display period, a negative field display section composed of a section identified by at least an ellipse 45, an ellipse 46 generated in the line display period of the negative field display period and a section identified by an ellipse 6, an ellipse 18, an ellipse 19, an ellipse 27 generated in the line address period of the adjacent positive field display period and a section identified by an ellipse 31 generated in the line display period T1 period of the positive field display period,
and the driving method further includes: the four time periods T1, T2, T3 and T4 in each row period are sequentially performed and then cyclically repeated, so that each display period can output an analog level corresponding to the number stored in the digital signal latch 11 in the row addressing period of the current display period at the pixel analog signal output electrode 26.
It should be understood that the present invention is not limited to the embodiments described herein, and that modifications and variations apparent to those skilled in the art in light of the above teachings are intended to be included within the scope of the present invention.

Claims (9)

1. Two-way symmetry slope type analog pixel drive circuit, characterized by: the circuit is composed of a digital signal latch, a counter, an enable digital signal comparator, a positive ramp signal amplifier, a positive ramp signal transfer gate, a pixel positive addressing storage circuit, a positive analog display amplifier, a positive analog display transfer gate, a negative ramp signal amplifier, a negative ramp signal transfer gate, a pixel negative addressing storage circuit, a negative analog display amplifier, a negative analog display transfer gate, a pixel output electrode circuit, and a display digital signal input bus, a comparator reset signal line, a positive ramp signal line, a negative ramp signal line, a ramp bias voltage supply line, a row addressing signal line, a positive bias voltage supply line, a negative bias voltage supply line, a global positive display positive phase signal line, a global positive display reverse phase signal line, a global negative display positive phase signal line, a global negative display reverse phase signal line, a column display positive analog signal line, and a column display negative analog signal line,
and the positive slope signal line, the positive slope signal amplifier, the positive slope signal transmission gate, the column display positive analog signal line, the pixel positive addressing storage circuit, the positive analog display amplifier and the positive analog display transmission gate are electrically connected in series to form a functional circuit to process the positive slope signal constructed by connecting four sections of waveforms,
and the negative slope signal line, the negative slope signal amplifier, the negative slope signal transmission gate, the column display negative analog signal line, the pixel negative addressing storage circuit, the negative analog display amplifier and the negative analog display transmission gate are electrically connected in series to form another functional circuit to process the negative slope signal constructed by connecting four sections of waveforms,
and the positive analog display transmission gate and the negative analog display transmission gate both output level signals to the pixel output electrode circuit, and the digital signal latch has the same number of bits as the counter, and is further configured with: the 2 nd connecting wire, the 5 th connecting wire, the 6 th connecting wire, reset connecting wire, the 1 st control line, power supply line, earth connection, just the digital signal latch passes through the 2 nd connecting wire receive by show the multi-bit digital signal of digital signal input bus transmission stores, just enable the digital signal comparator through the 5 th connecting wire receive by the multi-bit count digital signal that the counter sent, through the 6 th connecting wire receive by the multi-bit storage digital signal that the digital signal latch sent, through the reset connecting wire receive by the reset level signal that the comparator reset signal line sent, through the 1 st control line positive slope signal transmission gate with negative slope signal transmission gate sends the control level signal.
2. A two-way symmetric ramp type analog pixel driving circuit according to claim 1, wherein: the positive slope signal amplifier is configured with a positive slope amplification bias terminal, a positive slope amplification input terminal, a positive slope amplification output terminal, and the positive slope signal transmission gate is configured with a positive slope transmission control terminal, a positive slope transmission input terminal, a positive slope transmission output terminal, and the pixel positive addressing storage circuit is configured with a pixel positive addressing control terminal, a pixel positive storage input terminal, a pixel positive storage output terminal, and the positive analog display amplifier is configured with a positive display amplification bias terminal, a positive display amplification input terminal, a positive display amplification output terminal, and the positive analog display transmission gate is configured with a positive display transmission reverse phase control terminal, a positive display transmission input terminal, a positive display transmission output terminal, and the negative slope signal amplifier is configured with a negative slope amplification bias terminal, a negative slope amplification input terminal, and the negative slope signal transmission gate is configured with a negative slope transmission control terminal, a negative slope transmission input terminal, a negative slope transmission output terminal, and the pixel negative addressing storage circuit is configured with a pixel negative addressing control terminal, a pixel negative slope amplification input terminal, a negative slope amplification output terminal, a negative slope transmission output terminal, and a negative analog display output terminal,
and the enabling digital signal comparator is provided with a high level output to the 1 st control line when the rising edge of the enabling signal transmitted on the comparator resetting signal line is received through the resetting connection line and a low level output to the 1 st control line when the digital signal received from the digital signal latch through the 6 th connection line is compared with the digital signal received from the counter through the 5 th connection line and the two digital signals are the same.
3. A two-way symmetric ramp type analog pixel driving circuit according to claim 1, wherein: the positive slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P type amplifier offset end as the positive slope amplification offset end, a P type amplifier input end as the positive slope amplification input end and a P type amplifier output end as the positive slope amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N type amplifier offset end as the positive slope amplification offset end, an N type amplifier input end as the positive slope amplification input end and an N type amplifier output end as the positive slope amplification output end, the positive slope amplification offset end is connected with the slope bias voltage supply line, and the positive slope amplification input end is connected with the positive slope signal line,
the positive slope signal transmission gate is composed of a 1 st analog signal transmission gate which adopts a 1 st analog transmission gate control end as the positive slope transmission control end, a 1 st analog transmission gate input end as the positive slope transmission input end and a 1 st analog transmission gate output end as the positive slope transmission output end, the positive slope transmission input end is connected with the positive slope amplification output end, and the positive slope transmission output end is connected with the column display positive analog signal line;
the negative slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P-type amplifier offset end as the negative slope amplification offset end, a P-type amplifier input end as the negative slope amplification input end and a P-type amplifier output end as the negative slope amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N-type amplifier offset end as the negative slope amplification offset end, an N-type amplifier input end as the negative slope amplification input end and an N-type amplifier output end as the negative slope amplification output end, the negative slope amplification offset end is connected with the slope bias voltage supply line, and the negative slope amplification output end is connected with the negative slope signal line,
the negative slope signal transmission gate is composed of a 1 st analog signal transmission gate which adopts a 1 st analog transmission gate control end as the negative slope transmission control end, a 1 st analog transmission gate input end as the negative slope transmission input end and a 1 st analog transmission gate output end as the negative slope transmission output end, the negative slope transmission input end is connected with the negative slope amplification output end, and the negative slope transmission output end is connected with the column display negative analog signal line;
wherein the 1 st analog signal transmission gate is composed of a 3 rd PMOS transistor at least comprising a 3 rd PMOS gate, a 3 rd PMOS drain and a 3 rd PMOS source, a 3 rd NMOS transistor at least comprising a 3 rd NMOS gate, a 3 rd NMOS drain and a 3 rd NMOS source, a 4 th PMOS transistor at least comprising a 4 th PMOS gate, a 4 th PMOS drain and a 4 th PMOS source, and a 4 th NMOS transistor at least comprising a 4 th NMOS gate, a 4 th NMOS drain and a 4 th NMOS source, and is further configured with: the 4 th-NMOS gate, the 4 th-PMOS gate and the 3 rd-NMOS gate are connected to form the control end of the 1 st analog transmission gate, the 4 th-NMOS source, the 4 th-PMOS drain and the 3 rd-PMOS gate are connected with each other, the 4 th-PMOS source is connected to the power supply line, the 4 th-NMOS drain is connected to the ground line, the 3 rd-PMOS drain and the 3 rd-NMOS source are connected to form the input end of the 1 st analog transmission gate, and the 3 rd-PMOS source and the 3 rd-NMOS drain are connected to form the output end of the 1 st analog transmission gate.
4. The two-way symmetric ramp-type analog pixel driving circuit according to claim 1, wherein: the pixel positive addressing storage circuit is composed of one of a P-type switch capacitor control end serving as the pixel positive addressing control end, a P-type switch capacitor input end serving as the pixel positive storage input end, a P-type switch capacitor output end serving as a PMOS-type switch capacitor of the pixel positive storage output end or an N-type switch capacitor control end serving as the pixel positive addressing control end, an N-type switch capacitor input end serving as the pixel positive storage input end and an N-type switch capacitor output end serving as an NMOS-type switch capacitor of the pixel positive storage output end, the pixel positive addressing control end is connected with the row addressing signal line, the pixel positive storage input end is connected with the column display positive analog signal line,
the positive analog display amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P-type amplifier offset end as the positive display amplification offset end, a P-type amplifier input end as the positive display amplification input end and a P-type amplifier output end as the positive display amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N-type amplifier offset end as the positive display amplification offset end, an N-type amplifier input end as the positive display amplification input end and an N-type amplifier output end as the positive display amplification output end, the positive display amplification input end is connected with the pixel positive storage output end, and the positive display amplification offset end is connected with the positive bias voltage supply line;
the pixel negative addressing storage circuit is composed of one of a P-type switch capacitor control end serving as the pixel negative addressing control end, a P-type switch capacitor input end serving as the pixel negative storage input end, a P-type switch capacitor output end serving as a PMOS-type switch capacitor of the pixel negative storage output end or an N-type switch capacitor control end serving as the pixel negative addressing control end, an N-type switch capacitor input end serving as the pixel negative storage input end, and an N-type switch capacitor output end serving as an NMOS-type switch capacitor of the pixel negative storage output end, the pixel negative addressing control end is connected with the row addressing signal line, the pixel negative storage input end is connected with the column display negative analog signal line,
and the negative analog display amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P-type amplifier bias end as the negative display amplification bias end, a P-type amplifier input end as the negative display amplification input end and a P-type amplifier output end as the negative display amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N-type amplifier bias end as the negative display amplification bias end, an N-type amplifier input end as the negative display amplification input end and an N-type amplifier output end as the negative display amplification output end, the negative display amplification input end is connected with the pixel negative storage output end, and the negative display amplification bias end is connected with the negative bias voltage supply line.
5. A two-way symmetric ramp type analog pixel driving circuit according to claim 1, wherein: the positive analog display transmission gate is composed of a 2 nd analog signal transmission gate which adopts a 2 nd analog transmission gate positive phase control end as the positive display transmission positive phase control end, a 2 nd analog transmission gate reverse phase control end as the positive display transmission reverse phase control end, a 2 nd analog transmission gate input end as the positive display transmission input end and a 2 nd analog transmission gate output end as the positive display transmission output end, the positive display transmission input end is connected with the positive display amplification output end, the positive display transmission positive phase control end is connected with the global positive display positive phase signal line, and the positive display transmission reverse phase control end is connected with the global positive display reverse phase signal line;
the negative analog display transmission gate is composed of a 2 nd analog signal transmission gate which adopts a 2 nd analog transmission gate positive phase control end as the negative display transmission positive phase control end, a 2 nd analog transmission gate reverse phase control end as the negative display transmission reverse phase control end, a 2 nd analog transmission gate input end as the negative display transmission input end and a 2 nd analog transmission gate output end as the negative display transmission output end, the negative display transmission input end is connected with the negative display amplification output end, the negative display transmission positive phase control end is connected with the global negative display positive phase signal line, the negative display transmission reverse phase control end is connected with the global negative display reverse phase signal line,
the 2 nd analog signal transmission gate is composed of a 5 th-PMOS tube at least comprising a 5 th-PMOS grid electrode, a 5 th-PMOS drain electrode and a 5 th-PMOS tube at least comprising a 5 th-NMOS grid electrode, a 5 th-NMOS drain electrode and a 5 th-NMOS source electrode, the 5 th-PMOS drain electrode is connected with the 5 th-NMOS source electrode to form the input end of the 2 nd analog transmission gate, the 5 th-NMOS drain electrode is connected with the 5 th-PMOS source electrode to form the output end of the 2 nd analog transmission gate, the 5 th-PMOS grid electrode serves as the inverting control end of the 2 nd analog transmission gate, and the 5 th-NMOS grid electrode serves as the non-inverting control end of the 2 nd analog transmission gate;
and the pixel output electrode circuit is constructed by an output electrode parasitic capacitor formed between the pixel analog signal output electrode and a conductor which is close to the periphery but does not make contact and is connected to the ground line, and the pixel analog signal output electrode serves as one electrode plate of the output electrode parasitic capacitor, the ground line serves as the other electrode plate of the output electrode parasitic capacitor,
and the pixel analog signal output electrode is respectively connected with the negative display transmission output end and the positive display transmission output end.
6. A two-way symmetric ramp-type analog pixel driving circuit according to claim 3, wherein: the PMOS type double-tube common-drain amplifier is composed of a 1 st PMOS tube at least comprising a 1 st PMOS gate, a 1 st PMOS source and a 1 st PMOS drain and a 2 nd PMOS tube at least comprising a 2 nd PMOS gate, a 2 nd PMOS source and a 2 nd PMOS drain, wherein the 1 st PMOS gate serves as a bias end of the P type amplifier, the 2 nd PMOS gate serves as an input end of the P type amplifier, the 1 st PMOS drain is connected with the 2 nd PMOS source to form an output end of the P type amplifier, the 1 st PMOS source is connected to the power supply line, and the 2 nd PMOS drain is connected to the grounding line;
the NMOS type double-tube common-drain amplifier is composed of a 1 st NMOS tube at least comprising a 1 st NMOS grid electrode, a 1 st NMOS drain electrode and a 1 st NMOS source electrode and a 2 nd NMOS tube at least comprising a 2 nd NMOS grid electrode, a 2 nd NMOS drain electrode and a 2 nd NMOS source electrode, wherein the 2 nd NMOS grid electrode is used as the bias end of the N type amplifier, the 1 st NMOS grid electrode is used as the input end of the N type amplifier, the 2 nd NMOS drain electrode is connected with the 1 st NMOS source electrode to form the output end of the N type amplifier, the 1 st NMOS drain electrode is connected to the power supply line, and the 2 nd NMOS source electrode is connected to the grounding line.
7. The two-way symmetric ramp type analog pixel driving circuit according to claim 4, wherein: the PMOS type switch capacitor is composed of a 6 th PMOS tube at least comprising a 6 th-PMOS grid electrode, a 6 th-PMOS drain electrode and a 6 th-PMOS source electrode and a MIM capacitor at least comprising a MIM capacitor upper polar plate and a MIM capacitor lower polar plate, the 6 th-PMOS grid electrode is used as the P type switch capacitor control end, the 6 th-PMOS source electrode is used as the P type switch capacitor input end, the 6 th-PMOS drain electrode is connected with the MIM capacitor upper polar plate to form the P type switch capacitor output end, and the MIM capacitor lower polar plate is connected to the grounding wire;
the NMOS type switch capacitor is composed of a 6-NMOS tube at least comprising a 6-NMOS grid electrode, a 6-NMOS drain electrode and a 6-NMOS source electrode and a MIM capacitor at least comprising a MIM capacitor upper polar plate and a MIM capacitor lower polar plate, the 6-NMOS grid electrode serves as the N type switch capacitor control end, the 6-NMOS drain electrode serves as the N type switch capacitor input end, the 6-NMOS source electrode is connected with the MIM capacitor upper polar plate to form the N type switch capacitor output end, and the MIM capacitor lower polar plate is connected to the grounding wire.
8. A driving method of a two-way symmetrical ramp type analog pixel driving circuit according to any one of claims 1 to 7, characterized by: any one display period is formed by a positive field display period and a negative field display period which are adjacent to each other, the positive field display period and the negative field display period are respectively formed by an addressing line period which can enable the pixel positive addressing storage circuit and the pixel negative addressing storage circuit to have an input on-state and at least one display line period which always enables the pixel positive addressing storage circuit and the pixel negative addressing storage circuit to keep an input off-state, the addressing line period is the same as, time-connected with and commonly called as a line period, the positive ramp signal amplifier and the negative ramp signal amplifier are configured to be in an active working state by a bias level transmitted on the ramp bias voltage supply line in each line period, the negative analog display transmission gate is in an off-state and the negative analog display amplifier is in an inactive working state in all display line periods of the positive field display period and the addressing line period of the negative field display period, and the positive analog display transmission gate is in an off-state and the positive analog display amplifier is in an inactive working state in all display line periods of the negative field display period and the positive field display period and the addressing line period of the positive field display period,
each row period is divided into four time periods T1, T2, T3 and T4, two kinds of positive slope signals and two kinds of negative slope signals which are respectively constructed by connecting four wave forms are configured, the highest levels of the positive slope signals and the negative slope signals are the same as the highest level of the slope, the center levels of the positive slope signals and the negative slope signals are the same as the center level of the slope, the lowest levels of the negative slope signals are the same as the lowest level of the slope, in addition, in each row period, the positive slope signals jump from the highest level of the slope to the center level of the slope in the T1 time period, the negative slope signals jump from the lowest level of the slope to the center level of the slope in the T2 time period, the positive slope signals and the negative slope signals are fixed as the center level of the slope in the T3 time period, the positive slope signals jump from the center level of the slope to the lowest level of the slope and the negative slope signals jump from the center level of the slope to the highest level of the slope in the T4 time period, and the negative slope signals gradually decrease from the highest level of the slope to the lowest slope.
9. The driving method of a two-way symmetric ramp type analog pixel driving circuit according to claim 8, wherein: the four time periods T1, T2, T3 and T4 in each row period are performed sequentially and then circulate, so that each display period can output a pair of analog levels corresponding to the numbers stored by the digital signal latch in the row addressing period of the current display period at the pixel analog signal output electrode.
CN202210517668.8A 2022-05-13 2022-05-13 Double-path symmetrical slope type analog pixel driving circuit and driving method thereof Active CN114743518B (en)

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