CN114743518B - Double-path symmetrical slope type analog pixel driving circuit and driving method thereof - Google Patents

Abstract

The dual-channel symmetrical slope type analog pixel driving circuit and its driving method belong to the technical field of integrated circuits, and are composed of a digital signal latch, a counter, an enabling digital signal comparator, a positive slope signal amplifier, a positive slope signal transmission gate, and a pixel positive seeker. address storage circuit, positive analog display amplifier, positive analog display transmission gate, negative slope signal amplifier, negative slope signal transmission gate, pixel negative addressing storage circuit, negative analog display amplifier, negative analog display transmission gate, pixel output electrode circuit, connection Composed of signal lines and a driving method including dual-channel symmetrical four-segment wave-type ramp signals, it has a digital-to-analog conversion function, and not only combines the behavior of addressing and sampling analog signal levels in the same pixel circuit with the display drive output analog signal level Behavior allocation occurs in different time periods, which avoids the interference of electrical signals caused by the conflict between the two behaviors in timing, and can alternately output a pair of analog levels.

Description

Dual-channel symmetrical slope type analog pixel drive circuit and its drive method

technical field

The invention belongs to the application field of silicon-based display chip circuits of integrated circuit technology, and in particular relates to the field of silicon-based display driving circuits of dual-path symmetrical slope type analog pixels.

Background technique

Monocrystalline silicon planar device manufacturing technology is integrated with liquid crystal (LCD, Liquid Crystal Display) technology, organic light-emitting diode (OLED, Organic Light-Emitting Diode) technology and other active or passive display technologies to produce various silicon-based displays. For example, the silicon-liquid crystal-glass "sandwich" structural device technology combined with liquid crystal display technology produces a new type of reflective LCD display device. It first uses metal oxide semiconductors (metal oxide semiconductors) on single crystal silicon wafers. MOS (Metal Oxide Semiconductor) process to manufacture a silicon substrate containing an active addressing matrix chip, and then coat a smooth metal layer as a reflective mirror and as a so-called pixel output electrode, and then combine the silicon substrate with a glass substrate containing a transparent electrode Keep a distance of a few microns for bonding, where the transparent electrode of the glass substrate becomes the so-called common electrode, and finally pour liquid crystal material into the distance of a few microns to construct a reflective LCD screen. In fact, the level on the pixel output electrode will establish an electric field between the level on the common electrode of the liquid crystal pixel, so by modulating the level output from each pixel unit circuit on the silicon substrate to the pixel output electrode, the liquid crystal material can be controlled. Image display is realized for the intensity (gray scale) of the reflected light amplitude. (Chris Chinnock. "Microdisplays and Manufacturing Infrastructure Mature at SID2000" "Information Display", September 2000, P18).

Usually, the pixel unit circuit of the active addressing matrix of the chip is composed of an N-channel Metal Oxide Semiconductor (NMOS, N-channel Metal Oxide Semiconductor) transistor and a capacitor connected in series (R.Ishii, S.Katayama, H .Oka, S.yamazaki, S.lino "U.Efron, I.David, V.Sinelnikov, B.Apter "ACMOS/LCOS Image Transceiver Chip for Smart Goggle Applications" "IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY", Vol. 14 , No. 2, February 2004, P269), in which the gate of the NMOS transistor is connected to the output terminal of the addressing signal of the row scanner. However, when a single NMOS transistor transmits a high level, not only the threshold voltage loss occurs, but also the instantaneous State characteristics are also not ideal (edited by Chen Guican et al., "CMOS Integrated Circuit Design", Xi'an Jiaotong University Press, 1999.9, P110).

Contents of the invention

The invention proposes a digital signal latch, a counter, an enabling digital signal comparator, a positive ramp signal amplifier, a positive ramp signal transmission gate, a pixel positive addressing storage circuit, a positive analog display amplifier, and a positive analog display transmission gate , negative slope signal amplifier, negative slope signal transmission gate, pixel negative addressing storage circuit, negative analog display amplifier, negative analog display transmission gate, pixel output electrode circuit and display digital signal input bus, comparator reset signal line, positive slope signal line, negative slope signal line, slope bias voltage supply line, row addressing signal line, positive bias voltage supply line, negative bias voltage supply line, global positive display positive phase signal line, global positive display negative phase signal line, Global negative display positive-phase signal line, global negative display negative-phase signal line, column display positive analog signal line, column display negative analog signal line, the second connection line, the fifth connection line, the sixth connection line, the reset connection line, the first 1. A dual-channel symmetrical ramp-type analog pixel drive circuit composed of control lines and a driving method including a dual-channel symmetrical four-segment waveform ramp signal. It has a digital-to-analog conversion function and displays positive analog signal lines and column displays in each group of columns. The negative analog signal lines are equipped with double-tube common-drain amplifiers, objectively starting from the circuit structure to isolate the electrical signal crosstalk between each column display positive analog signal line and each column display negative analog signal line, and the driving method includes Dual-channel symmetrical four-segment wave-type ramp signal and its drive cycle method allocate the behavior of addressing and sampling the analog signal level in the same pixel circuit and the behavior of displaying the output analog signal level to occur in different time periods, avoiding timing It eliminates the mutual interference of electrical signals caused by the conflict between these two behaviors, and can alternately output a pair of analog levels.

Technical scheme of the present invention is:

The dual-way symmetrical slope type analog pixel driving circuit consists of a digital signal latch, a counter, an enable digital signal comparator, a positive slope signal amplifier, a positive slope signal transmission gate, a pixel positive addressing storage circuit, a positive analog display amplifier, a positive analog Display transmission gate, negative slope signal amplifier, negative slope signal transmission gate, pixel negative addressing storage circuit, negative analog display amplifier, negative analog display transmission gate, pixel output electrode circuit and display digital signal input bus, comparator reset signal line, Positive ramp signal line, negative ramp signal line, ramp bias voltage supply line, row addressing signal line, positive bias voltage supply line, negative bias voltage supply line, global positive display positive phase signal line, global positive display reverse phase The signal line, the global negative display positive phase signal line, the global negative display reverse signal line, the column display positive analog signal line, and the column display negative analog signal line are composed together, and have the positive slope signal line, the positive slope signal amplifier , the positive slope signal transmission gate, the column display positive analog signal line, the pixel positive addressing storage circuit, the positive analog display amplifier, and the positive analog display transmission gate are electrically connected in series to form a functional circuit for processing The positive ramp signal is constructed by connecting four sections of waveforms, and has the negative ramp signal line, the negative ramp signal amplifier, the negative ramp signal transmission gate, the column display negative analog signal line, and the pixel negative addressing The storage circuit, the negative analog display amplifier, and the negative analog display transmission gate are electrically connected in series to form another functional circuit to process the negative ramp signal constructed by connecting four waveforms, and the positive analog display transmission gate and the negative analog display The analog display transmission gates output level signals to the pixel output electrode circuit, and the number of digits of the digital signal latch is the same as the number of digits of the counter, and it is also equipped with: a second connection line, a fifth connection line, the sixth connection line, the reset connection line, the first control line, the power supply line, the ground line, and the digital signal latch receives the multiple signals transmitted by the display digital signal input bus through the second connection line The digital signal is stored, and the enabled digital signal comparator receives the multi-bit counting digital signal sent by the counter through the fifth connection line, and receives the digital signal latched by the sixth connection line through the sixth connection line. The multi-bit storage digital signal sent by the comparator, the reset level signal sent by the reset signal line of the comparator is received through the reset connection line, and the positive ramp signal is transmitted to the gate and the negative ramp signal through the first control line. The ramp signal transmission gate sends the control level signal,

Wherein, the positive slope signal amplifier is configured with a positive slope amplification bias terminal, a positive slope amplification input terminal, and a positive slope amplification output terminal, and the positive slope signal transmission gate is configured with a positive slope transmission control terminal and a positive slope transmission input terminal , a positive slope transmission output terminal, and the pixel positive addressing storage circuit is configured with a pixel positive addressing control terminal, a pixel positive storage input terminal, and a pixel positive storage output terminal, and the positive analog display amplifier is configured with a positive display amplification bias setting terminal, positive display amplification input terminal, positive display amplification output terminal, and the positive analog display transmission gate is configured with a positive display transmission inversion control terminal, a positive display transmission positive phase control terminal, a positive display transmission input terminal, a positive display transmission output terminal, and the negative slope signal amplifier is configured with a negative slope amplification bias terminal, a negative slope amplification input terminal, and a negative slope amplification output terminal, and the negative slope signal transmission gate is configured with a negative slope transmission control terminal, a negative slope transmission Input terminal, negative slope transmission output terminal, and the pixel negative addressing storage circuit is configured with a pixel negative addressing control terminal, a pixel negative storage input terminal, and a pixel negative storage output terminal, and the negative analog display amplifier is configured with a negative display Amplifying bias terminal, negative display amplifying input terminal, negative display amplifying output terminal, and the negative analog display transmission gate is equipped with negative display transmission inverting control terminal, negative display transmission positive phase control terminal, negative display transmission input terminal, negative a display transmission output terminal, and the pixel output electrode circuit is configured with a pixel analog signal output electrode,

And the enable digital signal comparator has the function of outputting a high level to the first control line when receiving the rising edge trigger of the enable signal transmitted on the reset signal line of the comparator through the reset connection line, The digital signal received by the sixth connection line from the digital signal latch is compared with the digital signal received by the counter through the fifth connection line, and when the two digital signals are the same, the digital signal is sent to the first 1 control line output low level;

On the one hand, the positive slope signal amplifier adopts a P-type amplifier bias terminal as the positive slope amplification bias terminal, a P-type amplifier input terminal as the positive slope amplification input terminal, and a P-type amplifier output terminal as the positive slope. The PMOS type dual-tube common-drain amplifier at the slope amplification output end or the N-type amplifier bias end is used as the positive slope amplification bias end, the N-type amplifier input end is used as the positive slope amplification input end, and the N-type amplifier output end is used as the positive slope amplification input end. One of the NMOS type dual-transistor common-drain amplifiers at the positive ramp amplifying output end, and the positive ramp amplifying bias end is connected to the ramp bias voltage supply line, and the positive ramp amplifying input end is connected to the positive ramp signal line connected,

Wherein the PMOS-type dual-transistor common-drain amplifier consists of at least the first-PMOS transistor including the first-PMOS gate, the first-PMOS source, and the first-PMOS drain, and at least including the second-PMOS gate, the first-PMOS 2-PMOS source, the 2nd-PMOS drain of the 2nd-PMOS tube structure, and it is characterized in that the 1st-PMOS gate acts as the bias terminal of the P-type amplifier, and the 2nd-PMOS gate Acting as the input terminal of the P-type amplifier, the drain of the first-PMOS is connected to the source of the second-PMOS to form the output terminal of the P-type amplifier, and the source of the first-PMOS is connected to the power supply line, the drain of the 2-PMOS is connected to the ground line,

Wherein the NMOS-type dual-transistor common-drain amplifier consists of a first-NMOS transistor including at least a 1st-NMOS gate, a 1st-NMOS drain, and a 1st-NMOS source, and at least a 2nd-NMOS gate, a 1st-NMOS transistor 2-NMOS drain, the 2nd-NMOS source of the 2nd-NMOS tube, and it is characterized in that the 2nd-NMOS gate acts as the bias terminal of the N-type amplifier, and the 1st-NMOS gate Acting as the input terminal of the N-type amplifier, the drain of the second-NMOS is connected to the source of the first-NMOS to form the output terminal of the N-type amplifier, and the drain of the first-NMOS is connected to the power supply line, the 2nd-NMOS source is connected to the ground line,

And the positive slope signal transmission gate is used as the positive slope transmission control terminal by using the first analog transmission gate control terminal, the first analog transmission gate input terminal as the positive slope transmission input terminal, and the first analog transmission gate output terminal as the positive slope transmission gate. The first analog signal transmission gate of the positive slope transmission output terminal is formed, and the positive slope transmission input terminal is connected to the positive slope amplification output terminal, and the positive slope transmission output terminal is connected to the column display positive analog signal line ,

Wherein the first analog signal transmission gate consists of a 3rd-PMOS transistor including at least a 3rd-PMOS gate, a 3rd-PMOS drain, a 3rd-PMOS source, and at least a 3rd-NMOS gate, a 3rd -NMOS drain, the 3rd-NMOS transistor of the 3rd-NMOS source, and the 4th-PMOS transistor including at least the 4th-PMOS gate, the 4th-PMOS drain, the 4th-PMOS source and at least including the 4th-PMOS transistor 4-NMOS gate, 4th-NMOS drain, 4th-NMOS source 4th-NMOS tube is composed of, and is also equipped with: power supply line, grounding line, and is characterized in that the 4th-NMOS gate Pole, the 4th-PMOS gate, and the 3rd-NMOS gate are connected to form the first analog transmission gate control terminal, and the 4th-NMOS source, the 4th-PMOS drain, The 3rd-PMOS gates are connected to each other, the 4th-PMOS source is connected to the power supply line and the 4th-NMOS drain is connected to the ground line, the 3rd-PMOS drain The pole is connected to the source of the 3rd-NMOS to form the input terminal of the first analog transmission gate, and the source of the 3rd-PMOS is connected to the drain of the 3rd-NMOS to form the output terminal of the first analog transmission gate. ,

In addition, the pixel positive addressing storage circuit adopts a P-type switched capacitor control terminal as the pixel positive address control terminal, a P-type switched capacitor input terminal as the pixel positive storage input terminal, and a P-type switched capacitor output terminal as the pixel positive address storage circuit. The PMOS type switched capacitor at the positive storage output end of the pixel or the N-type switched capacitor control end is used as the positive addressing control end of the pixel, the N-type switched capacitor input end is used as the pixel positive storage input end, and the N-type switched capacitor output end is used as the pixel positive storage input end. The pixel is composed of one of the NMOS type switching capacitors at the storage output end, and the pixel positive addressing control terminal is connected to the row addressing signal line, and the pixel positive storage input terminal is connected to the column display positive analog signal line connected,

Wherein the PMOS type switched capacitor is composed of at least the 6th-PMOS transistor including the 6th-PMOS gate, the 6th-PMOS drain, the 6th-PMOS source and at least including the upper plate of the MIM capacitor and the lower plate of the MIM capacitor The MIM capacitor is formed, and it is characterized in that the 6th-PMOS gate serves as the P-type switched capacitor control terminal, the 6th-PMOS source serves as the P-type switched capacitor input terminal, and the 6- The PMOS drain is connected to the upper plate of the MIM capacitor to form the output end of the P-type switched capacitor, and the lower plate of the MIM capacitor is connected to the ground wire,

Wherein the NMOS type switched capacitor is composed of at least the 6th-NMOS transistor including the 6th-NMOS gate, the 6th-NMOS drain, the 6th-NMOS source and at least including the upper plate of the MIM capacitor and the lower plate of the MIM capacitor The MIM capacitor is formed, and it is characterized in that the 6th-NMOS gate serves as the N-type switched capacitor control terminal, the 6th-NMOS drain serves as the N-type switched capacitor input terminal, and the 6th-NMOS drain serves as the N-type switched capacitor input terminal, and the 6th- The NMOS source is connected to the upper plate of the MIM capacitor to form the output end of the N-type switched capacitor, and the lower plate of the MIM capacitor is connected to the ground wire,

And the positive analog display amplifier adopts the P-type amplifier bias terminal as the positive display amplification bias terminal, the P-type amplifier input terminal as the positive display amplification input terminal, and the P-type amplifier output terminal as the positive display amplification The PMOS type dual-tube common-drain amplifier at the output end or the bias end of the N-type amplifier is used as the positive display amplification bias end, the N-type amplifier input end is used as the positive display amplification input end, and the N-type amplifier output end is used as the positive display amplification input end. One of the NMOS type dual-transistor common-drain amplifiers that display the amplification output terminal is composed, and the positive display amplification input terminal is connected to the positive storage output terminal of the pixel, and the positive display amplification bias terminal is connected to the positive bias voltage supply line connected,

And the positive analog display transmission gate uses the second analog transmission gate positive phase control terminal as the positive display transmission positive phase control terminal, the second analog transmission gate inversion control terminal as the positive display transmission inversion control terminal, The input end of the second analog transmission gate acts as the input end of the positive display transmission, and the output end of the second analog transmission gate acts as the second analog signal transmission gate of the output end of the positive display transmission, and the input end of the positive display transmission is connected to the transmission input end of the positive display. The positive display amplification output terminal is connected, the positive display transmission positive phase control terminal is connected to the global positive display positive phase signal line, the positive display transmission negative phase control terminal is connected to the global positive display negative phase signal line,

Wherein the second analog signal transmission gate is composed of a 5th-PMOS transistor including at least the 5th-PMOS gate, the 5th-PMOS drain, and the 5th-PMOS source, and at least including the 5th-NMOS gate, the 5th -NMOS drain, the 5th-NMOS source of the 5th-NMOS transistor, characterized in that the 5th-PMOS drain and the 5th-NMOS source are connected to form the second analog transmission gate input terminal , the drain of the 5th-NMOS is connected to the source of the 5th-PMOS to form the output terminal of the second analog transmission gate, and the gate of the 5th-PMOS serves as the inverting control terminal of the second analog transmission gate , the gate of the 5th-NMOS serves as the positive-phase control terminal of the second analog transmission gate;

On the other hand, the negative slope signal amplifier is composed of a P-type amplifier bias terminal as the negative slope amplification bias terminal, a P-type amplifier input terminal as the negative slope amplification input terminal, and a P-type amplifier output terminal as the negative slope amplification input terminal. The PMOS type dual-tube common-drain amplifier at the negative slope amplification output terminal or the N-type amplifier bias terminal is used as the negative slope amplification bias terminal, the N-type amplifier input terminal is used as the negative slope amplification input terminal, and the N-type amplifier output terminal is used as the negative slope amplification input terminal. One of the NMOS-type dual-tube common-drain amplifiers at the negative slope amplification output terminal is composed, and the negative slope amplification bias terminal is connected to the slope bias voltage supply line, and the negative slope amplification output terminal is connected to the negative slope The signal line is connected,

And the negative slope signal transmission gate is used as the negative slope transmission control terminal by using the first analog transmission gate control terminal, the first analog transmission gate input terminal as the negative slope transmission input terminal, and the first analog transmission gate output terminal as the The first analog signal transmission gate of the negative slope transmission output terminal is formed, and the negative slope transmission input terminal is connected to the negative slope amplification output terminal, and the negative slope transmission output terminal is connected to the column display negative analog signal line ,

In addition, the pixel negative address storage circuit adopts a P-type switched capacitor control terminal as the pixel negative address control terminal, a P-type switched capacitor input terminal as the pixel negative storage input terminal, and a P-type switched capacitor output terminal as the pixel negative storage circuit. The PMOS type switched capacitor at the pixel negative storage output terminal or the N-type switched capacitor control terminal is used as the pixel negative addressing control terminal, the N-type switched capacitor input terminal is used as the pixel negative storage input terminal, and the N-type switched capacitor output terminal is used as the pixel negative storage input terminal. The pixel negative storage output terminal is composed of one of the NMOS switch capacitors, and the pixel negative address control terminal is connected to the row addressing signal line, and the pixel negative storage input terminal is connected to the column display negative analog signal line connected,

And the negative analog display amplifier adopts the P-type amplifier bias terminal as the negative display amplification bias terminal, the P-type amplifier input terminal as the negative display amplification input terminal, and the P-type amplifier output terminal as the negative display amplification The PMOS type dual-tube common-drain amplifier at the output end or the bias end of the N-type amplifier is used as the negative display amplification bias end, the N-type amplifier input end is used as the negative display amplification input end, and the N-type amplifier output end is used as the negative display amplification input end. One of the NMOS type dual-transistor common-drain amplifiers at the display amplification output terminal, and the negative display amplification input terminal is connected to the negative storage output terminal of the pixel, and the negative display amplification bias terminal is connected to the negative bias voltage supply line connected,

And the negative analog display transmission gate uses the second analog transmission gate positive phase control terminal as the negative display transmission positive phase control terminal, the second analog transmission gate inversion control terminal as the negative display transmission inversion control terminal, The input terminal of the second analog transmission gate serves as the input terminal of the negative display transmission, and the output terminal of the second analog transmission gate serves as the second analog signal transmission gate of the output terminal of the negative display transmission, and the input terminal of the negative display transmission is connected to the input terminal of the negative display transmission. The negative display amplification output terminal is connected, the negative display transmission positive phase control terminal is connected to the global negative display positive phase signal line, the negative display transmission negative phase control terminal is connected to the global negative display negative phase signal line,

And the pixel output electrode circuit is constructed by an output electrode parasitic capacitor formed between the pixel analog signal output electrode and a conductor close to the periphery but not in contact and connected to the ground line, and is characterized in that the pixel analog signal the output electrode serves as one electrode plate of the output electrode parasitic capacitor, the ground line serves as the other electrode plate of the output electrode parasitic capacitor,

And the pixel analog signal output electrodes are respectively connected to the negative display transmission output terminal and the positive display transmission output terminal;

The driving method of the double-way symmetrical slope type analog pixel driving circuit is that any display period is composed of a positive field display period and a negative field display period adjacent to each other, and each of the positive field display period and the negative field display period is composed of one that can make the described Both the pixel positive addressing storage circuit and the pixel negative addressing storage circuit have an addressing row period in which the input access state occurs, and at least one display row period that always makes the pixel positive addressing storage circuit and the pixel negative addressing storage circuit both maintain the input disconnection state constitute, and the addressing row period and the display row period have the same duration, are connected in time and are collectively referred to as a row period, and in each row period, the positive ramp signal amplifier and the negative ramp signal amplifier are all controlled by the ramp The bias level transmitted on the bias voltage supply line is configured as a valid working state,

And in all the display row periods of the positive field display period and the addressing row periods of its adjacent negative field display period, the negative analog display transmission gate is in an off state and the negative analog display amplifier is in an invalid working state, and in the negative field display period The positive analog display transmission gate is in an open circuit state and the positive analog display amplifier is in an invalid working state in all display row periods of the field display period and its adjacent addressing row periods of the positive field display period,

And each line period is divided into four time periods T1, T2, T3, T4 and two types of positive ramp signals and negative ramp signals are respectively constructed by connecting four waveforms, and the waveform features are positive ramp signals and negative ramp signals The same highest level is the highest level of the slope, the same center level is the center level of the slope, and the same lowest level is the lowest level of the slope, and the positive slope signal jumps from the highest level of the slope in the T1 time period of each row cycle At the same time, the negative ramp signal jumps from the lowest level of the ramp to the central level of the ramp. In the T2 time period, both the positive ramp signal and the negative ramp signal are fixed at the ramp center level. In the T3 time period, the positive ramp signal changes from the ramp The center level jumps to the lowest level of the slope while the negative ramp signal jumps from the center level of the slope to the highest level of the slope, and the positive ramp signal changes incrementally from the lowest level of the slope to the highest level of the slope in the T4 time period The ramp signal changes gradually from the highest level of the ramp to the lowest level of the ramp;

First, in the addressing row period of the positive field display period,

In the T1 time period: the positive ramp signal transmitted on the positive ramp signal line jumps from the highest ramp level to the ramp center level, and at the same time the negative ramp signal transmitted on the negative ramp signal line transitions from the lowest ramp level to ramp center level,

And the rising edge signal of the pulse wave signal transmitted on the reset signal line of the comparator triggers the enable digital signal comparator to output a high level, and the positive slope transmission control terminal and the negative slope transmission control terminal respectively make the Both the positive slope signal transmission gate and the negative slope signal transmission gate are in the pass state, so that the columns display the analog signal transmitted on the positive analog signal line to follow the positive slope signal transmitted on the positive slope signal line, the The above column shows that the analog signal transmitted on the negative analog signal line follows the negative ramp signal transmitted on the negative ramp signal line, and the inactive level is transmitted on the row addressing signal line so that the pixel is addressing the storage circuit and all The pixel negative addressing storage circuit and the column display positive analog signal line and the column display negative analog signal line are both in an input disconnection state and continue to store the level stored at the end of the last display cycle, and the negative bias The analog signal transmitted on the voltage supply line configures the negative analog display amplifier to an effective working state, and the negative analog display transmission gate is controlled by the pulse wave signal transmitted on the global negative display inversion signal line and the global negative analog display amplifier. It shows that the pulse wave signal transmitted on the positive phase signal line is configured to be in the off state, and also causes the analog signal output on the analog signal output electrode of the pixel to continue to maintain the level state of the parasitic capacitor of the output electrode at the end of the last line period,

And in the T2 time period: the level of the positive ramp signal transmitted on the positive ramp signal line and the level of the negative ramp signal transmitted on the negative ramp signal line continue to be fixed at the central level of the ramp signal,

And the pulse wave signals received by the positive slope transmission control terminal and the negative slope transmission control terminal both continue to maintain the level state of the previous time period, so that the column shows that the analog signal transmitted on the positive analog signal line continues to follow the The positive slope signal transmitted on the positive slope signal line, the column shows that the analog signal transmitted on the negative analog signal line continues to follow the negative slope signal transmitted on the negative slope signal line, and the pixel is addressing the storage circuit and the The pixel negative addressing storage circuit continues to maintain the input off state and makes the respective level states continue to be stored and output, and the negative analog display amplifier continues to maintain an effective working state, and the global negative display inversion signal line The transmitted pulse wave signal and the pulse wave signal transmitted on the global negative display positive phase signal line change to put the negative analog display transmission gate in the open state, and also cause the pixel negative addressing storage circuit to save the level driving and enhancing the pixel analog signal output electrode in real time through the negative analog display amplifier and maintaining a parasitic capacitor on the output electrode,

And in the T3 time period: the positive slope signal transmitted on the positive slope signal line jumps from the slope center level to the lowest slope level, and at the same time the negative slope signal transmitted on the negative slope signal line jumps from the slope center level to ramp to the highest level,

And the pulse wave signals received by the positive slope transmission control terminal and the negative slope transmission control terminal continue to maintain the level state of the previous period, and then respectively make the analog signals transmitted on the positive analog signal line shown in the columns continue to follow the The positive ramp signal transmitted on the positive ramp signal line, the column shows that the analog signal transmitted on the negative analog signal line continues to follow the negative ramp signal transmitted on the negative ramp signal line, and the row addressing signal line changes In order to transmit the effective level, the positive addressing storage circuit of the pixel and the negative addressing storage circuit of the pixel are respectively in the communication state with the positive analog signal line of the column display and the negative analog signal line of the column display, and respectively make The column shows that the analog signal transmitted on the positive analog signal line is stored in the positive addressing storage circuit of the pixel in real time, and the column shows that the analog signal transmitted on the negative analog signal line is stored in the negative addressing storage circuit of the pixel in real time, And the pulse wave signal transmitted on the negative phase signal line of the global negative display and the pulse wave signal transmitted on the positive phase signal line of the global negative display change again so that the negative analog display transmission gate is in an open circuit state, and also Cause the pixel analog signal output electrode to continue the level state of the previous period, and the analog signal transmitted on the negative bias voltage supply line changes to reconfigure the negative analog display amplifier to an invalid working state,

And in the T4 time period: at the beginning, the counter resets to zero and starts counting, and the positive ramp signal transmitted on the positive ramp signal line starts from the lowest level of the ramp and changes synchronously with the counting speed of the counter to the highest level of the ramp. Level, the negative ramp signal transmitted on the negative ramp signal line starts from the highest level of the ramp and changes synchronously with the counting speed of the counter to the lowest level of the ramp, and the positive ramp transmission control terminal and the negative ramp transmission control The pulse wave signals received by the terminal continue to maintain the level state of the previous time period, so that the columns show that the analog signal transmitted on the positive analog signal line continues to follow the positive slope signal transmitted on the positive slope signal line, so The above column shows that the analog signal transmitted on the negative analog signal line continues to follow the negative slope signal transmitted on the negative slope signal line,

And when the number generated by the counter is equal to the number stored in the digital signal latch, it will trigger the enable digital signal comparator to output a low level, and cause the positive ramp signal transmission gate and the negative ramp signal transmission The gates are all in the open circuit state, and the analog signals transmitted on the positive analog signal line shown in the columns are no longer following the level change of the positive slope signal transmitted on the positive slope signal line in real time, and remain at a fixed level until the The positive slope signal transmission gate is in the pass state again, and the column shows that the analog signal transmitted on the negative analog signal line no longer follows the level change of the negative slope signal transmitted on the negative slope signal line in real time and remains at a fixed level until the The above-mentioned negative ramp signal transmission gate is in the pass state again,

And the positive addressing storage circuit of the pixel and the negative addressing storage circuit of the pixel continue to maintain the state of the input path, and respectively make the analog signal transmitted on the analog signal line of the column display drive the analog signal of the positive storage output end of the pixel update, the column shows that the analog signal transmitted on the negative analog signal line drives the update of the analog signal at the negative storage output of the pixel,

And the level of the positive ramp signal transmitted on the positive ramp signal line increases to the highest level of the ramp signal at the time of termination, while the level of the negative ramp signal transmitted on the negative ramp signal line decreases to the low level of the ramp signal , the counter also counts to a full value, the negative analog display amplifier continues to maintain an invalid working state, and the negative analog display transmission gate continues to maintain an off state, which also causes the analog signal output on the pixel analog signal output electrode to continue to go up The level status of a period of time;

Next, in the display line period of the positive field display period,

In the four time periods of T1, T2, T3, and T4: the positive ramp signal transmitted on the positive ramp signal line, the negative ramp signal transmitted on the negative ramp signal line, the pulse transmitted on the comparator reset signal line The wave signal and the pulse wave signal received by the positive ramp transmission control terminal and the negative ramp transmission control terminal in the first three time periods all repeat the waveform state in the previous line period, and respectively make the columns display positive analog signals The analog signal transmitted on the line continues to follow the positive ramp signal transmitted on the positive ramp signal line, and the column shows that the analog signal transmitted on the negative analog signal line continues to follow the negative ramp signal transmitted on the negative ramp signal line,

And the inactive level is transmitted on the row addressing signal line so that the positive addressing storage circuit of the pixel and the negative addressing storage circuit of the pixel are always kept in the input off state, so that the respective level states at the end of the last row cycle continue respectively. are stored and output, and the pulse wave signal transmitted on the global positive display anti-phase signal line and the pulse wave signal transmitted on the global positive display positive phase signal line first pass the positive analog display transmission gate in the T1 time period Being configured as an off state causes the analog signal output on the pixel analog signal output electrode to continue the level state of the previous period, and then in the T2 period, the positive analog display transmission gate is configured to enter the pass state and the positive analog The display amplifier is configured to be in an effective working state, which will cause the level of the output of the addressing storage circuit of the pixel to be driven in real time to update the analog signal output electrode of the pixel and maintain a parasitic capacitor on the output electrode,

And in the T4 time period, when the number generated by the counter is equal to the number stored in the digital signal latch, it will trigger the enable digital signal comparator to output a low level, causing the positive ramp signal transmission gate and the negative ramp The signal transmission gates are all in an open circuit state, and the respective analog signals transmitted on the column display positive analog signal line and the column display negative analog signal line are kept at a fixed level until the positive slope signal transmission gate and the column display negative analog signal line The above-mentioned negative ramp signal transmission gate is in the pass state again,

And the level of the positive ramp signal transmitted on the positive ramp signal line increases to the highest level of the ramp signal at the time of termination, while the level of the negative ramp signal transmitted on the negative ramp signal line decreases to the low level of the ramp signal , the counter also counts up to a full value;

Then, in the addressing row period of the negative field display period,

In the four time periods of T1, T2, T3, and T4: the positive ramp signal transmitted on the positive ramp signal line, the negative ramp signal transmitted on the negative ramp signal line, the pulse transmitted on the comparator reset signal line wave signal, the pulse wave signal transmitted on the positive bias voltage supply line, the pulse wave signal transmitted on the negative bias voltage supply line, the pulse wave signal transmitted on the global positive display positive phase signal line, the The pulse wave signal transmitted on the global positive display anti-phase signal line, the pulse wave signal transmitted on the global negative display positive phase signal line, and the pulse wave signal transmitted on the global negative display anti-phase signal line are all repeatedly transmitted in phase The waveform state transmitted in the display line period adjacent to the positive field display period, and the pulse wave signals received by the positive slope transmission control terminal and the negative slope transmission control terminal in the first three time periods are repeatedly transmitted in the previous line period and make the column display that the analog signal transmitted on the positive analog signal line continues to follow the positive ramp signal transmitted on the positive ramp signal line, and the column display that the analog signal transmitted on the negative analog signal line continues to follow a negative ramp signal transmitted on the negative ramp signal line,

And in the T1 and T2 time periods: the pixel positive addressing storage circuit and the pixel negative addressing storage circuit are both configured to maintain the input off state so that their respective level states in the previous time period respectively continue to be stored And output, and the pulse wave signal transmitted on the global positive display anti-phase signal line and the pulse wave signal transmitted on the positive phase signal line of the global positive display configure the positive analog display transmission gate to be closed in the T1 time period The off state causes the analog signal output on the pixel analog signal output electrode to continue the level state of the previous period, and in the T2 period, the positive analog display transmission gate is configured to enter the pass state and the positive analog display amplifier is activated. It is configured to be in an effective working state so as to cause the level of the output of the pixel positive addressing storage circuit to be driven in real time to enhance the analog signal output electrode of the pixel and maintain a parasitic capacitor on the output electrode,

And in the T3, T4 period, the active level is transmitted on the row addressing signal line, so that the pixel positive addressing storage circuit and the pixel negative addressing storage circuit re-enter and maintain the pass state, which will cause the pixel The analog signals at the positive storage output and the negative storage output of the pixel are updated,

And in the T4 time period, when the number generated by the counter is equal to the number stored in the digital signal latch, it will trigger the enable digital signal comparator to output a low level, causing the positive ramp signal transmission gate and the negative ramp The signal transmission gates are all in an open circuit state, and then respectively make the analog signals transmitted on the column display positive analog signal line and the column display negative analog signal line remain at a fixed level until the positive slope signal transmission gate and the The negative ramp signal transfer gate is re-enabled,

And the level of the positive ramp signal transmitted on the positive ramp signal line increases to the highest level of the ramp signal at the time of termination, while the level of the negative ramp signal transmitted on the negative ramp signal line decreases to the low level of the ramp signal , the counter also counts up to the full value,

Next, in the display line period of the negative field display period,

During T1, T2, T3, T4 time periods: the positive ramp signal transmitted on the positive ramp signal line, the negative ramp signal transmitted on the negative ramp signal line, the pulse wave signal transmitted on the comparator reset signal line , the pulse wave signal transmitted on the positive bias voltage supply line, the pulse wave signal transmitted on the negative bias voltage supply line, the pulse wave signal transmitted on the positive phase signal line of the global positive display, the global The positive display pulse wave signal transmitted on the anti-phase signal line, the global negative display pulse wave signal transmitted on the positive phase signal line, and the global negative display pulse wave signal transmitted on the anti-phase signal line are all repeatedly transmitted to the adjacent positive The waveform state transmitted in the addressing line period of the field display period, and the pulse wave signals received by the positive ramp transmission control terminal and the negative ramp transmission control terminal in the first three time periods are repeatedly transmitted in the previous line period Waveform state, and respectively make the analog signal transmitted on the positive analog signal line continue to follow the positive slope signal transmitted on the positive slope signal line in the column, and the analog signal transmitted on the negative analog signal line continue to follow the analog signal transmitted on the negative analog signal line in the column The negative ramp signal transmitted on the negative ramp signal line,

And the inactive level is transmitted on the row addressing signal line so that the positive addressing storage circuit of the pixel and the negative addressing storage circuit of the pixel are always kept in the input off state, so that the respective level states at the end of the last row cycle continue respectively. stored and output, and the pulse wave signal transmitted on the global negative display anti-phase signal line and the pulse wave signal transmitted on the global negative display positive phase signal line configure the negative analog display transmission gate in the T1 time period In the off state, the analog signal output on the analog signal output electrode of the pixel continues the level state of the previous time period, and the negative analog display transmission gate is configured to enter the pass state and the negative analog display is in the T2 time period The amplifier is configured to be in an effective working state, which will cause the output level of the pixel negative addressing storage circuit to drive and update the pixel analog signal output electrode in real time and maintain a parasitic capacitor on the output electrode,

And in the T4 time period, when the number generated by the counter is equal to the number stored in the digital signal latch, it will trigger the enable digital signal comparator to output a low level, causing the positive ramp signal transmission gate and the negative ramp The signal transmission gates are all in an open circuit state, and then respectively make the analog signals transmitted on the column display positive analog signal line and the column display negative analog signal line remain at a fixed level until the positive slope signal transmission gate and the The negative ramp signal transfer gate is re-enabled,

And the level of the positive ramp signal transmitted on the positive ramp signal line increases to the highest level of the ramp signal at the time of termination, while the level of the negative ramp signal transmitted on the negative ramp signal line decreases to the low level of the ramp signal , the counter also counts up to a full value;

As a result, the analog signal waveform output on the pixel analog signal output electrode is characterized by being divided into a positive field display part and a negative field display part, wherein the positive field display part is composed of the part generated in the row display period of the positive field display period and the The part generated in the row addressing period of the adjacent negative field display period and the part in the row display period T1 period of the negative field display period are composed, wherein the negative field display part is composed of the row display period generated in the negative field display period The part in and the part generated in the row addressing period of the adjacent positive field display period and the part in the row display period T1 period of the positive field display period are formed,

The driving method also includes: in each row cycle, T1, T2, T3, T4 four time periods are performed sequentially, and then go round and round, then each display cycle can be at the same time between the output of the pixel analog signal output electrode and the current display cycle. A pair of analog levels corresponding to the numbers stored in the digital signal latch in the row addressing period.

Beneficial effects of the present invention: Compared with the prior art, the present invention has three advantages: one is that a double-tube common-drain amplifier is arranged on the column display positive analog signal line and the column display negative analog signal line, which can objectively isolate each The columns show the electrical signal crosstalk between the positive analog signal lines, and each column shows the electrical signal crosstalk between the negative analog signal lines; the second is the two-way symmetrical four-segment waveform ramp signal and its T1, T2, T3, T4 sub-time segments included in the driving method The sequential cycle method avoids signal crosstalk between the addressing sampling behavior and the display behavior in the same pixel circuit; the third is the two-way symmetrical four-segment waveform ramp signal and its positive field display period and negative field display period included in the driving method Combining into one display cycle method can alternately output a pair of analog levels.

Description of drawings

Figure 1 is a schematic diagram of a dual-channel symmetrical slope analog pixel drive circuit, in which, 1: the first control line, 2: the second connection line, 3: positive slope signal amplifier, 4: positive slope amplification bias terminal, 5: the first 5 connection line, 6: 6th connection line, 7: positive slope amplification output terminal, 8: counter, 9: reset connection line, 10: negative slope amplification input terminal, 11: digital signal latch, 12: enable digital Signal comparator, 13: positive slope amplification input terminal, 14: negative slope signal amplifier, 15: positive slope transmission control terminal, 16: display digital signal input bus, 17: positive slope signal line, 18: slope bias voltage supply line , 19: Comparator reset signal line, 21: Positive display amplification output terminal, 22: Positive display transmission input terminal, 23: Positive analog display transmission gate, 24: Row addressing signal line, 25: Positive display transmission output terminal, 26 : pixel analog signal output electrode, 27: negative slope amplification output terminal, 28: positive bias voltage supply line, 29: global positive display positive phase signal line, 30: pixel output electrode circuit, 31: global negative display negative phase signal line , 32: positive display transmission inversion control terminal, 33: global negative display positive phase signal line, 34: positive display transmission positive phase control terminal, 35: negative slope amplification bias terminal, 36: negative slope transmission control terminal, 37: Positive display amplification bias terminal, 38: negative slope transmission input terminal, 39: positive display amplification input terminal, 40: negative slope signal transmission gate, 41: negative slope transmission output terminal, 42: pixel positive storage output terminal, 43: pixel Positive storage input terminal, 44: column display positive analog signal line, 45: column display negative analog signal line, 46: pixel positive addressing storage circuit, 47: pixel positive addressing control terminal, 48: pixel negative addressing control terminal, 49: Positive analog display amplifier, 51: Positive slope transmission output terminal, 52: Positive slope signal transmission gate, 53: Positive slope transmission input terminal, 57: Negative bias voltage supply line, 58: Global positive display inversion signal line, 59: Pixel negative storage input terminal, 60: Pixel negative addressing storage circuit, 69: Negative analog display transmission gate, 70: Negative analog display amplifier, 71: Negative display transmission output terminal, 72: Negative display transmission positive phase control terminal, 78: Negative display transmission inversion control terminal, 79: Negative slope signal line, 80: Negative display transmission input terminal, 89: Negative display amplification output terminal, 90: Negative display amplification bias terminal, 91: Negative display amplification input terminal, 92: pixel negative storage output terminal;

Fig. 2 is a schematic diagram of a PMOS dual-transistor common-drain amplifier circuit, wherein, 77: power supply line, 85: the first-PMOS gate, 86: the first-PMOS source, 87: the first-PMOS drain, 88 : 1st-PMOS transistor, 93: 2nd-PMOS transistor, 94: 2nd-PMOS gate, 95: 2nd-PMOS source, 96: 2nd-PMOS drain, 97: P-type amplifier input terminal, 98: P-type amplifier output terminal, 99: P-type amplifier bias terminal, 135: ground wire;

Fig. 3 is a circuit schematic diagram of an NMOS dual-transistor common-drain amplifier, wherein, 77: power supply line, 101: the 1st-NMOS transistor, 102: the 1st-NMOS gate, 103: the 1st-NMOS drain, 104: 1st-NMOS source, 105: 2nd-NMOS transistor, 106: 2nd-NMOS gate, 107: 2nd-NMOS drain, 108: 2nd-NMOS source, 109: N-type amplifier bias terminal , 110: N-type amplifier input terminal, 111: N-type amplifier output terminal, 135: ground wire;

Fig. 4 is a schematic diagram of the first analog signal transmission gate circuit, wherein, 54: the control terminal of the first analog transmission gate, 55: the output terminal of the first analog transmission gate, 56: the input terminal of the first analog transmission gate, 61: the third- PMOS gate, 62: 3rd-PMOS drain, 63: 3rd-PMOS source, 64: 3rd-PMOS transistor, 65: 3rd-NMOS source, 66: 3rd-NMOS gate, 67: 3rd-NMOS drain, 68: 3rd-NMOS transistor, 73: 4th-PMOS transistor, 74: 4th-PMOS gate, 75: 4th-PMOS source, 76: 4th-PMOS drain, 77: power supply line, 81: 4th-NMOS gate, 82: 4th-NMOS source, 83: 4th-NMOS tube, 84: 4th-NMOS drain, 135: ground wire;

Figure 5 is a schematic diagram of a PMOS switched capacitor circuit, wherein, 112: P-type switched capacitor control terminal, 113: MIM capacitor lower plate, 115: MIM capacitor, 116: MIM capacitor upper plate, 117: P-type switched capacitor input Terminal, 118: P-type switched capacitor output terminal, 121: 6th-PMOS source, 123: 6th-PMOS gate, 124: 6th-PMOS drain, 125: 6th-PMOS transistor, 135: ground wire ;

Figure 6 is a schematic diagram of the NMOS switched capacitor circuit, where 113: MIM capacitor lower plate, 114: N-type switched capacitor control terminal, 115: MIM capacitor, 116: MIM capacitor upper plate, 119: N-type switched capacitor input Terminal, 120: N-type switched capacitor output terminal, 126: 6th-NMOS drain, 127: 6th-NMOS gate, 128: 6th-NMOS source, 129: 6th-NMOS tube, 135: ground wire ;

7 is a schematic diagram of the second analog signal transmission gate circuit, wherein, 130: the input terminal of the second analog transmission gate, 131: the output terminal of the second analog transmission gate, 132: the positive phase control terminal of the second analog transmission gate, 133: the second analog transmission gate 2 analog transmission gate inverting control terminal, 141: 5th-PMOS gate, 142: 5th-PMOS drain, 143: 5th-PMOS source, 145: 5th-PMOS transistor, 146: 5th-NMOS Source, 147: 5th-NMOS gate, 148: 5th-NMOS drain, 149: 5th-NMOS transistor;

Fig. 8 is a schematic diagram of the pixel output electrode circuit, wherein, 20: output electrode parasitic capacitor, 26: pixel analog signal output electrode, 135: ground wire;

Fig. 9 is a waveform diagram of a dual-channel symmetrical four-segment waveform ramp signal in one of the application scenarios of the dual-channel symmetrical ramp-type analog pixel drive circuit, wherein:

Srp_p: the positive ramp signal transmitted on the positive ramp signal line 17,

Srp_n: the negative ramp signal transmitted on the negative ramp signal line 79,

V1: the lowest level of the slope,

V2: ramp center level,

V3: the highest level of the slope,

VD: The power supply line 77 level,

VG: the level of the ground line 135;

Figure 10 is a summary of signal waveforms driven by one of the application scenarios of the dual-channel symmetrical slope analog pixel drive circuit, wherein:

Srp_p: the positive ramp signal transmitted on the positive ramp signal line 17,

Srp_n: the negative ramp signal transmitted on the negative ramp signal line 79,

V1: the lowest level of the ramp signal,

V2: ramp signal center level,

V3: the highest level of the ramp signal,

Vbp: the slope positive bias level transmitted on the slope bias voltage supply line 18,

Vbn: the slope negative bias level transmitted on the slope bias voltage supply line 18,

RST: the pulse wave signal transmitted on the comparator reset signal line 19,

ENC: the positive ramp signal transmission gate 52 enables the pulse wave signal received by the control terminal,

SDi_p: the column shows the analog signal being transmitted on the analog signal line 44,

SDi_n: the column shows the analog signal transmitted on the negative analog signal line 45,

Sgp: the addressing positive pulse wave signal transmitted on the row addressing signal line 24,

Sgn: the addressing negative pulse wave signal transmitted on the row addressing signal line 24,

Vsc_p: the pixel is storing the analog signal output from the output terminal 42,

Vsc_n: the analog signal output by the negative storage output terminal 92 of the pixel,

Vbp2p: the P pulse wave signal transmitted on the positive bias voltage supply line 28,

Vbn2p: the N pulse wave signal transmitted on the positive bias voltage supply line 28,

Vbp2n: the P pulse wave signal transmitted on the negative bias voltage supply line 57,

Vbn2n: the N pulse wave signal transmitted on the negative bias voltage supply line 57,

SNp: the global positive display N pulse wave signal transmitted on the positive phase signal line 29,

SPp: the global is positively displaying the P pulse wave signal transmitted on the anti-phase signal line 58,

SNn: the global negative display N pulse wave signal transmitted on the positive phase signal line 33,

SPn: the global negative display P pulse wave signal transmitted on the inversion signal line 31,

Vout: the analog signal output on the pixel analog signal output electrode 26;

Detailed ways

Firstly, in conjunction with accompanying drawings 1, 2, 3, 4, 5, 6, 7, and 8, the structure of the dual-path symmetrical slope analog pixel circuit of the technology of the present invention is further specifically described:

The dual-way symmetrical slope type analog pixel drive circuit consists of a digital signal latch 11, a counter 8, an enable digital signal comparator 12, a positive slope signal amplifier 3, a positive slope signal transmission gate 52, a pixel positive addressing storage circuit 46, a positive Analog display amplifier 49, positive analog display transmission gate 23, negative slope signal amplifier 14, negative slope signal transmission gate 40, pixel negative addressing storage circuit 60, negative analog display amplifier 70, negative analog display transmission gate 69, pixel output electrode circuit 30 and display digital signal input bus 16, comparator reset signal line 19, positive slope signal line 17, negative slope signal line 79, slope bias voltage supply line 18, row addressing signal line 24, positive bias voltage supply line 28 , negative bias voltage supply line 28, global positive display positive phase signal line 29, global positive display reverse signal line 58, global negative display positive phase signal line 33, global negative display negative phase signal line 31, column display positive analog signal The line 44 and the column display negative analog signal line 45 are jointly formed, and there are the positive slope signal line 17, the positive slope signal amplifier 3, the positive slope signal transmission gate 52, the column display positive analog signal line 44, The pixel positive addressing storage circuit 46, the positive analog display amplifier 49, and the positive analog display transmission gate 23 are electrically connected in series to form a functional circuit to process a positive ramp signal constructed by connecting four waveforms, and the Negative ramp signal line 79, the negative ramp signal amplifier 14, the negative ramp signal transmission gate 40, the column display negative analog signal line 45, the pixel negative addressing storage circuit 60, the negative analog display amplifier 70 1. The negative analog display transmission gate 69 is electrically connected in series to form another functional circuit to process the negative ramp signal constructed by connecting four waveforms, and the positive analog display transmission gate 23 and the negative analog display transmission gate 69 both output The level signal is sent to the pixel output electrode circuit 30, and the number of digits of the digital signal latch 11 is the same as that of the counter 8, and is also configured with: a second connection line 2, a fifth connection line 5 , the sixth connection line 6, the reset connection line 9, the first control line 1, the power supply line 77, the ground line 135, the digital signal latch 11 is connected to the display digital signal input through the second connection line 2 The bus 16 receives and stores the multi-digit digital signal transmitted by the display digital signal input bus 16, and the enabling digital signal comparator 12 is connected to the counter 8 through the fifth connection line 5 and receives the digital signal transmitted by the display digital signal input bus 16. The multi-bit counting digital signal sent by the counter 8 is connected to the digital signal latch 11 through the sixth connection line 6 and receives the multi-bit storage digital signal sent by the digital signal latch 11, and the The reset connection line 9 is connected to the comparator reset signal line 19 and receives the reset level signal sent by the comparator reset signal line 19, and connects the positive slope transmission control terminal 15 and the The negative slope transmission control terminal 36 and send control level signals to the positive slope transmission control terminal 15 and the negative slope transmission control terminal 36 respectively;

Wherein as shown in the schematic diagram of the dual-way symmetrical slope type analog pixel drive circuit shown in Figure 1, the positive slope signal amplifier 3 is configured with a positive slope amplification bias terminal 4, a positive slope amplification input terminal 13, and a positive slope amplification output terminal 7, and The positive ramp signal transmission gate 52 is configured with a positive ramp transmission control terminal 15, a positive ramp transmission input terminal 53, and a positive ramp transmission output terminal 51, and the pixel positive addressing storage circuit 46 is configured with a pixel positive addressing control terminal 47 , the positive storage input terminal 43 of the pixel, the positive storage output terminal 42 of the pixel, and the positive analog display amplifier 49 is configured with a positive display amplification bias terminal 37, a positive display amplification input terminal 39, and a positive display amplification output terminal 21, and the The positive analog display transmission gate 23 is configured with a positive display transmission inversion control terminal 32, a positive display transmission positive phase control terminal 34, a positive display transmission input terminal 22, and a positive display transmission output terminal 25. The negative slope signal amplifier 14 is configured with a negative Slope amplification bias terminal 35, negative slope amplification input terminal 10, negative slope amplification output terminal 27, and the negative slope signal transmission gate 40 is equipped with negative slope transmission control terminal 36, negative slope transmission input terminal 38, negative slope transmission output terminal 41, and the pixel negative addressing storage circuit 60 is configured with a pixel negative addressing control terminal 48, a pixel negative storage input terminal 59, and a pixel negative storage output terminal 92, and the negative analog display amplifier 70 is configured with a negative display amplification Bias terminal 90, negative display amplification input terminal 91, negative display amplification output terminal 89, and the negative analog display transmission gate 69 is equipped with negative display transmission inverting control terminal 78, negative display transmission positive phase control terminal 72, negative display The transmission input terminal 80, the negative display transmission output terminal 71, and the pixel output electrode circuit 30 is configured with a pixel analog signal output electrode 26 and a conductor that is close to the periphery but does not contact and is connected to the ground line 135 to form a The output electrode parasitic capacitor 20,

And the enable digital signal comparator 12 has the function of outputting high power to the first control line 1 when receiving the rising edge trigger of the enable signal transmitted on the comparator reset signal line 19 through the reset connection line 9. flat, when the digital signal received from the digital signal latch 11 through the sixth connection line 6 is compared with the digital signal received from the counter 8 through the fifth connection line 5 and when the two Outputting a low level to the first control line 1 when the digital signals are the same;

Referring to accompanying drawing 2 and accompanying drawing 3 simultaneously, be on the one hand positive slope signal amplifier 3 as described positive slope amplification bias end 4, P type amplifier input end 97 by adopting P-type amplifier bias end 99 as described in Fig. 1 Serve as described positive slope amplifying input end 13, P-type amplifier output end 98 as described positive slope amplifying output end 7 PMOS type dual-tube common-drain amplifier or adopt N-type amplifier bias end 109 to serve as described positive slope amplifying bias Terminal 4, N-type amplifier input end 110 serve as described positive slope amplifying input end 13, N-type amplifier output end 111 serve as one of the NMOS type dual-tube common-drain amplifier of described positive slope amplifying output end 7, and described positive slope The slope amplification bias terminal 4 is connected to the slope bias voltage supply line 18, and the positive slope amplification input terminal 13 is connected to the positive slope signal line 17,

Wherein as shown in the schematic diagram of the PMOS type double-tube common-drain amplifier circuit schematic diagram of Fig. 2, described PMOS type double-tube common-drain amplifier comprises at least the 1st-PMOS grid 85, the 1st-PMOS source 86, the 1st-PMOS drain The first-PMOS transistor 88 of the electrode 87 and the second-PMOS transistor 93 including at least the second-PMOS gate 94, the second-PMOS source 95, and the second-PMOS drain 96 are composed, and are characterized in that The first-PMOS gate 85 serves as the P-type amplifier bias terminal 99, the second-PMOS gate 94 serves as the P-type amplifier input terminal 97, the first-PMOS drain 87 is connected to the first The 2-PMOS source 95 is connected to form the P-type amplifier output terminal 98, the first-PMOS source 86 is connected to the power supply line 77, and the second-PMOS drain 96 is connected to the ground line 135,

Wherein as shown in the schematic diagram of the NMOS type double-transistor common-drain amplifier circuit shown in Figure 3, the NMOS-type dual-transistor common-drain amplifier consists of at least the first-NMOS gate 102, the first-NMOS drain 103, and the first-NMOS source The 1st-NMOS transistor 101 of the electrode 104 and the 2nd-NMOS transistor 105 including at least the 2nd-NMOS gate 106, the 2nd-NMOS drain 107, and the 2nd-NMOS source 108 constitute, and are characterized in that The 2nd-NMOS gate 106 serves as the N-type amplifier bias terminal 109, the 1st-NMOS gate 102 serves as the N-type amplifier input 110, the 2nd-NMOS drain 107 and the 1st-NMOS The 1-NMOS source 104 is connected to form the N-type amplifier output terminal 111, the 1st-NMOS drain 103 is connected to the power supply line 77, and the 2nd-NMOS source 108 is connected to the grounding line 135,

Referring to accompanying drawing 4 simultaneously, and as described in Fig. 1 positive slope signal transmission gate 52 is by adopting the 1st analog transmission gate control terminal 54 to serve as described positive slope transmission control terminal 15, the 1st analog transmission gate input terminal 56 as described The positive slope transmission input 53 and the first analog transmission gate output 55 serve as the first analog signal transmission gate of the positive slope transmission output 51, and the positive slope transmission input 53 and the positive slope amplification output 7, the positive slope transmission output terminal 51 is connected to the column display positive analog signal line 44,

Wherein as shown in the schematic diagram of the first analog signal transmission gate circuit shown in FIG. The 3rd-PMOS transistor 64 and the 3rd-NMOS transistor 68 including at least the 3rd-NMOS gate 66, the 3rd-NMOS drain 67, the 3rd-NMOS source 65 and the 4th-PMOS gate 74 at least , the 4th-PMOS drain 76, the 4th-PMOS transistor 73 of the 4th-PMOS source 75, and at least the 4th-NMOS gate 81, the 4th-NMOS drain 84, the 4th-NMOS source 82 The 4th-NMOS transistor 83 is composed of, and is also configured with: a power supply line 77, a grounding line 135, and is characterized in that the 4th-NMOS gate 81, the 4th-PMOS gate 74, the 3rd - The NMOS gate 66 is connected to form the first analog transmission gate control terminal 54, and the 4th-NMOS source 82, the 4th-PMOS drain 76, and the 3rd-PMOS gate 61 are connected to each other , and the 4th-PMOS source 75 is connected to the power supply line 77 and the 4th-NMOS drain 84 is connected to the ground line 135, the 3rd-PMOS drain 62 and the 3rd-PMOS drain 84 The 3-NMOS source 65 is connected to form the input terminal 56 of the first analog transmission gate, and the 3rd-PMOS source 63 is connected to the third-NMOS drain 67 to form the output terminal 55 of the first analog transmission gate. ,

Referring to accompanying drawing 5 and accompanying drawing 6 simultaneously, and as described in Fig. 1 pixel positive addressing storage circuit 46 is by adopting P-type switched capacitor control terminal 112 to serve as described pixel positive addressing control terminal 47, P-type switched capacitor input terminal 117 is used as the positive storage input terminal 43 of the pixel, and the P-type switched capacitor output terminal 118 is used as the PMOS switched capacitor of the positive storage output terminal 42 of the pixel, or the N-type switched capacitor control terminal 114 is used as the positive addressing control terminal of the pixel 47. The N-type switched capacitor input terminal 119 serves as the positive storage input terminal 43 of the pixel, and the N-type switched capacitor output terminal 120 serves as one of the NMOS-type switched capacitors of the positive storage output terminal 42 of the pixel, and the pixel is positively seeks The address control terminal 47 is connected to the row addressing signal line 24, the pixel positive storage input terminal 43 is connected to the column display positive analog signal line 44,

Wherein as shown in the schematic diagram of the PMOS type switched capacitor circuit shown in Figure 5, the PMOS type switched capacitor is composed of at least the 6th-PMOS grid 123, the 6th-PMOS drain 124, and the 6th-PMOS source 121. The PMOS tube 125 and the MIM capacitor 115 comprising at least the upper plate 116 of the MIM capacitor and the lower plate 113 of the MIM capacitor are formed, and it is characterized in that the 6th-PMOS gate 123 serves as the P-type switched capacitor control terminal 112, the The 6th-PMOS source 121 acts as the P-type switched capacitor input 117, the 6th-PMOS drain 124 is connected to the MIM capacitor upper plate 116 to form the P-type switched capacitor output 118, and the P-type switched capacitor output 118 is formed. The lower plate 113 of the MIM capacitor is connected to the ground wire 135,

Wherein as shown in the schematic diagram of the NMOS type switched capacitor circuit shown in FIG. The NMOS transistor 129 and the MIM capacitor 115 comprising at least the upper plate 116 of the MIM capacitor and the lower plate 113 of the MIM capacitor are formed, and it is characterized in that the 6th-NMOS gate 127 serves as the N-type switched capacitor control terminal 114, the The 6th-NMOS drain 126 serves as the N-type switched capacitor input 119, the 6th-NMOS source 128 is connected to the MIM capacitor upper plate 116 to form the N-type switched capacitor output 120, the The lower plate 113 of the MIM capacitor is connected to the ground wire 135,

And as described in Figure 1, the positive analog display amplifier 49 is used as the positive display amplification bias terminal 37 by using the P-type amplifier bias terminal 99, and the P-type amplifier input terminal 97 is used as the positive display amplification input terminal 39. Amplifier output terminal 98 serves as the PMOS type double-tube common-drain amplifier of described positive display amplification output terminal 21 or adopts N-type amplifier bias terminal 109 to serve as described positive display amplification bias terminal 37, and N-type amplifier input terminal 110 serves as the described positive display amplification bias terminal 37. The positive display amplification input terminal 39 and the N-type amplifier output terminal 111 are used as one of the NMOS type dual-tube common-drain amplifiers of the positive display amplification output terminal 21, and the positive display amplification input terminal 39 and the positive storage output of the pixel terminal 42, the positive display amplification bias terminal 37 is connected to the positive bias voltage supply line 28,

Referring to accompanying drawing 7 simultaneously, and as described in Fig. 1 positive analog display transmission gate 23 is by adopting the 2nd analog transmission gate positive phase control terminal 132 to act as described positive display transmission positive phase control terminal 34, the 2nd analog transmission gate anti-phase The control terminal 133 serves as the positive display transmission inversion control terminal 32, the second analog transmission gate input terminal 130 serves as the positive display transmission input terminal 22, and the second analog transmission gate output terminal 131 serves as the positive display transmission output terminal 25 The second analog signal transmission gate constitutes, and the positive display transmission input terminal 22 is connected to the positive display amplification output terminal 21, the positive display transmission normal phase control terminal 34 is connected to the global positive display normal phase signal line 29 connection, the positive display transmission inversion control terminal 32 is connected to the global positive display inversion signal line 58,

Wherein as shown in the schematic diagram of the second analog signal transmission gate circuit shown in FIG. The 5th-PMOS transistor 145 and the 5th-NMOS transistor 149 including at least the 5th-NMOS gate 147, the 5th-NMOS drain 148, and the 5th-NMOS source 146 are composed, and it is characterized in that the 5th - The PMOS drain 142 is connected to the 5th-NMOS source 146 to form the second analog transmission gate input 130, and the 5th-NMOS drain 148 is connected to the 5th-PMOS source 143 to form the 5th-PMOS source 143. The second analog transmission gate output terminal 131, the 5th-PMOS gate 141 serves as the second analog transmission gate inverting control terminal 133, and the 5th-NMOS gate 147 serves as the second analog transmission gate Normal phase control terminal 132;

On the other hand, the negative slope signal amplifier 14 as described in Fig. 1 serves as the negative slope amplification bias terminal 35 by adopting the P-type amplifier bias terminal 99, and the P-type amplifier input terminal 97 serves as the negative slope amplification input terminal 10. , P-type amplifier output end 98 serves as the PMOS type double-tube common-drain amplifier of described negative slope amplifying output end 27 or adopts N-type amplifier bias end 109 to serve as described negative slope amplifying bias end 35, N-type amplifier input end 110 Serve as described negative slope to amplify input end 10, N-type amplifier output end 111 to serve as one of the NMOS type dual-tube common-drain amplifier of described negative slope to amplify output end 27 and form, and described negative slope amplifies bias end 35 and described The slope bias voltage supply line 18 is connected, and the negative slope amplification input terminal 10 is connected to the negative slope signal line 79,

And the negative slope signal transmission gate 40 is used as the negative slope transmission control terminal 36 by using the first analog transmission gate control terminal 54, the first analog transmission gate input terminal 56 is used as the negative slope transmission input terminal 38, the first analog The transmission gate output 55 serves as the first analog signal transmission gate of the negative slope transmission output 41, and the negative slope transmission input 38 is connected to the negative slope amplification output 27, and the negative slope transmission output 41 is connected with the column display negative analog signal line 45,

And the pixel negative addressing storage circuit 60 uses the P-type switched capacitor control terminal 112 as the pixel negative address control terminal 48, the P-type switched capacitor input terminal 117 as the pixel negative storage input terminal 59, and the P-type switch Capacitor output terminal 118 serves as the PMOS type switched capacitor of the pixel negative storage output terminal 92 or adopts N-type switched capacitor control terminal 114 as the pixel negative addressing control terminal 48, and N-type switched capacitor input terminal 119 as the pixel negative The storage input terminal 59 and the N-type switched capacitor output terminal 120 are composed of one of the NMOS-type switched capacitors serving as the negative storage output terminal 92 of the pixel, and the negative addressing control terminal 48 of the pixel is connected to the row addressing signal line 24 , the pixel negative storage input terminal 59 is connected to the column display negative analog signal line 45,

And the negative analog display amplifier 70 is used as the negative display amplification bias terminal 90 by using the P-type amplifier bias terminal 99, the P-type amplifier input terminal 97 is used as the negative display amplification input terminal 91, and the P-type amplifier output terminal 98 The PMOS type dual-tube common-drain amplifier serving as the negative display amplification output port 89 or the N-type amplifier bias port 109 is used as the negative display amplification bias port 90, and the N-type amplifier input port 110 is used as the negative display amplification input Terminal 91 and N-type amplifier output terminal 111 serve as one of the NMOS type dual-tube common-drain amplifiers of the negative display amplification output terminal 89, and the negative display amplification input terminal 91 is connected to the negative storage output terminal 92 of the pixel, The negative display amplification bias terminal 90 is connected to the negative bias voltage supply line 57,

And the negative analog display transmission gate 69 uses the second analog transmission gate positive phase control terminal 132 as the negative display transmission positive phase control terminal 72, and the second analog transmission gate inversion control terminal 133 as the negative display transmission negative phase control terminal 133. The phase control terminal 78, the second analog transmission gate input terminal 130 serve as the negative display transmission input terminal 80, and the second analog transmission gate output terminal 131 serves as the second analog signal transmission gate of the negative display transmission output terminal 71, and The negative display transmission input terminal 80 is connected to the negative display amplification output terminal 89, the negative display transmission positive phase control terminal 72 is connected to the global negative display positive phase signal line 33, and the negative display transmission inversion control Terminal 78 is connected with global negative display inversion signal line 31,

And the schematic diagram of the pixel output electrode circuit shown in FIG. 8 shows that the pixel output electrode circuit 30 is an output formed between the pixel analog signal output electrode 26 and the conductors that are close to the periphery but not in contact and connected to the ground line 135. The electrode parasitic capacitor 20 is constructed, and it is characterized in that the pixel analog signal output electrode 26 serves as one electrode plate of the output electrode parasitic capacitor 20, and the ground line 135 serves as the other electrode plate of the output electrode parasitic capacitor 20,

And as shown in FIG. 1, the pixel analog signal output electrodes 26 are respectively connected to the negative display transmission output terminal 71 and the positive display transmission output terminal 25;

Then, in conjunction with accompanying drawings 9 and 10 , the driving method of the dual-channel symmetrical slope type analog pixel driving circuit of the present invention will be further described in detail, the high level described below has the same voltage value as the level VD of the power supply line 77, and the following The low level has the same voltage value as the ground line 135 level VG:

Any display period is formed adjacent to a positive field display period and a negative field display period, and each of the positive field display period and the negative field display period is composed of a positive addressing storage circuit 46 and a negative addressing circuit 46 for the pixel. The storage circuits 60 all appear in the addressing row period of the input path state and at least one display row period that always makes the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 maintain the input disconnection state, and the addressing row The period is the same as the duration of the display line period, time is connected and collectively referred to as the line period, and in each line period, the positive ramp signal amplifier and the negative ramp signal amplifier are transmitted by the ramp bias voltage supply line 18 The bias level is configured for active operation,

And in all the display row periods of the positive field display period and the addressing row periods of its adjacent negative field display period, the negative analog display transmission gate 69 is in an off state and the negative analog display amplifier 70 is in an invalid working state, and In all the display row periods of the negative field display period and the addressing row periods of its adjacent positive field display period, the positive analog display transmission gate 23 is in an open circuit state and the positive analog display amplifier is in an ineffective working state,

And each line period is divided into four time periods T1, T2, T3, T4 and two types of positive ramp signals and negative ramp signals are respectively constructed by connecting four waveforms, and the waveform features are positive ramp signals and negative ramp signals The same highest level is the highest level of the slope, the same center level is the center level of the slope, and the same lowest level is the lowest level of the slope, and the positive slope signal jumps from the highest level of the slope in the T1 time period of each row cycle At the same time, the negative ramp signal jumps from the lowest level of the ramp to the central level of the ramp. In the T2 time period, both the positive ramp signal and the negative ramp signal are fixed at the ramp center level. In the T3 time period, the positive ramp signal changes from the ramp The center level jumps to the lowest level of the slope while the negative ramp signal jumps from the center level of the slope to the highest level of the slope, and the positive ramp signal changes incrementally from the lowest level of the slope to the highest level of the slope in the T4 time period The ramp signal changes gradually from the highest level of the ramp to the lowest level of the ramp;

As shown in FIG. 9, two kinds of four-segment waveform ramp signal waveforms of the two-way symmetrical ramp analog pixel drive circuit in one of the application scenarios where a positive field display period T_P is adjacent to a negative field display period T_N are shown (Fig. The shaded part indicates the omitted waveform),

Among them, the positive field display period T_P is composed of the addressing line period TC11 and at least one display line period TP11, the negative field display period T_N is composed of the addressing line period TC21 and at least one display line period TP21, and each line period is at T1 time The positive ramp signal Vrp_p jumps from the highest ramp level V3 to the ramp center level V2 while the negative ramp signal Vrp_n jumps from the lowest ramp level V1 to the ramp center level V2. During the T2 period, the positive ramp signal Vrp_p and the negative ramp The signal Vrp_n is fixed at the ramp center level V2, and the positive ramp signal Vrp_p jumps from the ramp center level V2 to the lowest ramp level V1 in the T3 time period, and the negative ramp signal Vrp_n jumps from the ramp center level V2 to the ramp highest level. Level V3, the positive ramp signal Vrp_p changes incrementally from the lowest ramp level V1 to the highest ramp level V3 during the T4 time period, and the negative ramp signal Vrp_n decreases from the highest ramp level V3 to the lowest ramp level V1;

As shown in Figure 10, the driving signal waveform diagram of the two-way symmetrical ramp-type analog pixel driving circuit in one of the application scenarios where a positive field display period is adjacent to a negative field display period is summarized (the shaded part in the figure represents the omitted waveform),

First, in the positive field display period T_P and the negative field display period T_N,

If both the positive slope signal amplifier 3 and the negative slope signal amplifier 14 adopt PMOS type dual-transistor common-drain amplifiers, then the characteristic of transmission on the positive bias voltage supply line 18 of the slope is lower than the voltage VD of the power supply line 77. The slope negative bias level Vbn will be input to the 1st-PMOS gate 85, and can make the 1st-PMOS transistor 88 enter the saturation region, thereby making both the positive slope signal amplifier 3 and the negative slope signal amplifier 14 It is configured as an effective working state, and if the positive slope signal amplifier 3 and the negative slope signal amplifier 14 all adopt NMOS type dual-transistor common-drain amplifiers, then what is transmitted on the slope bias voltage supply line 18 is characterized by being higher than the The slope positive bias level Vbp of the voltage VG of the ground line 135 is input to the 2nd-NMOS gate 106, and can make the 2nd-NMOS transistor 105 enter the saturation region, and then the positive slope signal amplifier 3 and negative The ramp signal amplifiers 3 are all configured to work effectively,

And only in all the display row periods of the positive field display period T_P and the addressing row periods of its adjacent negative field display period, if the negative analog display amplifier 70 adopts a PMOS type dual-transistor common-drain amplifier, the negative bias voltage The P pulse wave Vbp2n transmitted on the supply line 28 will input a high level, and make the first-PMOS gate 85 connected to the power supply line 77 level VD, so that the first-PMOS transistor 88 is turned off and then The negative analog display amplifier 70 enters an invalid working state, and if the negative analog display amplifier 70 adopts an NMOS type dual-transistor common-drain amplifier, the N pulse wave Vbn2n transmitted on the negative bias voltage supply line 28 will input a low voltage level, and make the 2nd-NMOS gate 106 connected to the ground line 135 level VG to cause the 2nd-NMOS transistor 105 to be turned off, so that the negative analog display amplifier 70 remains in an invalid working state, and has The P pulse wave signal SPn transmitted on the global negative display inversion signal line 31 is at a high level so that the 5th-PMOS grid 141 is connected to a high level, causing the 5th-PMOS transistor 145 to be turned off, and at the same time The N pulse wave signal SNn transmitted on the positive-phase signal line 33 of the global negative display is at a low level so that the 5th-NMOS gate 147 is connected to a low level and causes the 5th-NMOS transistor 149 to be turned off This further causes the negative analog display transmission gate 69 to be in an off-circuit state, thereby preventing electrical signals from driving the pixel analog signal output electrode 26 through the negative analog display transmission gate 69,

And only in all display row periods of the negative field display period T_P and the addressing row periods of its adjacent negative field display periods, if the positive analog display amplifier 49 adopts a PMOS type dual-tube common-drain amplifier, the positive bias voltage The P pulse wave Vbp2p transmitted on the supply line 28 will input a high level, and make the first-PMOS gate 85 connected to the power supply line 77 level VD, causing the first-PMOS transistor 88 to turn off Furthermore, the positive analog display amplifier 49 enters an invalid working state, and if the positive analog display amplifier 49 adopts an NMOS type dual-tube common-drain amplifier, then the N pulse wave Vbn2p transmitted on the positive bias voltage supply line 28 will be input low level, and make the 2nd-NMOS gate 106 connected to the ground line 135 level VG to cause the 2nd-NMOS transistor 105 to be turned off, so that the positive analog display amplifier 49 remains in an invalid working state, and The P pulse wave signal SPp transmitted on the global positive and negative phase signal line 58 is at a high level so that the 5th-PMOS gate 141 is connected to a high level and the 5th-PMOS transistor 145 is turned off, At the same time, the N pulse wave signal SNp transmitted on the positive phase signal line 29 of the global positive display is at a low level so that the 5th-NMOS grid 147 is connected to a low level, and the 5th-NMOS transistor 149 is turned off. The disconnection causes the positive analog display transmission gate 23 to be in an open circuit state, thereby preventing the electrical signal from driving the pixel analog signal output electrode 26 through the negative analog display transmission gate 69;

Meanwhile, in the addressing row period TC11 of the positive field display period T_P,

In the time period T1: the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 jumps from the highest ramp level V3 to the ramp center level V2 while the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79 changes from The lowest level of the slope V1 jumps to the center level of the slope V2,

And at the beginning, the pulse signal RST transmitted on the comparator reset signal line 19 is low level and the positive slope signal Vrp_p transmitted on the positive slope signal line 17 and the positive slope signal Vrp_p transmitted on the negative slope signal line 79 After the negative slope signal Vrp_n jumps to the center level V2, the rising edge signal marked by ellipse 8 triggers the enable digital signal comparator 12 to output a high level, as indicated by the one-way arrow line 9 to the first Control line 1, and make the positive slope transmission control terminal 15 and the negative slope transmission control terminal 36 both receive the pulse wave signal ENC as the high level marked by ellipse 9, and then there is a high level connected to the The 3rd-NMOS grid 66 also has the low level converted by the inverter formed by the 4th-PMOS transistor and the 4th-NMOS transistor connected to the 3rd-PMOS grid 61, and will cause the Both the positive slope signal transmission gate 6 and the negative slope signal transmission gate 40 are in the pass state, and then respectively make the analog signal SDi_p transmitted on the positive analog signal line 44 of the column display follow the transmission on the positive slope signal line 17 The positive slope signal Srp_p of the electrical signal identified by the ellipse 10 produces the electrical signal portion identified by the ellipse 11 as shown by the unidirectional arrow line 10, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 follows the negative slope The negative slope signal Srp_n transmitted on the signal line 79 is marked by the ellipse 50 as shown by the unidirectional arrow line 50 to generate the electrical signal part marked by the ellipse 51,

And if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 both use the NMOS type switched capacitor, then the output of the addressing positive pulse wave signal Sgp transmitted on the row addressing signal line 24 is elliptical The low level indicated by 12 will be input to the 6th-NMOS gate 127, and the 6th-NMOS transistor 129 will be turned off, so that the respective MIM capacitors 115 and the column display positive analog signal lines 44 and the column display negative analog signal line 45 are all in an open circuit state, and if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 all adopt the PMOS type switched capacitor, the row addressing The address signal line 24 transmits the address negative pulse wave signal Sgn, and the high level indicated by the ellipse 13 will be input to the 6th-PMOS gate 123, and the 6th-PMOS transistor 125 will be turned off, resulting in the use of The MIM capacitor 115 and the column display positive analog signal line 44 and the column display negative analog signal line 45 are all in an open circuit state, and the result will be that the pixel is positively addressing the storage circuit 46 and the The pixel negative addressing storage circuits 60 all enter the input shutdown state, and each makes the level states of the pixel positive storage output terminal 42 analog signal Vsc_p and the pixel negative storage output terminal 92 analog signal Vsc_n at the end of the last display period Continue to be stored and output respectively as ellipse 14 and ellipse 54 identification part,

And if the negative analog display amplifier 70 adopts a PMOS type dual-tube common-drain amplifier, the level of the P pulse wave Vbp2n transmitted on the negative bias voltage supply line 28 jumps from a high voltage to a level marked by an ellipse 16, And it can cause the negative analog display amplifier 70 to cause the first-PMOS transistor 88 to enter the saturation region because the first-PMOS gate 85 is connected to a level lower than the voltage VD of the power supply line 77, thereby realizing an effective Working state, and if the negative analog display amplifier 70 adopts NMOS type dual-tube common-drain amplifier, the N pulse wave Vbn2n level transmitted on the negative bias voltage supply line 28 jumps from low level to marked by ellipse 17 level, and can cause the negative analog display amplifier 70 to cause the second-NMOS transistor 105 to enter the saturation region because the second-NMOS gate 106 is connected to the level VG higher than the ground line 135, thereby realizing Effective working state, and the result will be that the level signal stored by the pixel negative addressing storage circuit 60 at the end of the last display period is driven to the negative display transmission input terminal 80 through the negative analog display amplifier 70,

And the P pulse wave signal SPn transmitted on the global negative display inversion signal line 31 is at a high level so that the 5th-PMOS gate 141 is connected to a high level and the 5th-PMOS transistor 145 is turned off , At the same time, the N pulse wave signal SNn transmitted on the positive phase signal line 33 of the global negative display is at a low level so that the 5th-NMOS grid 147 is connected to a low level, and causes the 5th-NMOS transistor 149 Turning off further causes the negative analog display transmission gate 69 to be in an off-circuit state and also causes the analog signal Vout output on the pixel analog signal output electrode 26 to continue at the level state of the output electrode parasitic capacitor 20 at the end of the last line period For example, the part marked by ellipse 6;

And in the T2 time period: the level of the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 and the level of the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79 continue to be fixed at the center level of the ramp signal V2 ,

And the pulse wave signal RST transmitted on the comparator reset signal line 19 continues to maintain the level state of the previous time period, and the pulse wave signal ENC received by the positive slope transmission control terminal 15 and the negative slope transmission control terminal 36 are both Continue to maintain the level state of the previous time period, and then respectively make the analog signal SDi_p transmitted on the positive analog signal line 44 of the column display continue to follow the positive slope signal Srp_p transmitted on the positive slope signal line 17 to generate a corresponding level State, the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 continues to follow the positive slope signal Srp_n transmitted on the negative slope signal line 79 to generate a corresponding level state,

And the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 continue to keep the input turned off because the pulse wave signal transmitted on the row addressing signal line 24 maintains the level state of the previous period. state, and respectively make the level state of the pixel marked by ellipse 14 in the last time period to store the output terminal 42 analog signal Vsc_p continue to be stored and output as indicated by unidirectional arrow line 11 and the part marked by ellipse 15, The level state of the analog signal Vsc_n of the pixel negative storage output terminal 92 identified by the ellipse 54 in the last time period continues to be stored and output as indicated by the one-way arrow line 51 and the part identified by the ellipse 55,

And the negative analog display amplifier 70 continues to maintain an effective working state because the analog signal transmitted on the negative bias voltage supply line 57 maintains the level state of the previous period,

And the P pulse wave signal SPn transmitted on the global negative display inversion signal line 31 jumps to a low level so that the 5th-PMOS gate 141 is connected to a low level, causing the 5th-PMOS transistor 145 to be connected to a low level. conduction, and at the same time, the N pulse wave signal SNn transmitted on the positive phase signal line 33 of the global negative display jumps to a high level so that the 5th-NMOS gate 147 is connected to a high level, resulting in the 5th- The NMOS transistor 149 is turned on to cause the negative analog display transmission gate 69 to be in the pass state, and also cause the analog signal Vsc_n level of the negative storage output terminal 92 of the pixel to be marked by the ellipse 55, as indicated by the unidirectional arrow line 12. It shows that the analog signal Vout generated by the pixel analog signal output electrode 26 is driven in real time by the negative analog display amplifier 70 and maintained at the level state of the output electrode parasitic capacitor 20, such as the part marked by ellipse 18 to strengthen the part marked by ellipse 6 level status;

And in the time period T3: the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 jumps from the ramp center level V3 to the lowest ramp level V2 and at the same time the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79 Jump from the ramp center level V1 to the highest ramp level V2,

And the pulse wave signal RST transmitted on the comparator reset signal line 19 continues to maintain the level state of the previous time period, and the pulse wave signal ENC received by the positive slope transmission control terminal 15 and the negative slope transmission control terminal 36 are both Continue to maintain the level state of the previous time period so that the columns displaying the analog signal SDi_p transmitted on the positive analog signal line 44 continues to follow the positive slope signal Srp_p transmitted on the positive slope signal line 17. The part marked by the ellipse 7 The portion of the electrical signal identified by the ellipse 22 is produced as shown by the one-way arrow line 8, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 continues to follow the positive ramp signal Srp_n transmitted on the negative ramp signal line 79 and is The part identified by ellipse 47 produces the electrical signal part identified by ellipse 62 as shown in unidirectional arrow line 30,

And if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 both use the NMOS type switched capacitor, then the output of the addressing positive pulse wave signal Sgp transmitted on the row addressing signal line 24 is elliptical The high level indicated by 20 will be input to the 6th-NMOS gate 127, and make the 6th-NMOS transistor 129 conduct and cause the respective MIM capacitors 115 and the columns to display positive analog signals The line 44 and the column display negative analog signal line 45 are all in a pass state, and if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 all adopt the PMOS type switched capacitor, then the row The addressing negative pulse wave signal Sgn transmitted on the addressing signal line 24 outputs a low level marked by an ellipse 21, which will be input to the 6th-PMOS gate 123, and make the 6th-PMOS transistor 125 conduct and cause The MIM capacitors 115 used respectively are in a pass state with the column display positive analog signal line 44 and the column display negative analog signal line 45, and the result will be that the pixel is addressing the storage circuit 46 and The pixel negative addressing storage circuits 60 all enter the input path state, and respectively make the column display positive analog signal SDi_p transmitted on the analog signal line 44. The part marked by the ellipse 22 will be stored in real time as indicated by the unidirectional arrow line 13 In the positive addressing storage circuit 46 of the pixel, the part marked by the ellipse 23, and the analog signal SDi_n transmitted on the negative analog signal line 45 of the column is marked by the ellipse 62, as indicated by the unidirectional arrow line 53, will be stored in real time to the The pixel negative addressing storage circuit 60 is marked by an ellipse 63,

And the P pulse wave signal SPn transmitted on the global negative display inversion signal line 31 jumps to a high level so that the 5th-PMOS gate 141 is connected to a high level, causing the 5th-PMOS transistor 145 to be connected to a high level. turn off, and at the same time, the N pulse wave signal SNn transmitted on the positive phase signal line 33 of the global negative display jumps to a low level so that the 5th-NMOS gate 147 is connected to a low level, resulting in the 5th- The NMOS transistor 149 is turned off, which in turn causes the negative analog display transmission gate 69 to be in an off-circuit state and also causes the pixel analog signal output electrode 26 to produce a level state indicated by the ellipse 18 in the upper time period, such as the one-way arrow line 14 indicates the part that continues to be transmitted as identified by ellipse 19,

And if the negative analog display amplifier 70 adopts a PMOS type dual-tube common-drain amplifier, then the P pulse wave Vbp2n level transmitted on the negative bias voltage supply line 28 jumps up to a high level again, and makes the first- The PMOS grid 85 is connected to the power supply line 77 level VD to cause the first-PMOS transistor 88 to be turned off, thereby causing the negative analog display amplifier 70 to enter an invalid working state, and if the negative analog display amplifier 70 If the NMOS type dual-tube common-drain amplifier is adopted, the N pulse wave Vbn2p level transmitted on the negative bias voltage supply line 28 jumps down to a low level again, and the second-NMOS grid 106 is connected to the The ground line 135 level VG causes the second-NMOS transistor 105 to be turned off, thereby causing the negative analog display amplifier 70 to enter an invalid working state;

And in the T4 time period: and at the beginning, the counter 8 resets to zero and starts counting, and the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 starts from the lowest level V1 of the ramp and synchronizes with the counting speed of the counter 8 Incrementally change to the highest slope level V3, the negative slope signal Vrp_n transmitted on the negative slope signal line 79 starts from the highest slope level V3 and decreases synchronously with the counting speed of the counter 8 to the lowest slope level V1,

And the pulse wave signal RST transmitted on the comparator reset signal line 19 continues to maintain the level state of the previous time period, and the pulse wave signal ENC received by the positive slope transmission control terminal 15 and the negative slope transmission control terminal 36 are both Continue to maintain the level state of the previous time period, and then respectively make the analog signal SDi_p transmitted on the positive analog signal line 44 of the column display continue to follow the positive slope signal Srp_p transmitted on the positive slope signal line 17 to generate a corresponding level State, the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 continues to follow the positive slope signal Srp_n transmitted on the negative slope signal line 79 to generate a corresponding level state,

And if the number produced by the counter 8 is equal to the number stored in the digital signal latch 11 when passing through the Tx1 time not exceeding the T4 time length, it will trigger the enabling digital signal comparator 12 to output a low level to the The first control line 1 makes the positive slope transmission control terminal 15 and the negative slope transmission control terminal 36 both receive the pulse wave signal ENC as a low level marked by an ellipse 24, and then a low level is input to The 3rd-NMOS gate 66 has a converted high level connected to the 3rd-PMOS gate 61 so that both the positive ramp signal transmission gate 6 and the negative ramp signal transmission gate 40 are in an off state , and then respectively make the column show that the analog signal SDi_p transmitted on the positive analog signal line 44 no longer follows the level change of the positive slope signal Srp_p transmitted on the positive slope signal line 17 in real time and remains fixed as indicated by the ellipse 25 level until the positive slope signal transmission gate 52 is in the pass state again, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 no longer follows the negative slope signal Srp_n transmitted on the negative slope signal line 79 in real time. level change and remain at a fixed level indicated by ellipse 65 until the negative ramp signal transmission gate 40 is in the on state again,

And the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 continue to maintain the input channel state because the pulse wave signal transmitted on the row addressing signal line 24 maintains the level state of the previous period , and respectively make the analog signal SDi_p transmitted on the analog signal line 44 of the column display to be updated by the ellipse 25 as indicated by the unidirectional arrow line 15 to drive the analog signal Vsc_p of the pixel storage output 42 to be updated by the ellipse 26 The fixed level part of the mark, the analog signal SDi_n transmitted on the negative analog signal line 45 shown in the column is updated by the analog signal Vsc_n driving the negative storage output terminal 92 of the pixel as indicated by the unidirectional arrow line 55 as indicated by the ellipse 65. The fixed level portion identified by oval 66,

And the level of the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 increases to the highest level of the ramp signal V3 while the level of the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79 decreases to The ramp signal is at a low level V1, and the counter 8 also counts to a full value,

And the negative analog display amplifier 70 maintains an invalid working state because the pulse wave signal transmitted on the negative bias voltage supply line 28 continues the level state at the end of the previous time period, and the negative analog display transmission gate 69 maintains an invalid working state because of the negative bias voltage supply line 28. The P pulse wave signal SPn transmitted on the global negative display anti-phase signal line 31 and the N pulse wave signal SNn transmitted on the global negative display positive phase signal line 33 continue to the level at the end of the previous time period and then maintain the off state , and also cause the analog signal Vout output on the analog signal output electrode 26 of the pixel to continue the level state identified by the ellipse 19 in the last period of time, as shown by the unidirectional arrow line 16, to produce the part identified by the ellipse 27;

Next, in the display line period TP11 of the positive field display period T_P,

During T1, T2, T3, T4 time periods: and the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17, the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79, the comparator reset signal line 19 The pulse wave signal RST transmitted above repeats the waveform state in the previous line cycle,

And if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 both use the NMOS type switched capacitor, then the output of the addressing positive pulse wave signal Sgp transmitted on the row addressing signal line 24 is elliptical The low level indicated by 28 will be input to the 6th-NMOS gate 127, and make the 6th-NMOS transistor 129 turn off and cause the respective MIM capacitors 115 and the columns to display positive analog signals The line 44 and the column display negative analog signal line 45 are all in an open circuit state, and if the pixel positive addressing storage circuit 46 and the pixel negative addressing storage circuit 60 all adopt the PMOS type switched capacitor, then the row The addressing negative pulse wave signal Sgn transmitted on the addressing signal line 24 outputs a high level marked by an ellipse 29, which will be input to the 6th-PMOS gate 123, and cause the 6th-PMOS transistor 125 to be turned off and cause The MIM capacitors 115 used respectively are in an open circuit state with the column display positive analog signal line 44 and the column display negative analog signal line 45, and the result will be that the pixel positively addresses the storage circuit 46 and the column display negative analog signal line 45. The pixel negative addressing storage circuits 60 always maintain the input off state, and respectively make the level state of the analog signal Vsc_p of the pixel positive storage output terminal 42 respectively marked by the ellipse 26 in the last row period T4 continue to be controlled. Store and output the level state of the negative storage output terminal 92 analog signal Vsc_n of the negative storage output terminal 92 of the pixel identified by the ellipse 66, as shown by the unidirectional arrow line 17, which is identified by the ellipse 30 and can continue to be transmitted and maintained in the adjacent row display period Continue to be stored and output as shown by the one-way arrow line 57 and the part identified by the ellipse 70 and can continue to be maintained in the adjacent row display period,

And in the T1, T2, T3 time periods: and the pulse wave signal ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 repeatedly transmits the waveform state in the previous line period, and respectively makes the columns It shows that the analog signal SDi_p transmitted on the positive analog signal line 44 continues to follow the positive slope signal Srp_p transmitted on the positive slope signal line 17 to generate a corresponding level state, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 continues Following the positive ramp signal Srp_n transmitted on the negative ramp signal line 79 generates a corresponding level state,

And in the T1 time period: and if the positive analog display amplifier 49 adopts a PMOS type double-tube common-drain amplifier, then the P pulse wave Vbp2p level transmitted on the positive bias voltage supply line 28 jumps from a high voltage to an elliptical 48, and can cause the positive analog display amplifier 49 to cause the first-PMOS transistor 88 to enter saturation because the first-PMOS gate 85 is connected to the level VD lower than the power supply line 77 area and then realize the effective working state, and if the positive analog display amplifier 49 adopts NMOS type double-tube common-drain amplifier, then the N pulse wave Vbn2p level transmitted on the positive bias voltage supply line 28 jumps from low level to The level marked by the ellipse 49 can make the positive analog display amplifier 49 cause the second-NMOS transistor 105 to be connected to the level VG higher than the ground line 135 because the second-NMOS gate 106 is connected to the ground line 135. Entering the saturation region and then realizing the effective working state, and the result that will be caused is that the level signal saved by the pixel positive addressing storage circuit 46 at the end of the last line period is driven to the positive display transmission through the positive analog display amplifier 49 input 22,

And the P pulse wave signal SPp transmitted on the global positive display and inversion signal line 58 is at a high level so that the 5th-PMOS gate 141 is connected to a high level and the 5th-PMOS transistor 145 is turned off , At the same time, the N pulse wave signal SNp transmitted on the positive-phase signal line 29 of the global positive display is at a low level so that the 5th-NMOS gate 147 is connected to a low level and the 5th-NMOS transistor 149 is turned off and then cause the positive analog display transmission gate 23 to be in an off state and also cause the level part of the analog signal Vout output on the pixel analog signal output electrode 26 to be marked by the ellipse 31 to continue as indicated by the one-way arrow line 18 The level state marked by ellipse 27 in the last time period,

And in the T2 time period: the positive analog display amplifier 49 continues to maintain an effective working state because the analog signal transmitted on the positive bias voltage supply line 28 maintains the level state of the previous time period,

And the P pulse wave signal SPp transmitted on the global positive display inversion signal line 58 jumps to a low level so that the 5th-PMOS gate 141 is connected to a low level, causing the 5th-PMOS transistor 145 to be connected to a low level. conduction, and at the same time, the N pulse wave signal SNp transmitted on the positive phase signal line 29 of the global positive display jumps to a high level so that the 5th-NMOS gate 147 is connected to a high level, resulting in the 5th- The NMOS transistor 149 is turned on, which in turn causes the positive analog display transmission gate 23 to be in a pass state and also causes the pixel to store the level portion of the analog signal Vsc_p at the output terminal 42 marked by the ellipse 30 , as shown in the unidirectional arrow line 19 It is shown that the analog signal Vout of the pixel analog signal output electrode 26 is driven and updated in real time by the positive analog display amplifier 49, as indicated by the ellipse 32 and kept in the parasitic capacitor 20 of the output electrode,

And in the T3, T4 time period: and if the positive analog display amplifier 49 adopts a PMOS type dual-tube common-drain amplifier, then the P pulse wave Vbp2p level transmitted on the positive bias voltage supply line 28 jumps up to a high level again , and make the first-PMOS gate 85 connected to the power supply line 77 level VD to cause the first-PMOS transistor 88 to be turned off and then make the positive analog display amplifier 49 enter an invalid working state, and If the positive analog display amplifier 49 adopts an NMOS type dual-tube common-drain amplifier, then the N pulse wave Vbn2p level transmitted on the positive bias voltage supply line 28 jumps down to a low level again, and makes the 2- The NMOS gate 106 is connected to the level VG of the ground line 135 to cause the second-NMOS transistor 105 to be turned off, thereby causing the positive analog display amplifier 49 to enter an invalid working state,

And the P pulse wave signal SPp transmitted on the global positive display antiphase signal line 58 is restored to high level, and the N pulse wave signal SNp transmitted on the global positive display positive phase signal line 29 is restored to low level Leveling makes the positive analog display transfer gate 23 again in the off-circuit state, causing the analog signal Vout output on the pixel analog signal output electrode 26 to be marked by the ellipse 33 as indicated by the unidirectional arrow line 20 to continue the previous period of time The level state indicated by ellipse 32,

And if the number produced by the counter 8 is equal to the number stored in the digital signal latch 11 when passing through the Tx2 time of not exceeding the T4 time length, it will trigger the enabling digital signal comparator 12 to output a low level to the The first control line 1, and make the positive slope transmission control terminal 15 and the negative slope transmission control terminal 36 all receive the low level of the pulse wave signal ENC, and then make the columns display the positive analog signal line 44 respectively The analog signal SDi_p transmitted above no longer follows the level change of the positive slope signal Srp_p transmitted on the positive slope signal line 17 in real time, and remains at the fixed level part marked by the ellipse 34 until the positive slope signal transmission gate 52 is again at Path state, the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 no longer follows the level change of the negative slope signal Srp_n transmitted on the negative slope signal line 79 in real time, but remains at a fixed level marked by the ellipse 74 section until the negative ramp signal transmission gate 40 is again in the ON state,

And the level of the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 increases to the highest level of the ramp signal V3 while the level of the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79 decreases to The ramp signal is low level V1, and the counter 8 also counts to a full value;

Then, in the addressing row period TC21 of the negative field display period T_N,

During T1, T2, T3, T4 time periods: and the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17, the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79, the comparator reset signal line 19 The pulse wave signal RST transmitted on the above, the pulse wave signal transmitted on the positive bias voltage supply line 28, the pulse wave signal transmitted on the negative bias voltage supply line 28, the global positive display positive phase signal line 29 The N pulse wave signal SNp transmitted on the above, the P pulse wave signal SPp transmitted on the global positive display anti-phase signal line 58, the N pulse wave signal SNn transmitted on the global negative display positive phase signal line 33, the global The P pulse wave signal SPn transmitted on the negative display inversion signal line 31 repeats the waveform state transmitted in the display line period of the adjacent positive field display period T_P,

And in the T1, T2, T3 time periods: and the pulse wave signal ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 repeatedly transmits the waveform state in the previous line period, and respectively makes the columns It shows that the analog signal SDi_p transmitted on the positive analog signal line 44 continues to follow the positive slope signal Srp_p transmitted on the positive slope signal line 17 to generate a corresponding level state, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 continues Following the positive ramp signal Srp_n transmitted on the negative ramp signal line 79 generates a corresponding level state,

And in the T1 and T2 time periods: and when the pulse wave signal transmitted on the row addressing signal line 24 appears in the level state of the adjacent positive field display period T_N addressing row period TC11 in the same time period, the pixel is addressing Both the address storage circuit 46 and the pixel negative address storage circuit 60 maintain the input off state, and respectively make the pixel indicated by the ellipse 30 in the last time period store the level state of the analog signal Vsc_p of the output terminal 42 Continue to be transmitted and stored and output as shown by the one-way arrow line 21, which is indicated by the ellipse 35 and the level state of the pixel negative storage output terminal 92 analog signal Vsc_n identified by the ellipse 70 in the previous time period continues to be transmitted and stored And output the part identified by the ellipse 75 as shown in the one-way arrow line 61,

And in the T1 time period: and the positive analog display amplifier 49 starts to enter an effective working state because the analog signal transmitted on the positive bias voltage supply line 28 maintains the level state of the previous time period, and the positive analog The display transmission gate 23 is because the P pulse wave signal SPp transmitted on the anti-phase signal line 58 of the global positive display and the N pulse wave signal SNp transmitted on the positive phase signal line 29 of the global positive display continue the current at the end of the previous time period. If the level continues to be in the off-circuit state, the analog signal Vout output on the analog signal output electrode 26 of the pixel is indicated by the ellipse 33. As indicated by the one-way arrow line 22, it continues to be held in the parasitic capacitor 20 of the output electrode for the previous period. The level state indicated by ellipse 36,

And in the T2 time period: and the positive analog display amplifier 49 continues to maintain an effective working state because the pulse wave signal transmitted on the positive bias voltage supply line 28 maintains the level state of the previous time period, and there is the The P pulse wave signal SPp transmitted on the global positive display anti-phase signal line 58 jumps to a low level, and at the same time, the N pulse wave signal SNp transmitted on the positive phase signal line 29 of the global positive display jumps to a high level so that The passage state of the positive analog display transmission gate 23 will cause the analog signal Vsc_p level of the positive storage output terminal 42 of the pixel to be marked by the ellipse 35, and the part indicated by the unidirectional arrow line 23 will pass through the positive analog display amplifier 49 as indicated by the one-way arrow line 23 Drive the pixel analog signal output electrode 26 in real time to generate and maintain the level state of the output electrode parasitic capacitor 20, such as the part marked by the ellipse 37 to enhance the level state of the part marked by the ellipse 36,

And in the T3 and T4 time periods: and when the pulse wave signal transmitted on the row addressing signal line 24 has a level state of the same time period as the addressing row period TC11 of the positive field display period T_N, the pixel is being addressed Both the storage circuit 46 and the negative addressing storage circuit 60 of the pixel enter and maintain the conduction state, and respectively make the column display positive analog signal SDi_p transmitted on the analog signal line 44 marked by the ellipse 38 as the one-way arrow line 24 The analog signal Vsc_p schematically driving the positive storage output terminal 42 of the pixel is updated to a fixed level part marked by an ellipse 39, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 is marked by an ellipse 78 as a unidirectional The arrow line 56 indicates that the analog signal Vsc_n driving the negative storage output terminal 92 of the pixel is updated to a fixed level part marked by an ellipse 79,

And when the pulse wave signal transmitted on the positive bias voltage supply line 28 has a level state of the same time period as the display line period of the adjacent positive field display period T_N, the positive analog display amplifier 49 enters an invalid working state, and The P pulse wave signal SPp transmitted on the global positive display anti-phase signal line 58 is restored to a high level, and the N pulse wave signal SNp transmitted on the global positive display positive phase signal line 29 is restored to a low level Make the positive analog display transmission gate 23 to be in the disconnected state again, causing the analog signal Vout output on the pixel analog signal output electrode 26 to be marked by the level part of the ellipse 40, as indicated by the one-way arrow line 25, continuing the previous period of time The level state of ellipse 37 marks,

And if the number produced by the counter 8 is equal to the number stored in the digital signal latch 11 when passing through the Ty1 time not exceeding the T4 time length, it will trigger the enabling digital signal comparator 12 to output a low level to the The first control line 1, and respectively cause the analog signal SDi_p transmitted on the positive analog signal line 44 of the column display to no longer follow the level change of the positive slope signal Srp_p transmitted on the positive slope signal line 17 in real time and keep being elliptical. 38 marks the fixed level part until the positive slope signal transmission gate 52 is in the pass state again, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 no longer follows the signal transmitted on the negative slope signal line 79 in real time. The level of the negative ramp signal Srp_n changes and remains at the fixed level part marked by the ellipse 78 until the negative ramp signal transmission gate 40 is in the pass state again,

And the level of the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 increases to the highest level of the ramp signal V3 while the level of the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79 decreases to The ramp signal is low level V1, and the counter 8 also counts to a full value;

Next, in the display line period TP21 of the negative field display period T_N,

During T1, T2, T3, T4 time periods: and the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17, the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79, the comparator reset signal line 19 The pulse wave signal RST transmitted on the above, the pulse wave signal transmitted on the positive bias voltage supply line 28, the pulse wave signal transmitted on the negative bias voltage supply line 28, the global positive display positive phase signal line 29 The N pulse wave signal SNp transmitted on the above, the P pulse wave signal SPp transmitted on the global positive display anti-phase signal line 58, the N pulse wave signal SNn transmitted on the global negative display positive phase signal line 33, the global The P pulse wave signal SPn transmitted on the negative display inversion signal line 31 repeats the waveform state transmitted in the addressing row period TC11 of the previous adjacent positive field display period T_P,

And the addressing positive pulse wave signal Sgp transmitted on the row addressing signal line 24 remains at the low level indicated by the ellipse 81 and the addressing negative pulse wave signal Sgn transmitted on the row addressing signal line 24 remains at the level indicated by the ellipse 42 A high level will respectively cause the positive addressing storage circuit 46 of the pixel and the negative addressing storage circuit 60 of the pixel to maintain the input off state all the time, and make the said The level state of the analog signal Vsc_p at the positive storage output terminal 42 of the pixel is continuously stored and output as the ellipse 43 marked part, and the voltage level of the negative storage output terminal 92 analog signal Vsc_n of the pixel negative storage output terminal 92 identified by the ellipse 79 is shown by the unidirectional arrow line 26. The flat state continues to be stored as indicated by the one-way arrow line 66 and is output as an ellipse 83 marking part,

And in the T1, T2, T3 time periods: and the pulse wave signal ENC received by the positive ramp transmission control terminal 15 and the negative ramp transmission control terminal 36 repeatedly transmits the waveform state in the previous line period, and respectively makes the columns It shows that the analog signal SDi_p transmitted on the positive analog signal line 44 continues to follow the positive slope signal Srp_p transmitted on the positive slope signal line 17 to generate a corresponding level state, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 continues Following the positive ramp signal Srp_n transmitted on the negative ramp signal line 79 generates a corresponding level state,

And in the T1 time period: and the negative analog display amplifier 70 enters an effective working state because the negative bias voltage supply line 57 starts to transmit an active level, and the positive analog display transmission gate 23 enters an effective working state because the global positive Display the P pulse wave signal SPp transmitted on the anti-phase signal line 58 and the global positive display N pulse wave signal SNp transmitted on the normal phase signal line 29 to continue the level at the end of the previous period and continue to be in the off-circuit state, causing the pixel The level part of the analog signal Vout output on the analog signal output electrode 26 marked by the ellipse 44 is shown by the unidirectional arrow line 27 and continues to remain at the level state marked by the ellipse 40 of the output electrode parasitic capacitor 20 for a period of time,

And in the T2 time period: and the positive analog display amplifier 49 continues to maintain an effective working state because the analog signal transmitted on the positive bias voltage supply line 28 maintains the level state of the previous time period,

And the P pulse wave signal SPn transmitted on the negative phase signal line 31 of the global negative display jumps to a low level and the N pulse wave signal SNn transmitted on the positive phase signal line 33 of the global negative display jumps to a high level Level, and then cause the negative analog display transmission gate 69 to be in the pass state, causing the analog signal Vsc_n level of the negative storage output terminal 92 of the pixel to be marked by the ellipse 83, as indicated by the one-way arrow line 28 through the negative The analog display amplifier 70 drives the pixel analog signal output electrode 26 in real time, and generates and maintains the level state of the output electrode parasitic capacitor 20, such as the part marked by the ellipse 45 to update the level state of the part marked by the ellipse 44,

And in the T3 and T4 time periods: the negative analog display amplifier 70 enters the invalid working state because the negative bias voltage supply line 57 resumes transmission of the inactive level,

And the P pulse wave signal SPn transmitted on the global negative display anti-phase signal line 31 is restored to high level and the N pulse wave signal SNn transmitted on the global negative display positive phase signal line 33 is restored to low level, And further cause the negative analog display transmission gate 69 to be in an open circuit state, causing the analog signal Vout output on the pixel analog signal output electrode 26 to be marked by the level part of the ellipse 45 as indicated by the one-way arrow line 29 to continue the previous time period The level state indicated by ellipse 46,

And if the number generated by the counter 8 is equal to the number stored in the digital signal latch 11 when passing through the Ty2 time not exceeding the T4 time length, it will trigger the enabling digital signal comparator 12 to output a low level to the The first control line 1, and respectively make the analog signal SDi_p transmitted on the positive analog signal line 44 of the column display no longer follow the level change of the positive slope signal Srp_p transmitted on the positive slope signal line 17 in real time and keep being elliptical. 41 marks the fixed level part until the positive slope signal transmission gate 52 is in the pass state again, and the column shows that the analog signal SDi_n transmitted on the negative analog signal line 45 no longer follows the signal transmitted on the negative slope signal line 79 in real time. The level of the negative ramp signal Srp_n changes and remains at the fixed level part marked by the ellipse 87 until the negative ramp signal transmission gate 40 is in the pass state again,

And the level of the positive ramp signal Vrp_p transmitted on the positive ramp signal line 17 increases to the highest level of the ramp signal V3 while the level of the negative ramp signal Vrp_n transmitted on the negative ramp signal line 79 decreases to The ramp signal is at a low level V1, and the counter 8 also counts to a full value,

As a result, the analog signal Vout waveform output on the pixel analog signal output electrode 26 is characterized in that it is divided into a positive field display part and a negative field display part, wherein the positive field display part is generated at least in the row display period of the positive field display period. The part marked by ellipse 32 and ellipse 33 and the part marked by ellipse 36, ellipse 37 and ellipse 40 in the row addressing period of the adjacent negative field display period and the row display period T1 time period of the negative field display period The part marked by ellipse 44 in it is formed, wherein the negative field display part consists of the part marked by ellipse 45 and ellipse 46 at least in the row display period of the negative field display period and the row addressing period produced in the adjacent positive field display period The part identified by ellipse 6, ellipse 18, ellipse 19, and ellipse 27 and the part marked by ellipse 31 in the line display cycle T1 time period of the positive field display cycle,

And the driving method also includes: in each row cycle, the four time periods T1, T2, T3, T4 are sequentially performed, and then go round and round, so that each display cycle can be connected between the output of the pixel analog signal output electrode 26 and the current display. The digital signal stored in the digital signal latch 11 during the row addressing period of the period corresponds to an analog level.

It should be clear that the present invention is not limited to the embodiments here, and obvious improvements and modifications made by those skilled in the art according to the disclosure of the present invention should be within the protection scope of the present invention.

Claims (9)

1. Two-way symmetry slope type analog pixel drive circuit, characterized by: the circuit is composed of a digital signal latch, a counter, an enable digital signal comparator, a positive ramp signal amplifier, a positive ramp signal transfer gate, a pixel positive addressing storage circuit, a positive analog display amplifier, a positive analog display transfer gate, a negative ramp signal amplifier, a negative ramp signal transfer gate, a pixel negative addressing storage circuit, a negative analog display amplifier, a negative analog display transfer gate, a pixel output electrode circuit, and a display digital signal input bus, a comparator reset signal line, a positive ramp signal line, a negative ramp signal line, a ramp bias voltage supply line, a row addressing signal line, a positive bias voltage supply line, a negative bias voltage supply line, a global positive display positive phase signal line, a global positive display reverse phase signal line, a global negative display positive phase signal line, a global negative display reverse phase signal line, a column display positive analog signal line, and a column display negative analog signal line,

and the positive slope signal line, the positive slope signal amplifier, the positive slope signal transmission gate, the column display positive analog signal line, the pixel positive addressing storage circuit, the positive analog display amplifier and the positive analog display transmission gate are electrically connected in series to form a functional circuit to process the positive slope signal constructed by connecting four sections of waveforms,

and the negative slope signal line, the negative slope signal amplifier, the negative slope signal transmission gate, the column display negative analog signal line, the pixel negative addressing storage circuit, the negative analog display amplifier and the negative analog display transmission gate are electrically connected in series to form another functional circuit to process the negative slope signal constructed by connecting four sections of waveforms,

and the positive analog display transmission gate and the negative analog display transmission gate both output level signals to the pixel output electrode circuit, and the digital signal latch has the same number of bits as the counter, and is further configured with: the 2 nd connecting wire, the 5 th connecting wire, the 6 th connecting wire, reset connecting wire, the 1 st control line, power supply line, earth connection, just the digital signal latch passes through the 2 nd connecting wire receive by show the multi-bit digital signal of digital signal input bus transmission stores, just enable the digital signal comparator through the 5 th connecting wire receive by the multi-bit count digital signal that the counter sent, through the 6 th connecting wire receive by the multi-bit storage digital signal that the digital signal latch sent, through the reset connecting wire receive by the reset level signal that the comparator reset signal line sent, through the 1 st control line positive slope signal transmission gate with negative slope signal transmission gate sends the control level signal.

2. A two-way symmetric ramp type analog pixel driving circuit according to claim 1, wherein: the positive slope signal amplifier is configured with a positive slope amplification bias terminal, a positive slope amplification input terminal, a positive slope amplification output terminal, and the positive slope signal transmission gate is configured with a positive slope transmission control terminal, a positive slope transmission input terminal, a positive slope transmission output terminal, and the pixel positive addressing storage circuit is configured with a pixel positive addressing control terminal, a pixel positive storage input terminal, a pixel positive storage output terminal, and the positive analog display amplifier is configured with a positive display amplification bias terminal, a positive display amplification input terminal, a positive display amplification output terminal, and the positive analog display transmission gate is configured with a positive display transmission reverse phase control terminal, a positive display transmission input terminal, a positive display transmission output terminal, and the negative slope signal amplifier is configured with a negative slope amplification bias terminal, a negative slope amplification input terminal, and the negative slope signal transmission gate is configured with a negative slope transmission control terminal, a negative slope transmission input terminal, a negative slope transmission output terminal, and the pixel negative addressing storage circuit is configured with a pixel negative addressing control terminal, a pixel negative slope amplification input terminal, a negative slope amplification output terminal, a negative slope transmission output terminal, and a negative analog display output terminal,

and the enabling digital signal comparator is provided with a high level output to the 1 st control line when the rising edge of the enabling signal transmitted on the comparator resetting signal line is received through the resetting connection line and a low level output to the 1 st control line when the digital signal received from the digital signal latch through the 6 th connection line is compared with the digital signal received from the counter through the 5 th connection line and the two digital signals are the same.

3. A two-way symmetric ramp type analog pixel driving circuit according to claim 1, wherein: the positive slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P type amplifier offset end as the positive slope amplification offset end, a P type amplifier input end as the positive slope amplification input end and a P type amplifier output end as the positive slope amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N type amplifier offset end as the positive slope amplification offset end, an N type amplifier input end as the positive slope amplification input end and an N type amplifier output end as the positive slope amplification output end, the positive slope amplification offset end is connected with the slope bias voltage supply line, and the positive slope amplification input end is connected with the positive slope signal line,

the positive slope signal transmission gate is composed of a 1 st analog signal transmission gate which adopts a 1 st analog transmission gate control end as the positive slope transmission control end, a 1 st analog transmission gate input end as the positive slope transmission input end and a 1 st analog transmission gate output end as the positive slope transmission output end, the positive slope transmission input end is connected with the positive slope amplification output end, and the positive slope transmission output end is connected with the column display positive analog signal line;

the negative slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P-type amplifier offset end as the negative slope amplification offset end, a P-type amplifier input end as the negative slope amplification input end and a P-type amplifier output end as the negative slope amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N-type amplifier offset end as the negative slope amplification offset end, an N-type amplifier input end as the negative slope amplification input end and an N-type amplifier output end as the negative slope amplification output end, the negative slope amplification offset end is connected with the slope bias voltage supply line, and the negative slope amplification output end is connected with the negative slope signal line,

the negative slope signal transmission gate is composed of a 1 st analog signal transmission gate which adopts a 1 st analog transmission gate control end as the negative slope transmission control end, a 1 st analog transmission gate input end as the negative slope transmission input end and a 1 st analog transmission gate output end as the negative slope transmission output end, the negative slope transmission input end is connected with the negative slope amplification output end, and the negative slope transmission output end is connected with the column display negative analog signal line;

wherein the 1 st analog signal transmission gate is composed of a 3 rd PMOS transistor at least comprising a 3 rd PMOS gate, a 3 rd PMOS drain and a 3 rd PMOS source, a 3 rd NMOS transistor at least comprising a 3 rd NMOS gate, a 3 rd NMOS drain and a 3 rd NMOS source, a 4 th PMOS transistor at least comprising a 4 th PMOS gate, a 4 th PMOS drain and a 4 th PMOS source, and a 4 th NMOS transistor at least comprising a 4 th NMOS gate, a 4 th NMOS drain and a 4 th NMOS source, and is further configured with: the 4 th-NMOS gate, the 4 th-PMOS gate and the 3 rd-NMOS gate are connected to form the control end of the 1 st analog transmission gate, the 4 th-NMOS source, the 4 th-PMOS drain and the 3 rd-PMOS gate are connected with each other, the 4 th-PMOS source is connected to the power supply line, the 4 th-NMOS drain is connected to the ground line, the 3 rd-PMOS drain and the 3 rd-NMOS source are connected to form the input end of the 1 st analog transmission gate, and the 3 rd-PMOS source and the 3 rd-NMOS drain are connected to form the output end of the 1 st analog transmission gate.

4. The two-way symmetric ramp-type analog pixel driving circuit according to claim 1, wherein: the pixel positive addressing storage circuit is composed of one of a P-type switch capacitor control end serving as the pixel positive addressing control end, a P-type switch capacitor input end serving as the pixel positive storage input end, a P-type switch capacitor output end serving as a PMOS-type switch capacitor of the pixel positive storage output end or an N-type switch capacitor control end serving as the pixel positive addressing control end, an N-type switch capacitor input end serving as the pixel positive storage input end and an N-type switch capacitor output end serving as an NMOS-type switch capacitor of the pixel positive storage output end, the pixel positive addressing control end is connected with the row addressing signal line, the pixel positive storage input end is connected with the column display positive analog signal line,

the positive analog display amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P-type amplifier offset end as the positive display amplification offset end, a P-type amplifier input end as the positive display amplification input end and a P-type amplifier output end as the positive display amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N-type amplifier offset end as the positive display amplification offset end, an N-type amplifier input end as the positive display amplification input end and an N-type amplifier output end as the positive display amplification output end, the positive display amplification input end is connected with the pixel positive storage output end, and the positive display amplification offset end is connected with the positive bias voltage supply line;

the pixel negative addressing storage circuit is composed of one of a P-type switch capacitor control end serving as the pixel negative addressing control end, a P-type switch capacitor input end serving as the pixel negative storage input end, a P-type switch capacitor output end serving as a PMOS-type switch capacitor of the pixel negative storage output end or an N-type switch capacitor control end serving as the pixel negative addressing control end, an N-type switch capacitor input end serving as the pixel negative storage input end, and an N-type switch capacitor output end serving as an NMOS-type switch capacitor of the pixel negative storage output end, the pixel negative addressing control end is connected with the row addressing signal line, the pixel negative storage input end is connected with the column display negative analog signal line,

and the negative analog display amplifier is composed of one of a PMOS type double-tube common-drain amplifier which adopts a P-type amplifier bias end as the negative display amplification bias end, a P-type amplifier input end as the negative display amplification input end and a P-type amplifier output end as the negative display amplification output end, or an NMOS type double-tube common-drain amplifier which adopts an N-type amplifier bias end as the negative display amplification bias end, an N-type amplifier input end as the negative display amplification input end and an N-type amplifier output end as the negative display amplification output end, the negative display amplification input end is connected with the pixel negative storage output end, and the negative display amplification bias end is connected with the negative bias voltage supply line.

5. A two-way symmetric ramp type analog pixel driving circuit according to claim 1, wherein: the positive analog display transmission gate is composed of a 2 nd analog signal transmission gate which adopts a 2 nd analog transmission gate positive phase control end as the positive display transmission positive phase control end, a 2 nd analog transmission gate reverse phase control end as the positive display transmission reverse phase control end, a 2 nd analog transmission gate input end as the positive display transmission input end and a 2 nd analog transmission gate output end as the positive display transmission output end, the positive display transmission input end is connected with the positive display amplification output end, the positive display transmission positive phase control end is connected with the global positive display positive phase signal line, and the positive display transmission reverse phase control end is connected with the global positive display reverse phase signal line;

the negative analog display transmission gate is composed of a 2 nd analog signal transmission gate which adopts a 2 nd analog transmission gate positive phase control end as the negative display transmission positive phase control end, a 2 nd analog transmission gate reverse phase control end as the negative display transmission reverse phase control end, a 2 nd analog transmission gate input end as the negative display transmission input end and a 2 nd analog transmission gate output end as the negative display transmission output end, the negative display transmission input end is connected with the negative display amplification output end, the negative display transmission positive phase control end is connected with the global negative display positive phase signal line, the negative display transmission reverse phase control end is connected with the global negative display reverse phase signal line,

the 2 nd analog signal transmission gate is composed of a 5 th-PMOS tube at least comprising a 5 th-PMOS grid electrode, a 5 th-PMOS drain electrode and a 5 th-PMOS tube at least comprising a 5 th-NMOS grid electrode, a 5 th-NMOS drain electrode and a 5 th-NMOS source electrode, the 5 th-PMOS drain electrode is connected with the 5 th-NMOS source electrode to form the input end of the 2 nd analog transmission gate, the 5 th-NMOS drain electrode is connected with the 5 th-PMOS source electrode to form the output end of the 2 nd analog transmission gate, the 5 th-PMOS grid electrode serves as the inverting control end of the 2 nd analog transmission gate, and the 5 th-NMOS grid electrode serves as the non-inverting control end of the 2 nd analog transmission gate;

and the pixel output electrode circuit is constructed by an output electrode parasitic capacitor formed between the pixel analog signal output electrode and a conductor which is close to the periphery but does not make contact and is connected to the ground line, and the pixel analog signal output electrode serves as one electrode plate of the output electrode parasitic capacitor, the ground line serves as the other electrode plate of the output electrode parasitic capacitor,

and the pixel analog signal output electrode is respectively connected with the negative display transmission output end and the positive display transmission output end.

6. A two-way symmetric ramp-type analog pixel driving circuit according to claim 3, wherein: the PMOS type double-tube common-drain amplifier is composed of a 1 st PMOS tube at least comprising a 1 st PMOS gate, a 1 st PMOS source and a 1 st PMOS drain and a 2 nd PMOS tube at least comprising a 2 nd PMOS gate, a 2 nd PMOS source and a 2 nd PMOS drain, wherein the 1 st PMOS gate serves as a bias end of the P type amplifier, the 2 nd PMOS gate serves as an input end of the P type amplifier, the 1 st PMOS drain is connected with the 2 nd PMOS source to form an output end of the P type amplifier, the 1 st PMOS source is connected to the power supply line, and the 2 nd PMOS drain is connected to the grounding line;

the NMOS type double-tube common-drain amplifier is composed of a 1 st NMOS tube at least comprising a 1 st NMOS grid electrode, a 1 st NMOS drain electrode and a 1 st NMOS source electrode and a 2 nd NMOS tube at least comprising a 2 nd NMOS grid electrode, a 2 nd NMOS drain electrode and a 2 nd NMOS source electrode, wherein the 2 nd NMOS grid electrode is used as the bias end of the N type amplifier, the 1 st NMOS grid electrode is used as the input end of the N type amplifier, the 2 nd NMOS drain electrode is connected with the 1 st NMOS source electrode to form the output end of the N type amplifier, the 1 st NMOS drain electrode is connected to the power supply line, and the 2 nd NMOS source electrode is connected to the grounding line.

7. The two-way symmetric ramp type analog pixel driving circuit according to claim 4, wherein: the PMOS type switch capacitor is composed of a 6 th PMOS tube at least comprising a 6 th-PMOS grid electrode, a 6 th-PMOS drain electrode and a 6 th-PMOS source electrode and a MIM capacitor at least comprising a MIM capacitor upper polar plate and a MIM capacitor lower polar plate, the 6 th-PMOS grid electrode is used as the P type switch capacitor control end, the 6 th-PMOS source electrode is used as the P type switch capacitor input end, the 6 th-PMOS drain electrode is connected with the MIM capacitor upper polar plate to form the P type switch capacitor output end, and the MIM capacitor lower polar plate is connected to the grounding wire;

the NMOS type switch capacitor is composed of a 6-NMOS tube at least comprising a 6-NMOS grid electrode, a 6-NMOS drain electrode and a 6-NMOS source electrode and a MIM capacitor at least comprising a MIM capacitor upper polar plate and a MIM capacitor lower polar plate, the 6-NMOS grid electrode serves as the N type switch capacitor control end, the 6-NMOS drain electrode serves as the N type switch capacitor input end, the 6-NMOS source electrode is connected with the MIM capacitor upper polar plate to form the N type switch capacitor output end, and the MIM capacitor lower polar plate is connected to the grounding wire.

8. A driving method of a two-way symmetrical ramp type analog pixel driving circuit according to any one of claims 1 to 7, characterized by: any one display period is formed by a positive field display period and a negative field display period which are adjacent to each other, the positive field display period and the negative field display period are respectively formed by an addressing line period which can enable the pixel positive addressing storage circuit and the pixel negative addressing storage circuit to have an input on-state and at least one display line period which always enables the pixel positive addressing storage circuit and the pixel negative addressing storage circuit to keep an input off-state, the addressing line period is the same as, time-connected with and commonly called as a line period, the positive ramp signal amplifier and the negative ramp signal amplifier are configured to be in an active working state by a bias level transmitted on the ramp bias voltage supply line in each line period, the negative analog display transmission gate is in an off-state and the negative analog display amplifier is in an inactive working state in all display line periods of the positive field display period and the addressing line period of the negative field display period, and the positive analog display transmission gate is in an off-state and the positive analog display amplifier is in an inactive working state in all display line periods of the negative field display period and the positive field display period and the addressing line period of the positive field display period,

each row period is divided into four time periods T1, T2, T3 and T4, two kinds of positive slope signals and two kinds of negative slope signals which are respectively constructed by connecting four wave forms are configured, the highest levels of the positive slope signals and the negative slope signals are the same as the highest level of the slope, the center levels of the positive slope signals and the negative slope signals are the same as the center level of the slope, the lowest levels of the negative slope signals are the same as the lowest level of the slope, in addition, in each row period, the positive slope signals jump from the highest level of the slope to the center level of the slope in the T1 time period, the negative slope signals jump from the lowest level of the slope to the center level of the slope in the T2 time period, the positive slope signals and the negative slope signals are fixed as the center level of the slope in the T3 time period, the positive slope signals jump from the center level of the slope to the lowest level of the slope and the negative slope signals jump from the center level of the slope to the highest level of the slope in the T4 time period, and the negative slope signals gradually decrease from the highest level of the slope to the lowest slope.

9. The driving method of a two-way symmetric ramp type analog pixel driving circuit according to claim 8, wherein: the four time periods T1, T2, T3 and T4 in each row period are performed sequentially and then circulate, so that each display period can output a pair of analog levels corresponding to the numbers stored by the digital signal latch in the row addressing period of the current display period at the pixel analog signal output electrode.

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