CN114731141A - 高频放大器 - Google Patents
高频放大器 Download PDFInfo
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Abstract
放大元件(T1)放大输入信号。高次谐波匹配电路(3)经由第一线缆(W1)与放大元件(T1)的输出端连接。高次谐波匹配电路(3)具有:与第一线缆(W1)连接的第一电感器(L1)、与第一电感器(L1)串联地连接的第一电容器(C1)、与第一电感器(L1)并联地连接的第二电感器(L2)、以及与第二电感器(L2)串联地连接的第二电容器(C2)。第一电感器(L1)与第二电感器(L2)形成呈减极性的互感的减极性耦合器。
Description
技术领域
本发明涉及高频放大器。
背景技术
动作时的低耗电化、即高效率化是半导体放大器中的基本的课题。在以超过微波的高频放大电力的高频放大器中,从电路方面针对该课题的研讨之一,存在所谓的高次谐波处理。在此,半导体放大的信号的频率为基波,基波的倍数的频率为高次谐波。高次谐波处理是在高次谐波中通过从半导体放大器往回看的外围电路的阻抗的控制,来实现高效率动作的手法。
作为实现高频放大器的高效率的电路,例如有F级放大器。在F级放大器中,在将从FET的漏极端子观察到的对偶数次的高次谐波的负荷设为短路,并将对奇数次的高次谐波的负荷设为开路的F级负荷条件下,使漏极电压的时间波形接近矩形波,使漏极电压的时间波形与电流的时间波形的重叠部分的面积减少。由此,由FET消耗的电力减少,因此能得到极高的漏极效率。
但是实际上存在由FET以及线缆等组件引起的寄生电容以及电感,这些影响漏极端子处的电压、电流的时间波形。因此,F级负荷电路在考虑到这些寄生成分的基础上,需要设计成相对于偶数次高次谐波成为短路,并且相对于奇数次高次谐波成为开路(例如,参照专利文献1)。
专利文献1:日本专利第5958834号公报
然而在以往的高频放大器中,存在难以同时实现基波、二倍波、三倍波下的阻抗匹配的问题。
发明内容
本发明是为了解决上述那样的课题所做出的,其目的在于得到能够同时实现基波、二倍波、三倍波下的阻抗匹配的高频放大器。
本发明的高频放大器的特征在于,具备:放大元件,其放大输入信号;和高次谐波匹配电路,其经由第一线缆而与所述放大元件的输出端连接,所述高次谐波匹配电路具有:与所述第一线缆连接的第一电感器、与所述第一电感器串联地连接的第一电容器、与所述第一电感器并联地连接的第二电感器、以及与所述第二电感器串联地连接的第二电容器,所述第一电感器与所述第二电感器形成呈减极性的互感的减极性耦合器。
在本发明中,通过第一电感器和第二电感器生成减极性的互感,因此能够降低第一线缆的寄生电感的影响。特别是能够实现三倍波匹配所需要的低电感。另外,通过由第一电感器和第一电容器形成的电路来降低高次谐波匹配电路的影响,因此不会对基波的匹配带来影响。因此,能够同时使基波、二倍波、三倍波下的阻抗最佳化。
附图说明
图1是表示实施方式1的高频放大器的电路图。
图2是表示实施方式1的高频放大器的俯视图。
图3是表示实施方式1的高频放大器的立体图。
图4是表示第一电感器和第二电感器的立体图。
图5是用于说明实施方式1的高频放大器的电路动作的等效电路图。
图6是用于说明实施方式1的高频放大器的电路动作的等效电路图。
图7是表示在第一电感器和第二电感器中流动的电流之比n的频率依赖性的图。
图8是表示比较例的高频放大器的电路图。
图9是表示在实施方式1中从晶体管的输出端往回看的输出阻抗的轨迹的图。
图10是表示在比较例中从晶体管的输出端往回看的输出阻抗的轨迹的图。
图11是表示在比较例中从晶体管的输出端往回看的输出阻抗的轨迹的图。
图12是表示实施方式2的高频放大器的电路图。
图13是表示实施方式2的高频放大器的俯视图。
图14是表示实施方式3的高频放大器的电路图。
图15是表示在实施方式4中从晶体管的输出端往回看的输出阻抗的图。
图16是表示实施方式5的高频放大器的电路图。
图17是表示在实施方式5中从晶体管的输出端往回看的输出阻抗的轨迹的图。
具体实施方式
参照附图,对实施方式的高频放大器进行说明。对相同或对应的构成要素标注相同的附图标记,有时省略重复说明。
实施方式1.
图1是表示实施方式1的高频放大器的电路图。图2是表示实施方式1的高频放大器的俯视图。高频放大器的电路模块使用多层玻璃环氧基板1构成。
在玻璃环氧基板1的最上层的金属2通过导电型粘接剂固定有晶体管T1和输入匹配电路MC1。输入匹配电路MC1与晶体管T1的栅极连接。晶体管T1是对从输入端子P1经由输入匹配电路MC1输入的输入信号进行放大的放大元件,例如是GaN系HEMT芯片。最上层的金属2通过贯通孔连接于玻璃环氧基板1的背面的接地层。在晶体管T1的输出端亦即漏极焊盘,经由线缆W1连接有高次谐波匹配电路3。线缆W1具有寄生电感L3。
高次谐波匹配电路3具有与线缆W1连接的第一电感器L1、与第一电感器L1串联地连接的第一电容器C1、与第一电感器L1并联地连接的第二电感器L2、以及与第二电感器L2串联地连接的第二电容器C2。第一电容器C1以及第二电容器C2为片式电容器。
用于匹配相对于输入信号的基波的阻抗的基波匹配电路MC2的一端连接于线缆W1与高次谐波匹配电路3的连接点。基波匹配电路MC2的另一端连接于高频放大器的输出端子P2。
图3是表示实施方式1的高频放大器的立体图。图4是表示第一电感器和第二电感器的立体图。第一电感器L1由从玻璃环氧基板1的表面起第一层的布线层和第三层的布线层形成。第二电感器L2由玻璃环氧基板1的第二层的布线层形成。在从玻璃环氧基板1的上方观察的俯视图中,第一电感器L1从晶体管T1的漏极朝向第一电容器C1顺时针卷绕。在俯视观察时,第二电感器L2从晶体管T1的漏极朝向第二电容器C2逆时针卷绕。第一电感器L1与第二电感器L2相互向相反方向卷绕并重叠,因此形成呈减极性的互感的减极性耦合器。
在不考虑互感的情况下,由于线缆W1的寄生电感L3的影响,由第二电感器L2和第二电容器C2构成的二倍波谐振电路的谐振频率设定为相对于基波的频率fo高于2fo。因此,二倍波谐振电路的阻抗相对于二倍波以下的频率表示电容性,相对于三倍波表示感应性。由于相对于基波降低基于二倍波谐振电路的电容,因此由第一电感器L1和第一电容器C1构成的谐振电路的阻抗设定为相对于基波表示感应性。
接下来,对考虑了互感的情况下的电路动作进行说明。图5以及图6是用于说明实施方式1的高频放大器的电路动作的等效电路图。为了简化说明,基波匹配电路MC2作为开路处理。将晶体管T1的内部负荷设为Rds,将晶体管T1的寄生电容设为Cds。将在第一电感器L1中流动的电流设为i1,将在第二电感器L2中流动的电流设为i2。将第一电感器L1的电感设为L(L1),将第二电感器L2的电感设为L(L2),将互感设为-M。
为了使高频放大器进行理想的F级动作,优选为从晶体管T1的输出端往回看高次谐波匹配电路3的阻抗相对于基波成为开路,相对于二倍波成为短路,相对于三倍波与晶体管T1的寄生电容Cds谐振而成为开路。
在图5中,将图1的第一电感器L1和第二电感器L2置换成没有耦合的电感器。电感器L4与由第一电感器L1和第二电感器L2生成的减极性的互感器对应。基波电感器L1a的电感成为L(L1)+M,高次谐波电感器L2a的电感成为L(L2)+M,电感器L4的电感成为-M。调整各常数,使由L1a、L2a、C1、C2形成的电路在基波下成为开路。由此,能够使该电路不对基波下的从晶体管T1的输出端往回看的输出阻抗带来影响。
在图5的电感器L4中流动有电流i1和电流i2的双方。在图6中,将图5的电感器L4假想地分割成仅电流i1流动的电感器L4a、和仅电流i2流动的电感器L4b。
将电感器L4a的电感设为L(M1a),将电感器L4b的电感设为L(M1b)。图5的节点N1与图6的节点N11以及N12为同一电位,因此L(M1a)、L(M1b)能够表示如下。
L(M1a)=-(i1+i2)/i1×M
L(M1b)=-(i1+i2)/i2×M
在此,设为n=i1/i2。N表示在第一电感器L1和第二电感器L2中流动的电流之比。上述的L(M1a)、L(M1b)能够用n表示如下。
L(M1a)=-(1+1/n)×M
L(M1b)=-(1+n)×M
将电感器L1a与电感器L4a的串联连接设为电感器L1b。作为基波电感的电感器L1b的电感L(L1b)能够表示如下。
L(L1b)=L(L1a)+L(M1a)=L(L1)-(1/n)×M
将电感器L2a和电感器L4b的串联连接设为电感器L2b。作为二倍波电感的电感器L2b的电感L(L2b)能够表示如下。
L(L2b)=L(L2a)+L(M1b)=L(L2)-n×M
图7是表示在第一电感器和第二电感器中流动的电流之比n的频率依赖性的图。在电流i1和电流i2流动的路径中仅连接有LC电路,因此n的值为实数。虽然主要对高次谐波的阻抗产生影响的是L4b、L2a、C2,但由于n的值随着频率而增加,因此可知等效的电感L(L2b)能够随着频率而减少。
在高次谐波匹配,特别是三倍波匹配中,在基波的3倍高的频率中,需要使与晶体管T1的寄生电容Cds谐振的电感的值减小。但是在没有耦合的以往电路中难以实现。与此相对,在本实施方式中,由于通过第一电感器L1和第二电感器L2生成减极性的互感,因此能够降低线缆W1的寄生电感L3的影响。特别是能够实现三倍波匹配所需的低电感。另外,由于通过由第一电感器L1和第一电容器C1形成的电路来降低高次谐波匹配电路3的影响,因而不会对基波的匹配带来影响。因此,能够同时使基波、二倍波、三倍波下的阻抗最佳化。
接着,将本实施方式的效果与比较例进行比较来说明。图8是表示比较例的高频放大器的电路图。高次谐波匹配电路3具有:由电感器L4以及电容器C3构成的二倍波用的谐振电路、和由电感器L5以及电容器C4构成的三倍波用的谐振电路。在比较例中,电感器L4和电感器L5不形成减极性耦合器。
图9是表示在实施方式1中从晶体管的输出端往回看的输出阻抗的轨迹的图。图10以及图11是表示在比较例中从晶体管的输出端往回看的输出阻抗的轨迹的图。图中fl、fc、fh分别表示基波的频带下限、频带中心、频带上限处的阻抗。2fl、2fc、2fh分别表示二倍波的频带下限、频带中心、频带上限处的阻抗。3fl、3fc、3fh分别表示三倍波的频带下限、频带中心、频带上限处的阻抗。fc_o表示不包含高次谐波匹配电路3的情况下的基波中的频带中心处的阻抗。晶体管T1的输出阻抗是从晶体管T1的漏极端、内部电流源Is或内部负荷Rds往回看高次谐波匹配电路3的阻抗。
由图9~11可知,相对于在实施方式1中对基波、二倍波、三倍波的各个频率取得匹配,在比较例中未取得二倍波的匹配。另外,实施方式1的三倍波频率特性优于比较例。
由图10可知,在比较例中,通过使L4、C3、L5、C4最佳化,由此满足作为F级动作的必要条件的二倍波下短路,三倍波下开路的条件。但是基波下的阻抗从fc_o偏移到fc。
在放大器中,将在一定的反射系数以下取得匹配的频率范围的宽度程度称为宽频带性。通常,公知有放大器的宽频带性与晶体管T1的Rds·Cds成反比。在比较例中,如图10所示,fc从不包含高次谐波电路的情况下的阻抗fc_o偏移。若将晶体管T1的等效的寄生电容设为Cds′,则成为Cds<Cds′,使宽频带性劣化。另外,若Cds′变大,则需要附加补偿电容的增加量的电路,因而存在输出匹配电路的损失增加等问题。
在图11中,将相对于基波和三倍波的阻抗固定。由该图可知,若将相对于基波的阻抗固定为fc_o,将相对于三倍波的阻抗3fl、3fc、3fh固定为开路,则相对于二倍波的阻抗2fl、2fc、2fh存在从短路端偏移的问题。因此,在比较例中同时实现基波、二倍波、三倍波处的阻抗匹配是困难的。
与此相对,在本实施方式中,即使是由将高频放大器中的主要的寄生成分亦即晶体管T1的漏极焊盘与高次谐波匹配电路3连接的线缆W1引起的寄生电感存在的情况下,也能够同时实现基波、二倍波、三倍波下的阻抗匹配。
实施方式2.
图12是表示实施方式2的高频放大器的电路图。图13是表示实施方式2的高频放大器的俯视图。高次谐波匹配电路3经由线缆W1连接于晶体管T1的漏极。另一方面,基波匹配电路MC2经由另外的设置的线缆W2连接于晶体管T1的漏极。线缆W2具有寄生电感器L5。基波的基波匹配电路MC2和高次谐波匹配电路3在晶体管T1的漏极被分离。线缆W2相对于线缆W1倾斜地配置。因此,能够降低线缆间的耦合,基波匹配电路MC2与高次谐波匹配电路3的干扰较少。因此,能够使基波匹配电路MC2和高次谐波匹配电路3分别最佳化,使电路设计变得容易。
实施方式3.
图14是表示实施方式3的高频放大器的电路图。实施方式1的第二电容器C2与基波频率的3倍高的频率对应。例如,若是3GHz频带的放大器,则第二电容器C2与9GHz对应。因此,第二电容器C2的电容值为1pF以下,并且要求精度。在实施方式1中,使用片式电容器作为第二电容器C2。但是市面上出售的片式电容器的电容值的步长粗糙,是以0.1pF为单位的。另外,用于安装片式电容器的焊盘大,且具有数分之一的1pF程度的寄生电容。因此,第二电容器C2的电容值的微调是困难的。
因此,在本实施方式中,将实施方式1的第二电容器C2置换为开路短截线STB1。因此能够进行电容值的微调。另外,由于不需要用于安装电容器的焊盘,因此能够缩小电路规模。另外,也可以代替开路短截线STB1而使用由玻璃环氧基板1和布线形成的层间电容。
实施方式4.
在本实施方式中,在实施方式1的电路结构中,将第一电感器L1、第一电容器C1、第二电感器L2以及第二电容器C2的常数设定为:从晶体管T1的输出端往回看高次谐波匹配电路3的阻抗相对于二倍波与晶体管T1内的寄生电容Cds谐振而成为开路,相对于三倍波成为短路。由此,能够满足高频放大器进行逆F级动作的高次谐波条件。
图15是表示在实施方式4中从晶体管的输出端往回看的输出阻抗的图。通过调整各常数,虽然对基波产生较大影响,但可知能够实现作为逆F级放大器的阻抗条件的、相对于二倍波的频率成为开路,相对于三倍波成为短路的状态。另外,相对于三倍波,利用减极性的互感在宽频带中满足短路条件。
实施方式5.
图16是表示实施方式5的高频放大器的电路图。在实施方式4的结构的基础上,在第一电感器L1与第一电容器C1之间连接有相对于基波的波长λ而言,电长度为λ/4的传输线TRL1。
在实施方式4中,从晶体管T1的电流源往回看的相对于基波的阻抗受到两个LC谐振电路影响较大。与此相对,通过插入传输线TRL1,能够减小对基波的影响,使电路设计变得容易。
图17是表示在实施方式5中从晶体管的输出端往回看的输出阻抗的轨迹的图。可知通过传输线TRL1的插入来减小对基波的影响。
附图标记说明
1...玻璃环氧基板;3...高次谐波匹配电路;C1...第一电容器;C2...第二电容器;L1...第一电感器;L2...第二电感器;MC2...基波匹配电路;STB1...开路短截线;T1...晶体管(放大元件);TRL1...传输线;W1...第一线缆;W2...第二线缆。
Claims (13)
1.一种高频放大器,其特征在于,具备:
放大元件,其放大输入信号;和
高次谐波匹配电路,其经由第一线缆而与所述放大元件的输出端连接,
所述高次谐波匹配电路具有:与所述第一线缆连接的第一电感器、与所述第一电感器串联地连接的第一电容器、与所述第一电感器并联地连接的第二电感器、以及与所述第二电感器串联地连接的第二电容器,
所述第一电感器与所述第二电感器形成呈减极性的互感的减极性耦合器。
2.根据权利要求1所述的高频放大器,其特征在于,
所述第一电感器与所述第二电感器相互向相反方向卷绕并重叠。
3.根据权利要求1或2所述的高频放大器,其特征在于,
从所述放大元件的所述输出端往回看所述高次谐波匹配电路的阻抗,相对于所述输入信号的基波成为开路,相对于二倍波成为短路,相对于三倍波成为开路,所述高频放大器进行F级动作。
4.根据权利要求3所述的高频放大器,其特征在于,
由所述第二电感器和所述第二电容器构成的谐振电路的阻抗,相对于所述二倍波以下的频率表示电容性,相对于所述三倍波表示感应性,
由所述第一电感器和所述第一电容器构成的谐振电路的阻抗,相对于所述基波表示感应性。
5.根据权利要求1或2所述的高频放大器,其特征在于,
从所述放大元件的所述输出端往回看所述高次谐波匹配电路的阻抗,相对于所述输入信号的二倍波成为开路,相对于三倍波成为短路,所述高频放大器进行逆F级动作。
6.根据权利要求5所述的高频放大器,其特征在于,
还具备传输线,该传输线连接于所述第一电感器与所述第一电容器之间,电长度相对于所述输入信号的波长λ为4/λ。
7.根据权利要求1~6中的任一项所述的高频放大器,其特征在于,
还具备基波匹配电路,该基波匹配电路连接于所述第一线缆与所述高次谐波匹配电路的连接点。
8.根据权利要求1~6中的任一项所述的高频放大器,其特征在于,
还具备基波匹配电路,该基波匹配电路通过第二线缆连接于所述放大元件的所述输出端。
9.根据权利要求8所述的高频放大器,其特征在于,
所述第二线缆相对于所述第一线缆倾斜地配置。
10.根据权利要求1~9中的任一项所述的高频放大器,其特征在于,
所述第一电容器以及所述第二电容器为片式电容器。
11.根据权利要求1~9中的任一项所述的高频放大器,其特征在于,
所述第二电容器是由多层玻璃环氧基板和布线形成的层间电容。
12.根据权利要求1~9中的任一项所述的高频放大器,其特征在于,
所述第二电容器是开路短截线。
13.根据权利要求1~12中的任一项所述的高频放大器,其特征在于,
所述放大元件为GaN系HEMT芯片,
所述第一电感器以及所述第二电感器由玻璃环氧基板的布线层形成。
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