CN114725211A - 高电子迁移率晶体管及其制作方法 - Google Patents
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Abstract
本发明公开一种高电子迁移率晶体管及其制作方法，其中该制作高电子迁移率晶体管的方法为，首先形成一缓冲层于基底上，然后进行一现场掺杂制作工艺以形成第一含氟层于缓冲层上，形成一阻障层于第一含氟层上，形成第二含氟层于阻障层上，形成一栅极电极于第二含氟层上，再形成一源极电极以及一漏极电极于该栅极电极两侧。
Description
技术领域
本发明涉及一种高电子迁移率晶体管及其制作方法。
背景技术
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点，例如宽能隙、高击穿电压、高电子迁移率、大弹性模数(elastic modulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通讯元件等应用的元件的制作。
发明内容
本发明一实施例揭露一种制作高电子迁移率晶体管的方法。首先形成一缓冲层于基底上，然后进行一现场掺杂制作工艺以形成第一含氟层于缓冲层上，形成一阻障层于第一含氟层上，形成第二含氟层于阻障层上，形成一栅极电极于第二含氟层上，再形成一源极电极以及一漏极电极于该栅极电极两侧。
本发明另一实施例揭露一种高电子迁移率晶体管，其主要包含一缓冲层设于基底上，第一含氟层设于缓冲层上，一阻障层设于第一含氟层上，一栅极电极设于阻障层上以及源极电极与漏极电极设于栅极电极两侧。
附图说明
图1为本发明一实施例的一高电子迁移率晶体管的结构示意图；
图2为本发明一实施例的一高电子迁移率晶体管的结构示意图。
主要元件符号说明
12:基底
14:核晶层
16:缓冲层
18:非刻意掺杂缓冲层
20:阻障层
22:栅极结构
24:栅极介电层
26:栅极电极
28:源极电极
30:漏极电极
32:含氟层
34:含氟层
具体实施方式
请参照图1，图1为本发明一实施例的一高电子迁移率晶体管的结构示意图。如图1所示，首先提供一基底12，例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底，其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。
然后于基底12表面形成一选择性核晶层(nucleation layer)14以及一缓冲层16。在一实施利中，核晶层14较佳包含氮化铝而缓冲层16包含III-V族半导体例如氮化镓或更具体而言掺杂碳原子的氮化镓，其厚度可介于0.5微米至10微米之间。在一实施利中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metalorganic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapordeposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层16。
需注意的是，本实施例较佳于形成缓冲层16的时候进行一现场掺杂(in-situdoping)制作工艺以形成一含氟层32于缓冲层16表面，其中含氟层32中的氟浓度较佳约1.0×1015离子/平方厘米而含氟层32的厚度则较佳约略等于或小于缓冲层16整体厚度的三分之一。另外本实施例中的缓冲层16可选择由梯度缓冲层所构成或可由超晶格缓冲层所构成。其中缓冲层16若由梯度缓冲层所构成则缓冲层16较佳包含多个梯度氮化铝镓(AlGaN)层，而若缓冲层16由超晶格缓冲层所构成则缓冲层16则较佳包含多个掺杂碳的氮化镓层。
接着于缓冲层16或前述所形成的含氟层32表面形成一非刻意掺杂(unintentionally doped)缓冲层18。在本实施例中，非刻意掺杂缓冲层18较佳包含III-V族半导体，例如氮化镓或更具体而言非刻意掺杂氮化镓。在一实施例中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层16上形成非刻意掺杂缓冲层18。
随后形成一阻障层20于非刻意掺杂缓冲层18表面。在本实施例中阻障层20较佳包含III-V族半导体例如N型氮化铝镓(AlxGa1-xN)，其中0<x<1，阻障层20较佳包含一由外延成长制作工艺所形成的外延层，且阻障层20可包含硅或锗的掺质。如同上述形成缓冲层16与非刻意掺杂缓冲层18的方式，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydridevapor phase epitaxy,HVPE)制作工艺或上述组合于非刻意掺杂缓冲层18上形成阻障层20。
然后依序形成一栅极介电层以及一栅极材料层于阻障层20表面，再利用光刻暨蚀刻制作工艺去除部分栅极材料层及部分栅极介电层以形成一栅极结构22于阻障层20表面，其中栅极结构22较佳包含一图案化的栅极介电层24与栅极电极26。在本实施中，栅极电极26的下半部可包含P型氮化镓等半导体材料而栅极电极26的上半部则较佳包含金属，例如可包含金、银或铂等萧特基(Schottky)金属。栅极介电层24则可包含氧化硅、氮化铝或氧化铝等材料。
随后形成一源极电极28以及一漏极电极30于栅极电极26两侧。在本实施例中，源极电极28与漏极电极30较佳由金属所构成，但有别于栅极电极26的上半部由萧特基金属所构成，源极电极28与漏极电极30较佳由欧姆接触金属所构成。依据本发明一实施例，源极电极28与漏极电极30可各自包含钛、铝、钨、钯或其组合。在一些实施例中，可先以光刻暨蚀刻制作工艺去除部分栅极电极26两侧的阻障层20形成凹槽，再以电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapordeposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于凹槽内形成电极材料，然后再以蚀刻将电极材料图案化以形成源极电极28与漏极电极30。
请再参照图2，图2揭露本发明一实施例的一高电子迁移率晶体管的结构示意图。如图2所示，相较于前述实施例于阻障层20形成后便直接进行栅极结构22的制作，本发明又可选择在形成阻障层20的时候进行一另一道现场掺杂(in-situ doping)制作工艺以形成另一含氟层34于阻障层20表面，其中含氟层34中的氟浓度可等于或不同于前述含氟层32中的氟浓度例如但不局限于较佳约1.0×1015离子/平方厘米，且含氟层34的厚度较佳约阻障层20整体厚度的三分之一。
之后可利用光刻暨蚀刻制作工艺先去除部分含氟层34再进行后续栅极结构22的制作，或可直接形成前述栅极介电层与栅极材料层于含氟层34表面，再利用光刻暨蚀刻制作工艺去除部分栅极材料层、部分栅极介电层及部分含氟层34以形成栅极结构22于图案化的含氟层34表面，这些做法均属本发明所涵盖的范围。以结构来看，含氟层34顶部可选择切齐或略高于两侧的阻障层20顶部，含氟层34宽度可等于或大于上方栅极结构22的宽度，且含氟层34左右侧壁可选择切齐或不切齐栅极结构22的左右侧壁。另外由于含氟层34较佳利用光刻暨蚀刻制作工艺被图案化因此其宽度较佳小于设于缓冲层16表面的含氟层32宽度。
一般而言，由于缓冲层与阻障层的材料能带间隙(band gap)不同之故，缓冲层与阻障层的界面数较佳形成异质接面(heterojunction)。异质接面处的能带弯曲，导带(conduction band)弯曲深处形成量子阱(quantum well)，将压电效应(piezoelectricity)所产生的电子约束于量子阱中，因此在缓冲层与阻障层的界面处形成通道区58或二维电子气(two-dimensional electron gas,2DEG)，进而形成导通电流。
现行制备高电子迁移率晶体管时将晶体管由正常开启(Normally on)操作模式转换为正常关闭(Normally off)操作方式的手段之一是先形成一硬掩模于阻障层上，图案化硬掩模以形成一开口暴露出阻障层表面，再以离子注入制作工艺将氟离子直接注入阻障层内，其中所注入的氟离子较佳吸引一个自由电子并成为负固定电荷(negative fixedcharge)调变其局部电位(local portion)进而耗尽2DEG。考虑现行注入氟离子的方式在深浅度的控制上不容易控制进而影响元件阻值，本发明较佳采用现场掺质(in-situ doping)的方式将氟离子注入前述缓冲层16以及/或阻障层20的表面，由此提升所形成含氟层的均匀度并降低元件的闪烁噪声(flicker noise)。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。
Claims (20)
1.一种制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的方法，其特征在于，包含：
形成缓冲层于基底上；
形成第一含氟层于该缓冲层上；
形成阻障层于该第一含氟层上；
形成栅极电极于该阻障层上；以及
形成源极电极以及漏极电极于该栅极电极两侧。
2.如权利要求1所述的方法，另包含进行现场掺杂制作工艺以形成该第一含氟层。
3.如权利要求1所述的方法，另包含：
形成非刻意掺杂缓冲层于该缓冲层上；以及
形成该阻障层于该非刻意掺杂缓冲层上。
4.如权利要求1所述的方法，其中该缓冲层包含III-V族半导体。
5.如权利要求1所述的方法，其中该缓冲层包含梯度缓冲层。
6.如权利要求5所述的方法，其中该缓冲层包含多个梯度氮化铝镓(AlGaN)层。
7.如权利要求1所述的方法，其中该缓冲层包含超晶格缓冲层。
8.如权利要求7所述的方法，其中该缓冲层包含多个掺杂碳的氮化镓层。
9.如权利要求1所述的方法，另包含：
形成第二含氟层于该阻障层上；
图案化该第二含氟层；以及
形成该栅极电极于该第二含氟层上。
10.如权利要求1所述的方法，其中该阻障层包含氮化铝镓(AlxGa1-xN)。
11.一种高电子迁移率晶体管(high electron mobility transistor,HEMT)，其特征在于，包含：
缓冲层，设于基底上；
第一含氟层，设于该缓冲层上；
阻障层，设于该第一含氟层上；
栅极电极，设于该阻障层上；以及
源极电极以及漏极电极，设于该栅极电极两侧。
12.如权利要求11所述的高电子迁移率晶体管，另包含：
非刻意掺杂缓冲层，设于该缓冲层上；以及
该阻障层设于该非刻意掺杂缓冲层上。
13.如权利要求11所述的高电子迁移率晶体管，其中该缓冲层包含III-V族半导体。
14.如权利要求11所述的高电子迁移率晶体管，其中该缓冲层包含梯度缓冲层。
15.如权利要求14所述的高电子迁移率晶体管，其中该缓冲层包含多个梯度氮化铝镓(AlGaN)层。
16.如权利要求11所述的高电子迁移率晶体管，其中该缓冲层包含超晶格缓冲层。
17.如权利要求16所述的高电子迁移率晶体管，其中该缓冲层包含多个掺杂碳的氮化镓层。
18.如权利要求11所述的高电子迁移率晶体管，另包含第二含氟层，设于该阻障层以及该栅极电极之间。
19.如权利要求18所述的高电子迁移率晶体管，其中该第一含氟层宽度大于该第二含氟层宽度。
20.如权利要求11所述的高电子迁移率晶体管，其中该阻障层包含氮化铝镓(AlxGa1- xN)。
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