CN114725195A - AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device - Google Patents

AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device Download PDF

Info

Publication number
CN114725195A
CN114725195A CN202210158150.XA CN202210158150A CN114725195A CN 114725195 A CN114725195 A CN 114725195A CN 202210158150 A CN202210158150 A CN 202210158150A CN 114725195 A CN114725195 A CN 114725195A
Authority
CN
China
Prior art keywords
layer
aln
substrate
heterojunction
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210158150.XA
Other languages
Chinese (zh)
Inventor
张涛
苏华科
许晟瑞
段小玲
张进成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN202210158150.XA priority Critical patent/CN114725195A/en
Publication of CN114725195A publication Critical patent/CN114725195A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a two-dimensional hole gas heterojunction based on an AlN insert layer, a preparation method thereof and a PMOS device, wherein the heterojunction sequentially comprises the following components from bottom to top: the buffer layer, the back barrier layer, the insertion layer and the p-type GaN layer are sequentially arranged on the substrate layer, the nucleation layer, the buffer layer, the back barrier layer, the insertion layer and the p-type GaN layer, wherein the insertion layer is made of AlN. According to the invention, a thin AlN insertion layer is inserted in the heterojunction preparation process, and the higher forbidden bandwidth of the AlN material is utilized to promote the polarization effect at the heterojunction interface, so that the valence band at the interface is bent to be close to or even above the Fermi level, and then high-concentration two-dimensional hole gas is generated, thereby being beneficial to realizing the preparation of high-performance GaN PMOS.

Description

AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a two-dimensional hole gas heterojunction based on an AlN (aluminum nitride) insertion layer, a preparation method thereof and a PMOS (P-channel metal oxide semiconductor) device.
Background
With the development of microelectronics, the third generation semiconductor materials typified by GaN are beginning to stand out. Among them, GaN material has the advantages of wide bandgap, high stability and direct band gap, and is an important semiconductor material for manufacturing microwave power devices, power electronic devices and light emitting diodes.
In recent years, High Electron Mobility Transistors (HEMTs) and PMOS devices based on GaN materials have been rapidly developed, attracting a lot of research hotspots. The two devices operate by two-dimensional electron gas or two-dimensional hole gas generated by GaN polarization effect. However, due to the higher background carrier concentration and the lower p-type doping efficiency in GaN, the two-dimensional hole gas concentration based on AlGaN and p-type GaN heterojunction is lower, so that the performance of the manufactured PMOS device is far inferior to that of the HEMT device, and the mismatch of performance further causes difficulty in implementing the GaN-based complementary logic circuit. It is therefore essential to improve the heterojunction preparation of the two-dimensional hole gas.
In the past, researchers have used a series of methods to increase the concentration of two-dimensional hole gas, such as increasing the AlGaN/p-GaN doping concentration or using AlGaN barriers of higher Al composition. However, increasing the p-type doping concentration does not bring much gain, but causes the degradation of device performance due to the phenomena of the reduction of ionization rate and the great reduction of mobility rate caused by heavy doping; and the AlGaN with high Al component has poor growth quality and degraded surface appearance, thereby greatly reducing the surface mobility of the two-dimensional hole gas.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a two-dimensional hole gas heterojunction based on an AlN insert layer, a preparation method thereof and a PMOS device. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a two-dimensional hole gas heterojunction based on an AlN insertion layer, which sequentially includes, from bottom to top: the buffer layer, the back barrier layer, the insertion layer and the p-type GaN layer are sequentially arranged on the substrate layer, the nucleation layer, the buffer layer, the back barrier layer, the insertion layer and the p-type GaN layer, wherein the insertion layer is made of AlN.
In one embodiment of the invention, the thickness of the insertion layer is 1-3 nm.
In one embodiment of the invention, the substrate layer is a sapphire substrate, a silicon substrate, a gallium nitride substrate or a silicon carbide substrate.
In one embodiment of the invention, the material of the nucleation layer is GaN or AlN, and the thickness is 10-100 nm;
the buffer layer is made of GaN and has the thickness of 2-4 mu m;
the back barrier layer is made of AlGaN and has the thickness of 10-30 nm;
the thickness of the p-type GaN layer is 50-100 nm.
In a second aspect, the present invention provides a PMOS device having an AlN insertion layer, which is characterized by including the two-dimensional hole-gas heterojunction structure based on the AlN insertion layer described in the above embodiments.
In a third aspect, the present invention provides a method for preparing a two-dimensional hole gas heterojunction based on an AlN insertion layer, comprising:
selecting a substrate and preprocessing the substrate;
depositing a nucleating layer on the pretreated substrate;
depositing a buffer layer on the nucleation layer;
depositing a back barrier layer on the buffer layer;
forming an AlN insert layer on the back barrier layer;
forming a p-type GaN layer on the AlN insert layer to complete the preparation of the heterojunction.
In one embodiment of the present invention, a substrate is selected and pre-treated, comprising:
sequentially putting the substrate into hydrofluoric acid, acetone solution, absolute ethyl alcohol solution and deionized water for ultrasonic cleaning;
and placing the cleaned substrate in an MOCVD reaction chamber, introducing hydrogen and ammonia gas into the reaction chamber, and carrying out heat treatment on the substrate in a high-temperature environment.
In one embodiment of the invention, depositing a buffer layer on the nucleation layer comprises:
and growing GaN with the thickness of 2-4 mu m on the nucleation layer by adopting an MOCVD process to form a buffer layer.
In one embodiment of the invention, depositing a back barrier layer on the buffer layer comprises:
and growing AlGaN with the thickness of 10-30nm on the buffer layer by adopting an MOCVD (metal organic chemical vapor deposition) process to form a back barrier layer.
In one embodiment of the present invention, forming an AlN interposer on the back barrier layer comprises:
growing an AlN insert layer with the thickness of 1-3nm on the back barrier layer by adopting an MOCVD process; wherein the pressure in the reaction chamber is 20-60Torr, the temperature is 900-1100 deg.C, the flow of Al source is 200-600sccm, the flow of ammonia is 200-300sccm, and the flow of hydrogen is 1200 sccm.
The invention has the beneficial effects that:
1. according to the invention, the AlN thin layer with higher forbidden band width is inserted into the interface of the back barrier layer and the p-type GaN heterojunction, so that the polarization effect at the interface of the heterojunction is enhanced, the valence band at the interface of the heterojunction is bent to be close to or even above the Fermi level, the two-dimensional hole gas concentration is greatly improved, and the hole gas is slightly influenced by temperature and scattering due to deepening of a potential well, so that the device has higher temperature stability and carrier mobility;
2. the AlN-inserted-layer-based two-dimensional hole gas heterojunction provided by the invention can be combined with subsequent device process optimization, so that the performance of the GaN-based PMOS device is further improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic structural diagram of a two-dimensional hole gas heterojunction based on an AlN insert layer according to an embodiment of the invention;
FIG. 2 is a schematic illustration of a conventional heterojunction and AlN-inserted heterojunction energy band structure provided by an embodiment of the invention;
FIG. 3 is a flow chart of a method for preparing a two-dimensional hole gas heterojunction based on an AlN insert layer according to an embodiment of the invention;
fig. 4a to 4e are schematic process diagrams of the two-dimensional hole gas heterojunction based on the AlN insertion layer according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a two-dimensional hole-gas heterojunction based on an AlN insertion layer according to an embodiment of the present invention, which sequentially includes, from bottom to top: the semiconductor device comprises a substrate layer 1, a nucleation layer 2, a buffer layer 3, a back barrier layer 4, an insertion layer 5 and a p-type GaN layer 6, wherein the material of the insertion layer 5 is AlN.
In particular, the thickness of the insertion layer 5 is 1-3 nm.
In this embodiment, the substrate layer 1 may be any one of a sapphire substrate, a silicon substrate, a gallium nitride substrate, or a silicon carbide substrate.
Further, the material of the nucleation layer 2 is GaN or AlN, and the thickness is 10-100 nm;
the buffer layer 3 is made of GaN and has the thickness of 2-4 mu m;
the back barrier layer 4 is made of AlGaN and has the thickness of 10-30 nm;
the thickness of the p-type GaN layer 6 is 50-100 nm.
In the embodiment, the AlN thin layer with a higher forbidden band width is inserted into the interface between the back barrier layer and the p-type GaN heterojunction, so that the polarization effect of the interface of the heterojunction is enhanced, the valence band at the interface of the heterojunction is bent to be close to or even above the Fermi level, the two-dimensional hole gas concentration is greatly improved, and the hole gas is slightly influenced by temperature and scattering due to deepening of a potential well, so that the device has higher temperature stability and carrier mobility, and the method is convenient to realize.
Specifically, at the interface of the heterojunction, the potential well formed at the valence band is deeper in depth and narrower in width due to the existence of a larger band step, more holes are accumulated at the potential well according to boltzmann statistical distribution of carriers in the semiconductor, and since the width of the potential well is narrow, the hole gas at the interface can be considered to be "quasi two-dimensional", and thus, a high-concentration and high-mobility two-dimensional hole gas can be obtained.
Referring to fig. 2, fig. 2 is a schematic diagram of a heterojunction band structure of a conventional heterojunction and inserted AlN according to an embodiment of the present invention, where the left side of fig. 2 is the conventional heterojunction structure and the right side is the heterojunction structure with an inserted AlN layer, as is apparent from a comparison between the two structures, the heterojunction with inserted AlN has a deeper potential well at the interface, and the potential well is bent above the fermi level.
Example two
On the basis of the first embodiment, the present embodiment provides a PMOS device having an AlN insertion layer, which includes the two-dimensional hole-gas heterojunction structure based on the AlN insertion layer described in the first embodiment.
Therefore, the PMOS device provided by the embodiment also has higher two-dimensional hole gas concentration, and the device performance can be further improved.
EXAMPLE III
On the basis of the first embodiment, the present embodiment further provides a method for preparing a two-dimensional hole-gas heterojunction based on an AlN insertion layer. Referring to fig. 3, fig. 3 is a flowchart of a method for preparing a two-dimensional hole-gas heterojunction based on an AlN insertion layer according to an embodiment of the present invention, including:
s1: the substrate is selected and pretreated.
Firstly, a substrate made of a certain material is selected for cleaning.
Specifically, the substrate is sequentially placed in hydrofluoric acid, acetone solution, absolute ethyl alcohol solution and deionized water to be ultrasonically cleaned for 5min, and finally, nitrogen is used for blow-drying.
Then, the cleaned substrate is placed in an MOCVD reaction chamber, hydrogen and ammonia gas are introduced into the reaction chamber, and the substrate is subjected to heat treatment in a high-temperature environment.
Specifically, the degree of vacuum of the reaction chamber was reduced to less than 2X 10-2Torr; introducing mixed gas of hydrogen and ammonia gas into the reaction chamber, and allowing the pressure in the MOCVD reaction chamber to reach 20-760TorrThen, the substrate is heated to the temperature of 900-.
S2: and depositing a nucleation layer on the pretreated substrate.
And growing GaN or AlN with the thickness of 10-100nm on the substrate after the heat treatment by adopting an MOCVD process to form a nucleating layer.
The process conditions for growing the GaN nucleating layer are as follows: the pressure of the reaction chamber is 20-60Torr, the temperature is 520-560 ℃, the flow rate of the gallium source is 50-100sccm, the flow rate of the hydrogen is 1200sccm, and the flow rate of the ammonia is 3000-4000 sccm;
the process conditions for growing the AlN nucleating layer are as follows: the pressure in the reaction chamber is 20-60Torr, the temperature is 900 ℃ for 700-plus, the flow of hydrogen is 1200sccm, the flow of ammonia is 300sccm for 200-plus, and the flow of aluminum is 300sccm for 100-plus.
S3: depositing a buffer layer on the nucleation layer.
And growing GaN with the thickness of 2-4 mu m on the nucleation layer by adopting an MOCVD process to form a buffer layer.
The specific process conditions are as follows: the pressure of the reaction chamber is 20-60Torr, the temperature is 1000-1200 ℃, the flow rate of hydrogen is 1200sccm, the flow rate of the gallium source is 150-180sccm, and the flow rate of ammonia is 2000-5000 sccm.
S4: a back barrier layer is deposited on the buffer layer.
And growing AlGaN with the thickness of 10-30nm on the buffer layer by adopting an MOCVD (metal organic chemical vapor deposition) process to form a back barrier layer.
The specific process conditions are as follows: the pressure of the reaction chamber is 20-60Torr, the temperature is 1000-1200 deg.C, the flow rate of Al source is 20-50sccm, the flow rate of Ga source is 100-150sccm, the flow rate of ammonia is 3000-6000sccm, and the flow rate of hydrogen is 1200 sccm.
S5: an AlN insertion layer is formed on the back barrier layer.
Growing AlN with the thickness of 1-3nm on the back barrier layer by adopting an MOCVD (metal organic chemical vapor deposition) process to form an AlN insert layer; wherein the pressure in the reaction chamber is 20-60Torr, the temperature is 900-1100 deg.C, the flow of Al source is 200-600sccm, the flow of ammonia is 200-300sccm, and the flow of hydrogen is 1200 sccm.
S6: forming a p-type GaN layer on the AlN insert layer to complete the preparation of the heterojunction.
And growing a p-type GaN layer with the thickness of 50-100nm on the AlN insert layer by adopting an MOCVD process to finish the preparation of the heterojunction.
The specific process conditions are as follows: the pressure in the reaction chamber is 20-60Torr, the temperature is 1000-1200 deg.C, the flow rate of hydrogen is 1200sccm, the flow rate of gallium source is 150-180sccm, the flow rate of ammonia is 2000-5000sccm, and the flow rate of magnesium source is 100-200 sccm.
The preparation method provided by the embodiment is simple in process and easy to implement, the prepared two-dimensional hole gas heterojunction has high two-dimensional hole gas concentration, and due to deepening of the potential well, the hole gas is less affected by temperature and scattering, and has high temperature stability and carrier mobility.
Example four
The method of the present invention will be described in detail below by taking as an example the preparation of a heterojunction with a GaN nucleation layer thickness of 50nm, a GaN buffer layer thickness of 3 μm, an AlGaN back barrier layer thickness of 10nm, an AlN insertion layer of 1nm, and a p-type GaN layer of 50nm on a sapphire substrate.
Referring to fig. 4a to 4e, fig. 4a to 4e are schematic diagrams of a process for preparing a two-dimensional hole gas heterojunction based on an AlN insertion layer according to an embodiment of the present invention, which specifically includes:
step 1, cleaning the substrate.
And (3) putting the sapphire substrate into hydrofluoric acid for ultrasonic cleaning for 5min, then putting the sapphire substrate into an acetone solution for ultrasonic cleaning for 5min, then using an absolute ethyl alcohol solution for ultrasonic cleaning for 5min, then using deionized water for ultrasonic cleaning for 5min, and finally using nitrogen for drying.
And 2, carrying out heat treatment on the substrate.
Firstly, placing the cleaned sapphire substrate in a Metal Organic Chemical Vapor Deposition (MOCVD) reaction chamber, and reducing the vacuum degree of the reaction chamber to less than 2 x 10-2Torr; and introducing mixed gas of hydrogen and ammonia gas into the reaction chamber, heating the substrate to 1000 ℃ under the condition that the pressure of the MOCVD reaction chamber reaches 100Torr, and keeping the temperature for 5min to finish the heat treatment of the sapphire substrate.
And 3, growing the GaN nucleating layer.
The heat-treated sapphire substrate was placed in an MOCVD reactor, the pressure in the reactor was adjusted to 20Torr, and the temperature was adjusted to 560 ℃, and a GaN nucleation layer with a thickness of 50nm was grown on the substrate, as shown in fig. 4 a.
And 4, growing the GaN buffer layer.
A3 μm thick GaN buffer layer was grown on the GaN nucleation layer using the MOCVD process at a reaction chamber pressure of 40Torr and a temperature of 1100 deg.C, as shown in FIG. 4 b.
And 5, growing the AlGaN back barrier layer.
An AlGaN back barrier layer with a thickness of 10nm was grown on the GaN buffer layer by MOCVD under the conditions of a reaction chamber pressure of 60Torr and a temperature of 1000 c, as shown in fig. 4 c.
And 6, growing an AlN insert layer.
A1 nm thick AlN insert layer was grown on the AlGaN back barrier layer by the MOCVD process under the conditions of a reaction chamber pressure of 40Torr and a temperature of 1100 deg.C, as shown in FIG. 4 d.
And 7, growing a p-type GaN layer.
A50 nm thick p-type GaN layer was grown on the AlN insert layer by the MOCVD process under the conditions of a reaction chamber pressure of 50Torr and a temperature of 1100 deg.C to complete the preparation of the heterojunction, as shown in FIG. 4 e.
EXAMPLE five
The method of the present invention will be described in detail below by taking as an example the preparation of a heterojunction with an AlN nucleation layer thickness of 10nm, a GaN buffer layer thickness of 2 μm, an AlGaN back barrier layer thickness of 30nm, an AlN insertion layer thickness of 2nm, and a p-type GaN layer thickness of 70nm on a silicon substrate.
Step one, cleaning a substrate.
The silicon substrate is placed in hydrofluoric acid for ultrasonic cleaning for 5min, then placed in an acetone solution for ultrasonic cleaning for 5min, then absolute ethyl alcohol solution is used for ultrasonic cleaning for 5min, deionized water is used for ultrasonic cleaning for 5min, and finally nitrogen is used for blow-drying.
And step two, carrying out heat treatment on the substrate.
Firstly, the cleaned silicon substrate is placed in a Metal Organic Chemical Vapor Deposition (MOCVD) reaction chamber, and the vacuum degree of the reaction chamber is reduced toLess than 2 x 10-2Torr; and introducing mixed gas of hydrogen and ammonia gas into the reaction chamber, heating the substrate to 1000 ℃ under the condition that the pressure of the MOCVD reaction chamber reaches 100Torr, and keeping the temperature for 5min to finish the heat treatment of the silicon substrate.
And step three, growing an AlN nucleating layer.
The heat-treated silicon substrate was placed in an MOCVD reactor, the pressure in the reactor was adjusted to 40Torr, the temperature was adjusted to 900 ℃, and a 10nm thick AlN nucleation layer was grown on the substrate, as shown in fig. 4 a.
And step four, growing the GaN buffer layer.
A2 μm thick GaN buffer layer was grown on the AlN nucleation layer using an MOCVD process at a reaction chamber pressure of 20Torr and a temperature of 1000 deg.C, as shown in FIG. 4 b.
And step five, growing the AlGaN back barrier layer.
An AlGaN back barrier layer with a thickness of 30nm was grown on the GaN buffer layer by MOCVD under the conditions of a reaction chamber pressure of 20Torr and a temperature of 1200 c, as shown in fig. 4 c.
And step six, growing the AlN insert layer.
A 2nm thick AlN plug layer was grown on the AlGaN back barrier layer using MOCVD at a reaction chamber pressure of 20Torr and a temperature of 1000 c, as shown in fig. 4 d.
And step seven, growing a p-type GaN layer.
A70 nm thick p-type GaN layer was grown on the AlN insert layer by the MOCVD process under the conditions of a reaction chamber pressure of 60Torr and a temperature of 1000 deg.C to complete the preparation of the heterojunction, as shown in FIG. 4 e.
EXAMPLE six
The method of the present invention will be described in detail below by taking as an example the preparation of a heterojunction with 100nm thick AlN nucleation layer, 4 μm thick GaN buffer layer, 20nm thick AlGaN back barrier layer, 3nm thick AlN insertion layer and 100nm thick p-type GaN layer on a GaN substrate.
And step A, cleaning the substrate.
And (2) putting the gallium nitride substrate into hydrofluoric acid for ultrasonic cleaning for 5min, then putting the gallium nitride substrate into an acetone solution for ultrasonic cleaning for 5min, then using an absolute ethyl alcohol solution for ultrasonic cleaning for 5min, then using deionized water for ultrasonic cleaning for 5min, and finally using nitrogen for blow-drying.
And step B, carrying out heat treatment on the substrate.
Firstly, placing the cleaned gallium nitride substrate in a Metal Organic Chemical Vapor Deposition (MOCVD) reaction chamber, and reducing the vacuum degree of the reaction chamber to less than 2 x 10-2Torr; and introducing mixed gas of hydrogen and ammonia gas into the reaction chamber, heating the substrate to 1000 ℃ under the condition that the pressure of the MOCVD reaction chamber reaches 100Torr, and keeping the temperature for 5min to finish the heat treatment of the gallium nitride substrate.
And C, growing an AlN nucleating layer.
The heat-treated gallium nitride substrate was placed in an MOCVD reactor, the pressure in the MOCVD reactor was adjusted to 60Torr, and the temperature was adjusted to 700 ℃, and an AlN nucleation layer with a thickness of 100nm was grown on the substrate, as shown in fig. 4 a.
And D, growing the GaN buffer layer.
A4 μm thick GaN buffer layer was grown on the AlN nucleation layer using an MOCVD process at a reaction chamber pressure of 60Torr and a temperature of 1200 deg.C, as shown in FIG. 4 b.
And E, growing the AlGaN back barrier layer.
A20 nm thick AlGaN back barrier layer was grown on the GaN buffer layer by MOCVD at a reaction chamber pressure of 40Torr and a temperature of 1100 deg.C, as shown in FIG. 4 c.
And F, growing an AlN insert layer.
A 3nm thick AlN plug layer was grown on the AlGaN back barrier layer using an MOCVD process at a reaction chamber pressure of 60Torr and a temperature of 900 c, as shown in fig. 4 d.
And G, growing a p-type GaN layer.
A100 nm thick p-type GaN layer was grown on the AlN insert layer by the MOCVD process under the conditions of a reaction chamber pressure of 20Torr and a temperature of 1200 ℃ to complete the preparation of the heterojunction, as shown in FIG. 4 e.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Further, it should be noted that while the present embodiments provide examples of parameters including particular values, it should be appreciated that the parameters need not be exactly equal to the corresponding values, but rather approximate the corresponding values within acceptable error tolerances or design constraints.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. The utility model provides a two-dimentional hole gas heterojunction based on AlN inserted layer which characterized in that includes from bottom to top in proper order: the GaN-based light-emitting diode comprises a substrate layer (1), a nucleation layer (2), a buffer layer (3), a back barrier layer (4), an insertion layer (5) and a p-type GaN layer (6), wherein the insertion layer (5) is made of AlN.
2. A two-dimensional hole-gas heterojunction based on an AlN insertion layer according to claim 1, characterised in that the thickness of the insertion layer (5) is 1-3 nm.
3. The AlN insert layer-based two-dimensional hole-gas heterojunction according to claim 1, wherein the substrate layer (1) is a sapphire substrate, a silicon substrate, a gallium nitride substrate or a silicon carbide substrate.
4. A two-dimensional hole-gas heterojunction based on an AlN insertion layer according to claim 1, wherein the material of the nucleation layer (2) is GaN or AlN with a thickness of 10-100 nm;
the buffer layer (3) is made of GaN and has the thickness of 2-4 mu m;
the back barrier layer (4) is made of AlGaN and has the thickness of 10-30 nm;
the thickness of the p-type GaN layer (6) is 50-100 nm.
5. A PMOS device with an AlN insertion layer, comprising the two-dimensional hole gas heterojunction structure based on the AlN insertion layer according to any one of claims 1 to 4.
6. A preparation method of a two-dimensional hole gas heterojunction based on an AlN insert layer is characterized by comprising the following steps:
selecting a substrate and preprocessing the substrate;
depositing a nucleating layer on the pretreated substrate;
depositing a buffer layer on the nucleation layer;
depositing a back barrier layer on the buffer layer;
forming an AlN insert layer on the back barrier layer;
forming a p-type GaN layer on the AlN insert layer to complete the preparation of the heterojunction.
7. The method for preparing a two-dimensional hole gas heterojunction based on an AlN insertion layer according to claim 6, wherein the substrate is selected and pretreated, comprising:
sequentially putting the substrate into hydrofluoric acid, acetone solution, absolute ethyl alcohol solution and deionized water for ultrasonic cleaning;
and (3) placing the cleaned substrate in an MOCVD reaction chamber, introducing hydrogen and ammonia into the reaction chamber, and carrying out heat treatment on the substrate in a high-temperature environment.
8. The method of claim 6, wherein depositing a buffer layer on the nucleation layer comprises:
and growing GaN with the thickness of 2-4 mu m on the nucleation layer by adopting an MOCVD process to form a buffer layer.
9. The method of claim 6, wherein depositing a back barrier layer on the buffer layer comprises:
and growing AlGaN with the thickness of 10-30nm on the buffer layer by adopting an MOCVD (metal organic chemical vapor deposition) process to form a back barrier layer.
10. The method of claim 6, wherein forming an AlN insert layer on the back barrier layer comprises:
growing an AlN insert layer with the thickness of 1-3nm on the back barrier layer by adopting an MOCVD process; wherein the pressure in the reaction chamber is 20-60Torr, the temperature is 900-1100 deg.C, the flow of Al source is 200-600sccm, the flow of ammonia is 200-300sccm, and the flow of hydrogen is 1200 sccm.
CN202210158150.XA 2022-02-21 2022-02-21 AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device Pending CN114725195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210158150.XA CN114725195A (en) 2022-02-21 2022-02-21 AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210158150.XA CN114725195A (en) 2022-02-21 2022-02-21 AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device

Publications (1)

Publication Number Publication Date
CN114725195A true CN114725195A (en) 2022-07-08

Family

ID=82235773

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210158150.XA Pending CN114725195A (en) 2022-02-21 2022-02-21 AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device

Country Status (1)

Country Link
CN (1) CN114725195A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115036402A (en) * 2022-08-12 2022-09-09 江苏第三代半导体研究院有限公司 Induced enhanced Micro-LED homoepitaxy structure and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115036402A (en) * 2022-08-12 2022-09-09 江苏第三代半导体研究院有限公司 Induced enhanced Micro-LED homoepitaxy structure and preparation method thereof

Similar Documents

Publication Publication Date Title
CN101661878B (en) Method of double-element delta doped growth P-type GaN base material
CN106159048B (en) A kind of LED epitaxial slice and its growing method
CN112599648B (en) V-shaped tunneling junction LED epitaxial structure based on h-BN and preparation method thereof
CN114582972B (en) GAAFET device and preparation method thereof
CN106876529A (en) A kind of epitaxial wafer of gallium nitride based light emitting diode and preparation method thereof
CN109802020A (en) A kind of GaN base light emitting epitaxial wafer and preparation method thereof
WO2023231566A1 (en) Semiconductor epitaxial structure and preparation method therefor, and semiconductor device
CN111599901A (en) Ultraviolet LED epitaxial wafer grown on Si substrate and preparation method thereof
CN106876530B (en) A kind of epitaxial wafer of gallium nitride based light emitting diode and preparation method thereof
CN105098017A (en) N surface yellow-light LED material based on c-surface sapphire substrate and manufacturing method thereof
CN114725195A (en) AlN insertion layer-based two-dimensional hole gas heterojunction, preparation method thereof and PMOS device
CN103824916A (en) Growing method of composite nucleating layer for enhancing quality of gallium nitride crystal
CN107658374B (en) Epitaxial wafer of light emitting diode and preparation method thereof
CN101901758B (en) MOCVD growth method of non-polar m-surface GaN film based on m-surface SiC substrate
CN109346561B (en) Preparation method of GaN-based light-emitting diode epitaxial wafer
CN105140365A (en) C-surface sapphire substrate-based Ga polar yellow light-emitting diode (LED) material and fabrication method thereof
CN105118902A (en) Yellow LED material based on m-plane SiC substrate and manufacturing method thereof
CN112133799B (en) Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof
CN109473522B (en) Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof
CN101901760B (en) MOCVD growing method of polar c-plane GaN based on c-plane SiC substrate
CN112768570A (en) Method for manufacturing gallium nitride-based light emitting diode epitaxial wafer
CN107482093B (en) A kind of epitaxial wafer of light emitting diode and preparation method thereof
CN106299057A (en) A kind of LED epitaxial structure improving brightness band 3D layer
CN212907773U (en) Gallium nitride epitaxial chip
CN109346563A (en) A kind of preparation method and LED epitaxial slice of LED epitaxial slice

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination