CN114724504B

CN114724504B - Shift register unit, gate driving circuit, display substrate and display device

Info

Publication number: CN114724504B
Application number: CN202210530116.0A
Authority: CN
Inventors: 林允植; 李佩柔; 张振宇; 张震; 刘冬妮; 张舜航
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2023-12-12
Anticipated expiration: 2042-05-16
Also published as: CN114724504A

Abstract

The present disclosure provides a shift register unit, a gate driving circuit, a display substrate, and a display device. The shift register unit includes: an output circuit configured to transfer a clock signal provided by the clock signal terminal to at least the first signal output terminal under control of a voltage of the first node; the shift register unit further comprises a plurality of transistors, wherein the first electrode or the second electrode of the shift register unit is connected with the first node, at least one transistor in the plurality of transistors is a double-gate transistor, the first control electrode of the transistor is used for controlling the on-off state of the transistor, and the second control electrode of the transistor is connected with the fixed voltage end to receive a fixed voltage signal, so that leakage current of the transistor in the off state is inhibited. The shift register unit preferably outputs a signal waveform when the operating frequency is low.

Description

Shift register unit, gate driving circuit, display substrate and display device

Technical Field

The disclosure relates to a shift register unit, a gate driving circuit, a display substrate and a display device.

Background

This section is intended to provide a background or context for the embodiments recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

The pixel array of a display panel typically includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith. The driving of the gate lines may be implemented by an integrated driving circuit. With the increasing production process of amorphous silicon thin film transistors or oxide thin film transistors in recent years, a gate line driving circuit may be directly integrated on a thin film transistor array substrate to form GOA (Gate driver On Array) for driving a gate line. For example, GOAs composed of a plurality of cascaded shift register units may be used to provide a switching voltage signal to a plurality of rows of gate lines of a pixel array, so as to control the plurality of rows of gate lines to be sequentially opened for progressive scanning, and simultaneously provide a data signal to pixel units of corresponding rows in the pixel array by a data line, so as to form gray voltages required for each gray level of a display image at each pixel unit, thereby displaying one frame of image. Whether the voltage of the gate line is stable or not greatly affects the display quality.

Disclosure of Invention

The present disclosure provides a shift register unit, a gate driving circuit, a display substrate, and a display device.

The technical scheme adopted by the present disclosure is as follows: a shift register unit includes: an output circuit configured to transfer a clock signal provided by the clock signal terminal to at least the first signal output terminal under control of a voltage of the first node;

the shift register unit further comprises a plurality of transistors, wherein the first electrode or the second electrode of the shift register unit is connected with the first node, at least one transistor in the plurality of transistors is a double-gate transistor, the first control electrode of the transistor is used for controlling the on-off state of the transistor, and the second control electrode of the transistor is connected with the fixed voltage end to receive a fixed voltage signal, so that leakage current of the transistor in the off state is inhibited.

In some embodiments, the shift register unit specifically includes: the first transistor is a double-gate transistor, a first control electrode and a first electrode of the first transistor are connected with a cascading signal input end, a second electrode of the first transistor is connected with the first node, and a second control electrode of the first transistor is connected with a first fixed voltage end.

In some embodiments, the shift register unit specifically includes: the first control electrode of the second transistor is connected with the first reset signal end, the second control electrode of the second transistor is connected with the first fixed voltage end, and the first electrode and the second electrode of the second transistor are respectively connected with the first node and the second fixed voltage end.

In some embodiments, the shift register unit further includes: and a third transistor, wherein a control electrode of the third transistor is connected with the first reset signal end, and a first electrode and a second electrode of the third transistor are respectively connected with the first signal output end and the second fixed voltage end.

In some embodiments, the shift register unit further includes: and the first electrode and the second electrode of the fourth transistor are respectively connected with the first node and the second fixed voltage end.

In some embodiments, the shift register unit further includes: a first pull control circuit for controlling a voltage of a second node and a first pull circuit for setting the voltage of the first node to an invalid voltage under control of the voltage of the second node;

the first pull circuit includes: and the eighth transistor is a double-gate transistor, a first control electrode of the eighth transistor is connected with the second node, a second control electrode of the eighth transistor is connected with the first fixed voltage end, and a first electrode and a second electrode of the eighth transistor are respectively connected with the first node and the second fixed voltage end.

In some embodiments, the output circuit comprises: a first output transistor and a second output transistor; the control electrode of the first output transistor is connected with the first node, the first electrode of the first output transistor is connected with the clock signal end, and the second electrode of the first output transistor is connected with the first signal output end; the control electrode of the second output transistor is connected with the first node, the first electrode of the second output transistor is connected with the clock signal end, and the second electrode of the second output transistor is connected with the second signal output end; the first pull circuit further includes: a ninth transistor and a tenth transistor; the control electrode of the ninth transistor is connected with the second node, the first electrode of the ninth transistor is connected with the second signal output end, and the second electrode of the ninth transistor is connected with a second fixed voltage end; the control electrode of the tenth transistor is connected with the second node, the first electrode of the tenth transistor is connected with the first signal output end, and the second electrode of the tenth transistor is connected with the third fixed voltage end.

In some embodiments, the first pull control circuit includes: a fifth transistor, a sixth transistor, and a seventh transistor;

the control electrode and the first electrode of the fifth transistor are connected with a first control end, and the second electrode of the fifth transistor is connected with the second node;

the control electrode of the sixth transistor is connected with the first node, and the first electrode and the second electrode of the sixth transistor are respectively connected with the second node and the second fixed voltage end;

and a control electrode of the seventh transistor is connected with the cascade signal input end, and a first electrode and a second electrode of the seventh transistor are respectively connected with the second node and the second fixed voltage end.

In some embodiments, the shift register unit further includes: a second pull control circuit for controlling a voltage of a third node and a second pull circuit for setting the voltage of the first node to an invalid voltage under control of the voltage of the third node;

the second pull circuit includes: and the fourteenth transistor is a double-gate transistor, a first control electrode of the fourteenth transistor is connected with a third node, a second control electrode of the fourteenth transistor is connected with a first fixed voltage end, and a first electrode and a second electrode of the fourteenth transistor are respectively connected with the first node and the second fixed voltage end.

In some embodiments, the second pull circuit further comprises: a fifteenth transistor and a sixteenth transistor, wherein a control electrode of the fifteenth transistor is connected to the third node, a first electrode thereof is connected to the second signal output terminal, a second electrode thereof is connected to the second fixed voltage terminal, a control electrode of the sixteenth transistor is connected to the third node, a first electrode thereof is connected to the first signal output terminal, and a second electrode thereof is connected to the third fixed voltage terminal.

In some embodiments, the second pull control circuit includes: an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

the control electrode and the first electrode of the eleventh transistor are connected with a second control end, and the second electrode of the eleventh transistor is connected with the third node;

the control electrode of the twelfth transistor is connected with the first node, the first electrode of the twelfth transistor is connected with the third node, and the second electrode of the twelfth transistor is connected with the first fixed voltage end;

the control electrode of the thirteenth transistor is connected with the cascade signal input end, the first electrode of the thirteenth transistor is connected with the third node, and the second electrode of the thirteenth transistor is connected with the first fixed voltage end.

In some embodiments, the shift register unit further includes: a bootstrap capacitor connected between the first node and the first signal output terminal.

In some embodiments, the fixed voltage terminal provides a negative fixed voltage to increase a threshold voltage of the double-gate transistor with its own second control electrode connected to the fixed voltage terminal, wherein the double-gate transistor with its own second control electrode connected to the fixed voltage terminal is an N-type transistor;

or the fixed voltage terminal provides positive fixed voltage to reduce the threshold voltage of the double-gate transistor with the second control electrode connected with the fixed voltage terminal, wherein the double-gate transistor with the second control electrode connected with the fixed voltage terminal is a P-type transistor.

The technical scheme adopted by the present disclosure is as follows: the grid driving circuit is characterized by comprising a plurality of shift register units in cascade connection, wherein at least one shift register unit in the plurality of shift register units is the shift register unit.

The technical scheme adopted by the present disclosure is as follows: a display substrate comprises the gate driving circuit.

The technical scheme adopted by the present disclosure is as follows: a display device comprises the display substrate.

Drawings

Fig. 1 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure.

Fig. 2 is a block diagram of a shift register unit of another embodiment of the present disclosure.

Fig. 3 is a circuit diagram of a shift register cell of an embodiment of the present disclosure.

FIG. 4 is a waveform diagram illustrating performance testing of the shift register unit of the embodiment shown in FIG. 3.

Fig. 5 is a cross-sectional view of a display substrate of an embodiment of the present disclosure.

Fig. 6 is a cross-sectional view of a display substrate of another embodiment of the present disclosure.

1, an input circuit; m1, a first transistor; 2. an output circuit; m3, a first output transistor; m11, a second output transistor; 3. a first reset circuit; m2, a second transistor; m4, a third transistor; 4. a second reset circuit; m15, fourth transistor; 5. a first pull control circuit; M5A, fifth transistor; M6A, sixth transistor; M7A, seventh transistor; 6. a first pull circuit; M8A, eighth transistor; M12A, ninth transistor; M13A, tenth transistor; 7. a second pull control circuit; M5B, eleventh transistor; M6B, twelfth transistor; M7B, thirteenth transistor; 8. a second pull circuit; M8B, fourteenth transistor; M12B, fifteenth transistor; M13B, sixteenth transistor; c1, bootstrap capacitor; PU, first node; PD1, the second node; PD2, a third node; INPUT, cascade signal INPUT; CLK, clock signal terminal; OUT, the first signal output; out_c, the second signal output; RESET, first RESET signal terminal; t_reset, second RESET signal terminal; VDDN, a first fixed voltage terminal; LVGL, second fixed voltage terminal; VGL, third fixed voltage end; VDDo, first control end; VDDE, the second control end; VDD, power supply terminal; 10. a substrate; 20. a second control electrode; 30. a buffer layer; 40. an active layer; 50. a gate insulating layer; 60. a first control electrode; 70. an interlayer insulating layer; 80. a source/drain electrode; 90. a first passivation layer; 100. a planarization layer; 110. a common electrode; 120. a second passivation layer; 130. and a pixel electrode.

Detailed Description

The disclosure is further described below with reference to the embodiments shown in the drawings.

Fig. 1 shows a circuit diagram of a shift register cell of an embodiment of the present disclosure. Fig. 3 shows a circuit diagram of a shift register cell of another embodiment of the present disclosure. Fig. 5 and 6 are schematic structural diagrams of a part of the double gate transistor in the above two circuit diagrams.

The shift register unit provided by the embodiment of the disclosure comprises: an output circuit 2 configured to transfer the clock signal supplied from the clock signal terminal CLK to at least the first signal output terminal OUT under control of the voltage of the first node PU;

the shift register unit further includes a plurality of transistors having a first pole or a second pole connected to the first node PU, at least one of the plurality of transistors is a double-gate transistor, a first control pole 60 is used for controlling the on-off state of the transistor, and a second control pole 20 is connected to the fixed voltage terminal for receiving the fixed voltage signal, so as to inhibit leakage current in the off state.

The fixed voltage terminal provides negative fixed voltage to improve the threshold voltage of the double-gate transistor with the second control electrode 20 connected with the fixed voltage terminal, wherein the double-gate transistor with the second control electrode 20 connected with the fixed voltage terminal is an N-type transistor; alternatively, the fixed voltage terminal provides a positive fixed voltage to reduce the threshold voltage of the double-gate transistor with its own second control electrode 20 connected to the fixed voltage terminal, wherein the double-gate transistor with its own second control electrode 20 connected to the fixed voltage terminal is a P-type transistor.

When the double gate transistor is an N-type transistor and the second control electrode 20 thereof receives a negative fixed voltage, the second control electrode 20 repels electrons (electrons) in the active region of the double gate transistor. This causes the voltage of the first control electrode 60 to need to be set higher to form a channel in the active region of the double gate transistor. Thereby increasing the threshold voltage of the double gate transistor. When the threshold voltage of the N-type double gate transistor is raised, the leakage current thereof can be suppressed without changing the off-voltage supplied to the first control electrode 60 thereof.

When the double gate transistor is a P-type transistor and the second control electrode 20 thereof receives a positive fixed voltage, the second control electrode 20 repels minority carriers (holes) in the active region of the double gate transistor. This causes the voltage of the first control electrode 60 to be set lower to form a channel in the active region of the double gate transistor. Thereby lowering the threshold voltage of the double gate transistor. When the threshold voltage of the P-type double gate transistor is lowered, the leakage current thereof can be suppressed without changing the off-voltage supplied to the first control electrode 60 thereof.

Further, since the second control electrode 20 of the double gate transistor is connected to the fixed voltage terminal in the embodiment of the present disclosure, the power consumption required for supplying the fixed voltage signal to the fixed voltage terminal is very low. The wiring space occupied by the fixed voltage terminal in the display substrate is also relatively small, which contributes to an improvement in the integration level of the display substrate.

Fig. 5 and 6 each show one double gate transistor in a shift register unit in a gate driving circuit integrated on a liquid crystal display substrate.

The second control electrode 20 of the double gate transistor is arranged on the substrate 10. In some embodiments, the material of the substrate 10 includes: glass, or polyimide. In some embodiments, the material of the second control electrode 20 of the double gate transistor comprises: copper or aluminum.

The buffer layer 30 covers the second control electrode 20. The buffer layer 30 isolates the active layer 40 from the second control electrode 30. In some embodiments, the material of buffer layer 30 includes: silicon oxide or silicon nitride.

The active layer 40 is disposed on the buffer layer 30. The material of the active layer 40 includes amorphous silicon, polycrystalline silicon, or a transparent semiconductor oxide such as indium zinc oxide (IGZO). When the material of the active layer 40 is oxide, it is generally necessary to provide a metal light shielding layer on the side of the active layer 40 facing the substrate 10, and the metal light shielding layer also serves as the second control electrode 20. When the material of the active layer 40 is amorphous silicon or polysilicon, a metal light shielding layer is required to be additionally provided as the second control electrode 20.

The gate insulating layer 50 covers the active layer 40. In some embodiments, the material of the gate insulating layer 50 includes: silicon oxide or silicon nitride.

The first control electrode 60 is disposed on a side of the gate insulating layer 50 facing away from the active layer 40. In some embodiments, the material of the first control electrode 60 includes: elemental metals of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W), or metal alloys composed of these elemental metals.

The interlayer insulating layer 70 covers the first control electrode 60. In some embodiments, the material of the interlayer insulating layer 70 includes: silicon nitride or silicon oxide.

The source and drain electrodes 80 of the double gate transistor are disposed on the side of the interlayer insulating layer 70 facing away from the substrate 10 and connected to the active layer 40 through vias. The present disclosure does not distinguish between the source and drain 80 of the transistor, which are referred to as a first pole and a second pole, respectively.

The first passivation layer 90 covers the source and drain electrodes 80 of the double gate transistor, and the planarization layer 100 covers the first passivation layer 90. The first passivation layer 90 is used to prevent moisture from entering the interior of the double gate transistor. In some embodiments, the material of the first passivation layer 90 includes: silicon nitride. In some embodiments, the material of the planarization layer 100 includes: an organic resin.

The common electrode 110 is disposed on a side of the planarization layer 100 opposite to the substrate 10. The second passivation layer 120 covers the common electrode 110. The pixel electrode 130 is disposed on a side of the second passivation layer 120 opposite to the substrate 10.

In some embodiments, the material of the common electrode 110 includes: transparent conductor material such as indium tin oxide. In some embodiments, the material of the second passivation layer 120 includes: silicon oxide or silicon nitride. In some embodiments, the material of the pixel electrode 130 includes a transparent conductor material such as indium tin oxide.

The double gate transistor shown in fig. 6 is different from the double gate transistor shown in fig. 5 in that: one of the source and drain electrodes 80 is arranged in the same layer as the second control electrode 20. This makes it possible to fully utilize the space of the electrode layer where the second control electrode 20 is located, and to improve the degree of integration.

In the present disclosure, two electrode structures are arranged in the same layer, which means that they are formed by the same material layer, and the height of the two electrode structures is not limited to be the same.

The inventors of the present disclosure tested one shift register unit integrated in a liquid crystal display panel. The single-gate transistor (hereinafter, referred to as a transistor) and the double-gate transistor included in the shift register unit are both N-transistors. The following table is data from a test performed on a double gate transistor.

The second control electrode receives a fixed voltage (V)	Threshold voltage (V)
		-15	5.22
-10	3.5
		-5	1.83
0	0.12
		2	-0.56
4	-1.21
		5	-1.57
6	-1.93
		8	-2.59
10	-3.31
		15	-4.99

As can be seen from the test data of the above table, the threshold voltage of the double gate type transistor is increased from 0.12V to 1.83V when the fixed voltage supplied to the second control electrode of the double gate type transistor is-5V. Since these double gate type transistors are used as switching transistors, a slight increase in threshold voltage has an acceptable effect of reducing the driving capability of the double gate type transistor in the on state, and an effect of increasing the degree of turning off of the double gate type transistor in the off state is more remarkable.

In some embodiments, referring to fig. 1, the shift register unit includes: an input circuit 1, an output circuit 2 and a first reset circuit 3.

The INPUT circuit 1 is configured to set the voltage of the first node PU to an effective voltage under control of the cascade signal INPUT terminal INPUT. The single-gate transistor and the double-gate transistor in the shift register unit shown in fig. 1 are both N-type transistors, and the effective voltage is a high-level voltage.

The output circuit 2 is for transferring the voltage signal of the clock signal terminal CLK to the first signal output terminal OUT under the control of the first node PU.

The first RESET circuit 3 is configured to RESET the first node PU and the first signal output terminal OUT under control of the first RESET signal terminal RESET.

In some embodiments, the input circuit 1 comprises: the first transistor M1 of the double gate type, its first control electrode connects cascade signal INPUT end INPUT, its second control electrode connects first fixed voltage end VDDN, its first electrode connects power end VDD, its second electrode connects first node PU.

In some embodiments, the output circuit 2 comprises: the first output transistor M3 has a control electrode connected to the first node PU, a first electrode connected to the clock signal terminal CLK, and a second electrode connected to the first signal output terminal OUT.

In some embodiments, the first reset circuit 3 comprises: a third transistor M4 and a double gate type second transistor M2. The first control electrode of the second transistor M2 is connected to the first RESET signal terminal RESET, the second control electrode thereof is connected to the first voltage stabilizing terminal, the first electrode thereof is connected to the first node PU, and the second electrode thereof is connected to the second fixed voltage terminal LVGL. The third transistor M4 has a control electrode connected to the first RESET signal terminal RESET, a second electrode connected to the first signal output terminal OUT, and a second electrode connected to the second fixed voltage terminal LVGL.

The shift register unit further includes a bootstrap capacitor C1, two ends of which are respectively connected to the first node PU and the first signal output terminal OUT.

When a plurality of shift register units shown in fig. 1 are cascaded to obtain a gate driving circuit, the first signal output terminal OUT is connected to both the gate line to drive the gate line and the cascade signal INPUT terminal INPUT of the shift register unit of the next stage to provide a cascade INPUT signal.

In some other embodiments of the present disclosure, the shift register unit includes at least: an input circuit 1, an output circuit 2 and a first reset circuit 3.

An INPUT circuit 1 for setting the voltage of the first node PU to an active voltage under control of a cascade signal INPUT.

In some embodiments, the input circuit 1 comprises: the first transistor M1, the first transistor M1 is a dual-gate transistor, the first control electrode and the first electrode of the first transistor M1 are connected to the cascade signal INPUT terminal INPUT, the second electrode thereof is connected to the first node PU, and the second control electrode thereof is connected to the first fixed voltage terminal VDDN.

The first RESET circuit 3 is configured to RESET the voltages of the first node PU and the first signal output terminal OUT under the control of the first RESET signal terminal RESET.

In some embodiments, the first reset circuit 3 comprises: a second transistor M2 and a third transistor M4. The second transistor M2 is a dual-gate transistor, a first control electrode thereof is connected to the first RESET signal terminal RESET, a second control electrode thereof is connected to the first fixed voltage terminal VDDN, and a first electrode and a second electrode thereof are respectively connected to the first node PU and the second fixed voltage terminal LVGL. The third transistor M4 has a control electrode connected to the first RESET signal terminal RESET, and a first electrode and a second electrode connected to the first signal output terminal OUT and the second fixed voltage terminal LVGL, respectively.

An output circuit 2 for transferring the voltage of the clock signal terminal CLK to the first signal output terminal OUT and the second signal output terminal out_c under the control of the voltage of the first node PU. In the display substrate, the first signal output terminal OUT is used for driving one gate line, for example, and the second signal output terminal out_c provides a cascade input signal for a next stage shift register unit, for example.

In some embodiments, the output circuit 2 comprises: a first output transistor M3 and a second output transistor M11. The control electrode of the first output transistor M3 is connected to the first node PU, the first electrode thereof is connected to the clock signal terminal CLK, the second electrode thereof is connected to the first signal output terminal OUT, the control electrode of the second output transistor M11 is connected to the first node PU, the first electrode thereof is connected to the clock signal terminal CLK, and the second electrode thereof is connected to the second signal output terminal out_c.

In some embodiments, the shift register unit further includes: the second RESET circuit 4 is configured to RESET the voltage of the first node PU under the control of the second RESET signal terminal t_reset.

In the display substrate, the second RESET signal terminal t_reset is used for resetting the first node PU of all shift register units.

In some embodiments, the second reset module comprises: fourth transistor M15. The fourth transistor M15 is a dual-gate transistor, a first control electrode thereof is connected to the second RESET signal terminal t_reset, a second control electrode thereof is connected to the first fixed voltage terminal VDDN, and a first electrode and a second electrode thereof are respectively connected to the first node PU and the second fixed voltage terminal LVGL.

In some embodiments, the shift register unit further includes: a first pull control circuit 5 and a first pull circuit 6, the first pull control circuit 5 being for controlling the voltage of the second node PD1, the first pull circuit 6 being for setting the voltage of the first node PU to an invalid voltage under control of the voltage of the second node PD1. The transistors in the shift register unit shown in fig. 3 and the double gate transistor are both N-type transistors, the inactive voltage is a low level voltage.

In some embodiments, the first pull circuit 6 comprises: eighth transistor M8A. The eighth transistor M8A is a dual-gate transistor, a first control electrode thereof is connected to the second node PD1, a second control electrode thereof is connected to the first fixed voltage terminal VDDN, and a first electrode and a second electrode thereof are respectively connected to the first node PU and the second fixed voltage terminal LVGL.

In some embodiments, the first pull circuit 6 further comprises: a ninth transistor M12A and a tenth transistor M13A. The control electrode of the ninth transistor M12A is connected to the second node PD1, the first electrode thereof is connected to the second signal output terminal out_c, the second electrode thereof is connected to the second fixed voltage terminal LVGL, the control electrode of the tenth transistor M13A is connected to the second node PD1, the first electrode thereof is connected to the first signal output terminal OUT, and the second electrode thereof is connected to the third fixed voltage terminal VGL.

In some embodiments, the first pull control circuit 5 includes: a fifth transistor M5A, a sixth transistor M6A, and a seventh transistor M7A. The control pole and the first pole of the fifth transistor M5A are connected to the first control terminal VDDo, and the second pole thereof is connected to the second node PD1. The control electrode of the sixth transistor M6A is connected to the first node PU, and the first electrode and the second electrode thereof are respectively connected to the second node PD1 and the second fixed voltage terminal LVGL. The control electrode of the seventh transistor M7A is connected to the cascade signal INPUT terminal INPUT, and the first electrode and the second electrode thereof are respectively connected to the second node PD1 and the second fixed voltage terminal LVGL.

In the circuit diagram shown in fig. 3, the fifth transistor M5A is configured to set the second node PD1 high under the control of the first control terminal VDDo. The sixth transistor M6A is used to set the second node low under control of the first node PU. The seventh transistor M7A is configured to set the second node low under control of the cascade signal INPUT terminal INPUT.

In some embodiments, the shift register unit further includes: a second pull-in control circuit 7 and a second pull-in circuit 8, the second pull-in control circuit 7 being configured to control the voltage of the third node PD2, the second pull-in circuit 8 being configured to set the voltage of the first node PU to an invalid voltage under control of the voltage of the third node PD2.

In this way, the voltages of the second and third nodes PD1 and PD2 may be alternately set to the effective voltages, thereby preventing fatigue of the related transistors.

The second pull-in circuit 8 includes: fourteenth transistor M8B. The fourteenth transistor M8B is a dual-gate transistor, wherein a first control electrode thereof is connected to the third node PD2, a second control electrode thereof is connected to the first fixed voltage terminal VDDN, and a first electrode and a second electrode thereof are respectively connected to the first node PU and the second fixed voltage terminal LVGL.

In some embodiments, the second pull circuit 8 further comprises: the fifteenth transistor M12B and the sixteenth transistor M13B, wherein the control electrode of the fifteenth transistor M12B is connected to the third node PD2, the first electrode thereof is connected to the second signal output terminal out_c, the second electrode thereof is connected to the second fixed voltage terminal LVGL, the control electrode of the sixteenth transistor M13B is connected to the third node PD2, the first electrode thereof is connected to the first signal output terminal OUT, and the second electrode thereof is connected to the third fixed voltage terminal VGL.

In some embodiments, the second pull control circuit 7 includes: an eleventh transistor M5B, a twelfth transistor M6B, and a thirteenth transistor M7B. The control pole and the first pole of the eleventh transistor M5B are connected to the second control terminal VDDe, and the second pole thereof is connected to the third node PD2. The twelfth transistor M6B has a control electrode connected to the first node PU, a first electrode connected to the third node PD2, and a second electrode connected to the first fixed voltage terminal VDDN. The thirteenth transistor M7B has a control electrode connected to the cascade signal INPUT terminal INPUT, a first electrode connected to the third node PD2, and a second electrode connected to the first fixed voltage terminal VDDN.

In some embodiments, the shift register unit further includes: a bootstrap capacitor C1 connected between the first node PU and the first signal output terminal OUT.

Fig. 4 is a waveform diagram of the first node PU and the first signal output terminal OUT, which are obtained by driving the shift register unit shown in fig. 3. Regardless of whether the operating frequency of the shift register unit is 60Hz, 30Hz or 10Hz (when the first node PU is maintained at a high level for the longest time, the leakage time of the charges of the first node PU along the double-gate transistor connected thereto is also longest), the leakage current of the first node PU can be effectively suppressed, and the effective voltage of the first node PU is maintained at a stable high level voltage, which enables the first output transistor M3 to maintain a good on state during the on phase, thereby ensuring that the falling edge of the first signal output terminal OUT is steep.

The embodiment of the disclosure also provides a gate driving circuit, which comprises a plurality of shift register units in cascade connection, wherein at least one shift register unit in the plurality of shift register units is the shift register unit.

Embodiments of the present disclosure also provide a display substrate including the gate driving circuit of the foregoing embodiments. The display substrate is, for example, a liquid crystal display substrate or a light emitting diode display substrate. The light emitting diode display substrate is, for example, an organic light emitting diode display substrate or a micro light emitting diode display substrate.

The embodiment of the disclosure also provides a display device, and the display substrate. The display device is any component or product having a display function. The display device is, for example, a display panel, a display module, a mobile phone, a tablet computer, a display, an electronic billboard, a car navigator, a ground display screen, or the like.

The various embodiments in this disclosure are described in a progressive manner, and identical and similar parts of the various embodiments are all referred to each other, and each embodiment is mainly described as different from other embodiments.

The scope of the present disclosure is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present disclosure by those skilled in the art without departing from the scope and spirit of the disclosure. Such modifications and variations are intended to be included herein within the scope of the following claims and their equivalents.

Claims

1. A shift register unit, comprising: an output circuit (2) configured to transfer a clock signal provided by the clock signal terminal (CLK) to at least the first signal output terminal (OUT) under control of the voltage of the first node (PU);

the shift register unit further comprises a plurality of transistors, wherein a first electrode or a second electrode of the transistors is connected with the first node (PU), at least one transistor in the plurality of transistors is a double-gate transistor, a first control electrode of the transistor is used for controlling the on-off state of the transistor, and a second control electrode of the transistor is connected with a fixed voltage end to receive a fixed voltage signal, so that leakage current of the transistor in an off state is inhibited; wherein,

the shift register unit specifically includes: a first transistor (M1), wherein the first transistor (M1) is a double-gate transistor, a first control electrode and a first electrode of the first transistor (M1) are connected to a cascade signal INPUT terminal (INPUT), a second electrode thereof is connected to the first node (PU), and a second control electrode thereof is connected to a first fixed voltage terminal (VDDN);

the shift register unit specifically further includes: the second transistor (M2), the second transistor (M2) is a double-gate transistor, the first control electrode is connected with the first RESET signal end (RESET), the second control electrode is connected with the first fixed voltage end (VDDN), and the first electrode and the second electrode are respectively connected with the first node (PU) and the second fixed voltage end (LVGL).

2. The shift register unit of claim 1, wherein the shift register unit further comprises: and a third transistor (M4) having a control electrode connected to the first RESET signal terminal (RESET), and a first electrode and a second electrode connected to the first signal output terminal (OUT) and the second fixed voltage terminal (LVGL), respectively.

3. The shift register unit of claim 1, wherein the shift register unit further comprises: and the fourth transistor (M15), the fourth transistor (M15) is a double-gate transistor, the first control electrode of the fourth transistor is connected with the second RESET signal end (T_RESET), the second control electrode of the fourth transistor is connected with the first fixed voltage end (VDDN), and the first electrode and the second electrode of the fourth transistor are respectively connected with the first node (PU) and the second fixed voltage end (LVGL).

4. The shift register unit of claim 1, wherein the shift register unit further comprises: a first pull control circuit (5) and a first pull circuit (6), the first pull control circuit (5) being for controlling the voltage of a second node (PD 1), the first pull circuit (6) being for setting the voltage of the first node (PU) to an inactive voltage under control of the voltage of the second node (PD 1);

the first pull-out circuit (6) comprises: and an eighth transistor (M8A), wherein the eighth transistor (M8A) is a double-gate transistor, a first control electrode thereof is connected to the second node (PD 1), a second control electrode thereof is connected to the first fixed voltage terminal (VDDN), and a first electrode and a second electrode thereof are respectively connected to the first node (PU) and the second fixed voltage terminal (LVGL).

5. The shift register cell as claimed in claim 4, wherein,

the output circuit (2) includes: a first output transistor (M3) and a second output transistor (M11);

the control electrode of the first output transistor (M3) is connected with the first node (PU), the first electrode of the first output transistor is connected with the clock signal end (CLK), and the second electrode of the first output transistor is connected with the first signal output end (OUT);

the control electrode of the second output transistor (M11) is connected with the first node (PU), the first electrode thereof is connected with the clock signal end (CLK), and the second electrode thereof is connected with the second signal output end (OUT_C);

the first pull-in circuit (6) further comprises: a ninth transistor (M12A) and a tenth transistor (M13A);

-the control electrode of the ninth transistor (M12A) is connected to the second node (PD 1), the first electrode thereof being connected to the second signal output terminal (out_c), and the second electrode thereof being connected to a second fixed voltage terminal (LVGL);

the control electrode of the tenth transistor (M13A) is connected to the second node (PD 1), the first electrode thereof is connected to the first signal output terminal (OUT), and the second electrode thereof is connected to a third fixed voltage terminal (VGL).

6. A shift register unit according to claim 5, characterized in that the first pull-out control circuit (5) comprises: a fifth transistor (M5A), a sixth transistor (M6A), and a seventh transistor (M7A);

-the control and first poles of the fifth transistor (M5A) are connected to a first control terminal (VDDo), the second pole of which is connected to the second node (PD 1);

-the control electrode of the sixth transistor (M6A) is connected to the first node (PU), the first and second electrodes thereof being connected to the second node (PD 1) and to a second fixed voltage terminal (LVGL), respectively;

the control electrode of the seventh transistor (M7A) is connected to the cascade signal INPUT (INPUT), and the first electrode and the second electrode thereof are respectively connected to the second node (PD 1) and the second fixed voltage terminal (LVGL).

7. The shift register cell of claim 4, wherein the shift register cell further comprises: a second pull control circuit (7) and a second pull circuit (8), the second pull control circuit (7) being for controlling the voltage of a third node (PD 2), the second pull circuit (8) being for setting the voltage of the first node (PU) to an inactive voltage under control of the voltage of the third node (PD 2);

the second pull-in circuit (8) comprises: a fourteenth transistor (M8B), wherein the fourteenth transistor (M8B) is a double-gate transistor, a first control electrode thereof is connected to the third node (PD 2), a second control electrode thereof is connected to the first fixed voltage terminal (VDDN), and a first electrode and a second electrode thereof are respectively connected to the first node (PU) and the second fixed voltage terminal (LVGL).

8. A shift register unit according to claim 7, characterized in that the second pull-in circuit (8) further comprises: a fifteenth transistor (M12B) and a sixteenth transistor (M13B), wherein a control electrode of the fifteenth transistor (M12B) is connected to the third node (PD 2), a first electrode thereof is connected to the second signal output terminal (out_c), a second electrode thereof is connected to the second fixed voltage terminal (LVGL), a control electrode of the sixteenth transistor (M13B) is connected to the third node (PD 2), a first electrode thereof is connected to the first signal output terminal (OUT), and a second electrode thereof is connected to the third fixed voltage terminal (VGL).

9. A shift register unit according to claim 7, characterized in that the second pull-out control circuit (7) comprises: an eleventh transistor (M5B), a twelfth transistor (M6B), and a thirteenth transistor (M7B);

-a control electrode and a first electrode of the eleventh transistor (M5B) are connected to a second control terminal (VDDe), a second electrode of which is connected to the third node (PD 2);

-a control electrode of said twelfth transistor (M6B) is connected to said first node (PU), a first electrode thereof is connected to said third node (PD 2), and a second electrode thereof is connected to said first fixed voltage terminal (VDDN);

the thirteenth transistor (M7B) has its control electrode connected to the cascade signal INPUT (INPUT), its first electrode connected to the third node (PD 2), and its second electrode connected to the first fixed voltage terminal (VDDN).

10. The shift register unit of claim 1, wherein the shift register unit further comprises: -a bootstrap capacitor (C1) connected between said first node (PU) and said first signal output terminal (OUT).

11. The shift register cell of claim 1, wherein the fixed voltage terminal provides a negative fixed voltage to raise a threshold voltage of the double-gate transistor having its own second control electrode connected to the fixed voltage terminal, wherein the double-gate transistor having its own second control electrode connected to the fixed voltage terminal is an N-type transistor;

12. A gate drive circuit comprising a cascade of a plurality of shift register cells, at least one of the plurality of shift register cells being a shift register cell according to any one of claims 1 to 11.

13. A display substrate comprising the gate driving circuit according to claim 12.

14. A display device comprising the display substrate according to claim 13.