CN114724504A

CN114724504A - Shifting register unit, grid driving circuit, display substrate and display device

Info

Publication number: CN114724504A
Application number: CN202210530116.0A
Authority: CN
Inventors: 林允植; 李佩柔; 张振宇; 张震; 刘冬妮; 张舜航
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2022-07-08
Anticipated expiration: 2042-05-16
Also published as: CN114724504B

Abstract

The disclosure provides a shift register unit, a gate driving circuit, a display substrate and a display device. The shift register unit includes: an output circuit configured to pass a clock signal provided by the clock signal terminal to at least the first signal output terminal under control of a voltage of the first node; the shift register unit also comprises a plurality of transistors of which the first poles or the second poles are connected with the first nodes, at least one transistor in the plurality of transistors is a double-gate transistor, the first control pole of the transistor is used for controlling the on-off state of the transistor, and the second control pole of the transistor is connected with the fixed voltage end to receive a fixed voltage signal, so that the leakage current of the transistor in the off state is inhibited. The shifting register unit outputs better signal waveform when the working frequency is lower.

Description

Shifting register unit, grid driving circuit, display substrate and display device

Technical Field

The present disclosure relates to the field of display technologies, and more particularly, in some embodiments, to a shift register unit, a gate driving circuit, a display substrate, and a display device.

Background

This section is intended to provide a background or context to the embodiments recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

A pixel array of a display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith. The driving of the gate lines may be realized by an integrated driving circuit. In recent years, with the continuous improvement of the manufacturing process of the amorphous silicon thin film transistor or the oxide thin film transistor, the gate line driving circuit can also be directly integrated On the thin film transistor array substrate to form a gate driver On array (goa) to drive the gate line. For example, the GOA composed of a plurality of cascaded shift register units can be used to provide switching-state voltage signals to a plurality of rows of gate lines of the pixel array, so as to control the plurality of rows of gate lines to be sequentially opened for line-by-line scanning, and simultaneously provide data signals to corresponding rows of pixel units in the pixel array from the data lines, so as to form gray voltages required for displaying gray scales of an image in each pixel unit, thereby displaying a frame of image. Whether the voltage of the gate line is stable greatly affects the display quality.

Disclosure of Invention

The disclosure provides a shift register unit, a gate driving circuit, a display substrate and a display device.

The technical scheme adopted by the disclosure is as follows: a shift register unit includes: an output circuit configured to pass a clock signal provided by the clock signal terminal to at least the first signal output terminal under control of a voltage of the first node;

the shift register unit also comprises a plurality of transistors of which the first poles or the second poles are connected with the first nodes, at least one transistor in the plurality of transistors is a double-gate transistor, the first control pole of the transistor is used for controlling the on-off state of the transistor, and the second control pole of the transistor is connected with the fixed voltage end to receive a fixed voltage signal, so that the leakage current of the transistor in the off state is inhibited.

In some embodiments, the shift register unit specifically includes: the first transistor is a double-gate transistor, a first control electrode and a first electrode of the first transistor are connected with the cascade signal input end, a second electrode of the first transistor is connected with the first node, and a second control electrode of the first transistor is connected with the first fixed voltage end.

In some embodiments, the shift register unit specifically includes: and the first control electrode of the second transistor is connected with the first reset signal end, the second control electrode of the second transistor is connected with the first fixed voltage end, and the first electrode and the second electrode of the second transistor are respectively connected with the first node and the second fixed voltage end.

In some embodiments, the shift register cell further comprises: and a third transistor having a control electrode connected to the first reset signal terminal, and a first electrode and a second electrode connected to the first signal output terminal and the second fixed voltage terminal, respectively.

In some embodiments, the shift register cell further comprises: and the fourth transistor is a double-gate transistor, the first control electrode of the fourth transistor is connected with the second reset signal end, the second control electrode of the fourth transistor is connected with the first fixed voltage end, and the first electrode and the second electrode of the fourth transistor are respectively connected with the first node and the second fixed voltage end.

In some embodiments, the shift register cell further comprises: a first pull control circuit for controlling a voltage of a second node, and a first pull circuit for setting the voltage of the first node to an inactive voltage under the control of the voltage of the second node;

the first pull circuit includes: and the eighth transistor is a double-gate transistor, the first control electrode of the eighth transistor is connected with the second node, the second control electrode of the eighth transistor is connected with the first fixed voltage end, and the first electrode and the second electrode of the eighth transistor are respectively connected with the first node and the second fixed voltage end.

In some embodiments, the output circuit comprises: a first output transistor and a second output transistor; the control electrode of the first output transistor is connected with the first node, the first electrode of the first output transistor is connected with the clock signal end, and the second electrode of the first output transistor is connected with the first signal output end; the control electrode of the second output transistor is connected with the first node, the first electrode of the second output transistor is connected with the clock signal end, and the second electrode of the second output transistor is connected with the second signal output end; the first pull circuit further comprises: a ninth transistor and a tenth transistor; a control electrode of the ninth transistor is connected with the second node, a first electrode of the ninth transistor is connected with the second signal output end, and a second electrode of the ninth transistor is connected with a second fixed voltage end; a control electrode of the tenth transistor is connected to the second node, a first electrode thereof is connected to the first signal output terminal, and a second electrode thereof is connected to a third fixed voltage terminal.

In some embodiments, the first pull control circuit comprises: a fifth transistor, a sixth transistor, and a seventh transistor;

the control electrode and the first electrode of the fifth transistor are connected with the first control end, and the second electrode of the fifth transistor is connected with the second node;

a control electrode of the sixth transistor is connected with the first node, and a first electrode and a second electrode of the sixth transistor are respectively connected with the second node and a second fixed voltage end;

and a control electrode of the seventh transistor is connected with a cascade signal input end, and a first electrode and a second electrode of the seventh transistor are respectively connected with the second node and the second fixed voltage end.

In some embodiments, the shift register cell further comprises: a second pull control circuit for controlling a voltage of a third node, and a second pull circuit for setting the voltage of the first node to an inactive voltage under the control of the voltage of the third node;

the second pull circuit includes: and a fourteenth transistor which is a double-gate transistor, a first control electrode of which is connected to the third node, a second control electrode of which is connected to the first fixed voltage terminal, and a first electrode and a second electrode of which are respectively connected to the first node and the second fixed voltage terminal.

In some embodiments, the second pull circuit further comprises: a fifteenth transistor and a sixteenth transistor, wherein a control electrode of the fifteenth transistor is connected to the third node, a first electrode thereof is connected to the second signal output terminal, a second electrode thereof is connected to the second fixed voltage terminal, a control electrode of the sixteenth transistor is connected to the third node, a first electrode thereof is connected to the first signal output terminal, and a second electrode thereof is connected to the third fixed voltage terminal.

In some embodiments, the second pull control circuit comprises: an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

a control electrode and a first electrode of the eleventh transistor are connected with a second control end, and a second electrode of the eleventh transistor is connected with the third node;

a control electrode of the twelfth transistor is connected to the first node, a first electrode thereof is connected to the third node, and a second electrode thereof is connected to the first fixed voltage terminal;

and the control electrode of the thirteenth transistor is connected with the cascade signal input end, the first electrode of the thirteenth transistor is connected with the third node, and the second electrode of the thirteenth transistor is connected with the first fixed voltage end.

In some embodiments, the shift register cell further comprises: a bootstrap capacitor connected between the first node and the first signal output terminal.

In some embodiments, the fixed voltage terminal provides a negative fixed voltage to increase a threshold voltage of the dual-gate transistor whose own second control gate is connected to the fixed voltage terminal, wherein the dual-gate transistor whose own second control gate is connected to the fixed voltage terminal is an N-type transistor;

or the fixed voltage end provides positive fixed voltage to reduce the threshold voltage of the double-gate transistor of which the second control electrode is connected with the fixed voltage end, wherein the double-gate transistor of which the second control electrode is connected with the fixed voltage end is a P-type tube.

The technical scheme adopted by the disclosure is as follows: the gate driving circuit is characterized by comprising a plurality of cascaded shift register units, wherein at least one shift register unit in the plurality of shift register units is the shift register unit.

The technical scheme adopted by the disclosure is as follows: a display substrate comprises the gate driving circuit.

The technical scheme adopted by the disclosure is as follows: a display device comprises the display substrate.

Drawings

Fig. 1 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure.

FIG. 2 is a block diagram of a shift register cell according to another embodiment of the disclosure.

Fig. 3 is a circuit diagram of a shift register cell of an embodiment of the present disclosure.

Fig. 4 is a waveform diagram for performance testing of the shift register unit of the embodiment shown in fig. 3.

Fig. 5 is a cross-sectional view of a display substrate of an embodiment of the disclosure.

Fig. 6 is a cross-sectional view of a display substrate according to another embodiment of the present disclosure.

Wherein, 1, an input circuit; m1, a first transistor; 2. an output circuit; m3, a first output transistor; m11, a second output transistor; 3. a first reset circuit; m2, a second transistor; m4, a third transistor; 4. a second reset circuit; m15, a fourth transistor; 5. a first pull control circuit; M5A, fifth transistor; M6A, sixth transistor; M7A, seventh transistor; 6. a first pull circuit; M8A, eighth transistor; M12A, ninth transistor; M13A, tenth transistor; 7. a second pull control circuit; M5B, an eleventh transistor; M6B, twelfth transistor; M7B, thirteenth transistor; 8. a second pull circuit; M8B, fourteenth transistor; M12B, fifteenth transistor; M13B, sixteenth transistor; c1, bootstrap capacitor; PU, a first node; PD1, second node; PD2, third node; INPUT, cascade signal INPUT; CLK, clock signal terminal; OUT, a first signal output terminal; OUT _ C, a second signal output end; RESET, a first RESET signal terminal; t _ RESET and a second RESET signal terminal; VDDN, a first fixed voltage terminal; LVGL, second fixed voltage terminal; VGL, third fixed voltage terminal; VDDo, first control end; VDDE, a second control terminal; VDD, power supply terminal; 10. a substrate; 20. a second control electrode; 30. a buffer layer; 40. an active layer; 50. a gate insulating layer; 60. a first control electrode; 70. an interlayer insulating layer; 80. a source and a drain; 90. a first passivation layer; 100. a planarization layer; 110. a common electrode; 120. a second passivation layer; 130. and a pixel electrode.

Detailed Description

The disclosure will be further described with reference to the embodiments shown in the drawings.

Fig. 1 shows a circuit diagram of a shift register unit according to an embodiment of the present disclosure. Fig. 3 shows a circuit diagram of a shift register cell of another embodiment of the present disclosure. Fig. 5 and 6 are schematic structural diagrams of a part of the double-gate transistor in the above two circuit diagrams.

The shift register unit provided by the embodiment of the disclosure includes: an output circuit 2 configured to transfer the clock signal provided by the clock signal terminal CLK to at least the first signal output terminal OUT under the control of the voltage of the first node PU;

the shift register unit further includes a plurality of transistors having their first or second electrodes connected to the first node PU, at least one of the transistors is a dual gate transistor and has a first control electrode 60 for controlling its on/off state, and a second control electrode 20 connected to the fixed voltage terminal for receiving the fixed voltage signal, thereby suppressing leakage current thereof in the off state.

The fixed voltage end provides a negative fixed voltage to improve the threshold voltage of the double-gate transistor of which the second control electrode 20 is connected with the fixed voltage end, wherein the double-gate transistor of which the second control electrode 20 is connected with the fixed voltage end is an N-type tube; or, the fixed voltage terminal provides a positive fixed voltage to lower the threshold voltage of the dual-gate transistor whose own second control gate 20 is connected to the fixed voltage terminal, wherein the dual-gate transistor whose own second control gate 20 is connected to the fixed voltage terminal is a P-type transistor.

When the double-gate transistor is an N-type transistor and the second control electrode 20 receives a negative fixed voltage, the second control electrode 20 repels minority carriers (electrons) in the active region of the double-gate transistor. This causes the voltage of the first control gate 60 to need to be set higher to form a channel in the active region of the double-gate transistor. Thereby increasing the threshold voltage of the double gate transistor. When the threshold voltage of the N-type double gate transistor is increased, the leakage current can be suppressed without changing the off-voltage applied to the first control electrode 60.

When the double-gate transistor is a P-type transistor and the second control electrode 20 receives a positive fixed voltage, the second control electrode 20 repels minority carriers (holes) in the active region of the double-gate transistor. This results in the voltage of the first control gate 60 needing to be set lower to form a channel in the active region of the double-gated transistor. Thereby lowering the threshold voltage of the double gate type transistor. When the threshold voltage of the P-type double gate transistor is lowered, the leakage current thereof can be suppressed without changing the off-voltage applied to the first control electrode 60 thereof.

Further, since the second control electrode 20 of the double-gate transistor in the embodiment of the present disclosure is connected to the fixed voltage terminal, power consumption required to supply the fixed voltage signal to the fixed voltage terminal is very low. The wiring space occupied by the fixed voltage terminal in the display substrate is also relatively small, which contributes to an increase in the degree of integration of the display substrate.

Fig. 5 and 6 each show one double gate type transistor in a shift register cell integrated in a gate driver circuit on a liquid crystal display substrate.

The second control gate 20 of the double-gate transistor is provided on the substrate 10. In some embodiments, the materials of the substrate 10 include: glass, or polyimide. In some embodiments, the material of the second control gate 20 of the double-gate transistor comprises: copper or aluminum.

The buffer layer 30 covers the second control electrode 20. The buffer layer 30 insulates the active layer 40 from the second control electrode 30. In some embodiments, the material of buffer layer 30 includes: an oxide of silicon or a nitride of silicon.

The active layer 40 is disposed on the buffer layer 30. The material of the active layer 40 includes amorphous silicon, polycrystalline silicon, or a transparent semiconductor oxide such as indium zinc oxide (IGZO). When the material of the active layer 40 is an oxide, it is usually necessary to provide a metal light shielding layer on the side of the active layer 40 facing the substrate 10, and the metal light shielding layer also serves as the second control electrode 20. When the material of the active layer 40 is amorphous silicon or polysilicon, a metal light shielding layer is additionally required to be disposed as the second control electrode 20.

The gate insulating layer 50 covers the active layer 40. In some embodiments, the material of the gate insulating layer 50 includes: an oxide of silicon or a nitride of silicon.

The first control electrode 60 is disposed on a side of the gate insulating layer 50 opposite to the active layer 40. In some embodiments, the material of the first control electrode 60 includes: the metal alloy is composed of simple metal substances of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr) and tungsten (W) or metal alloys composed of the simple metal substances.

The interlayer insulating layer 70 covers the first control electrode 60. In some embodiments, the material of the interlayer insulating layer 70 includes: silicon nitride or silicon oxide.

The source and drain electrodes 80 of the double gate type transistor are disposed on the side of the interlayer insulating layer 70 facing away from the substrate 10 and are connected to the active layer 40 through via holes. The present disclosure does not distinguish between the source and drain 80 of the transistor, which are referred to as the first and second poles, respectively.

The first passivation layer 90 covers the source and drain electrodes 80 of the double gate type transistor, and the planarization layer 100 covers the first passivation layer 90. The first passivation layer 90 is used to prevent water vapor from entering the interior of the double gate type transistor. In some embodiments, the material of the first passivation layer 90 includes: a nitride of silicon. In some embodiments, the materials of the planarization layer 100 include: an organic resin.

The common electrode 110 is disposed on a side of the planarization layer 100 opposite to the substrate 10. The second passivation layer 120 covers the common electrode 110. The pixel electrode 130 is disposed on a side of the second passivation layer 120 opposite to the substrate 10.

In some embodiments, the material of the common electrode 110 includes: a transparent conductor material such as indium tin oxide. In some embodiments, the material of the second passivation layer 120 includes: an oxide of silicon or a nitride of silicon. In some embodiments, the material of the pixel electrode 130 includes a transparent conductor material such as indium tin oxide.

The dual-gate transistor shown in fig. 6 is different from the dual-gate transistor shown in fig. 5 in that: one of its source and drain electrodes 80 is disposed in the same layer as the second control electrode 20. This can make full use of the space of the electrode layer where the second control electrode 20 is located, improving the integration level.

In the present disclosure, the two electrode structures are disposed in the same layer, which means that the two electrode structures are formed by the same material layer, and the heights of the two electrode structures are not limited to be the same.

The inventors of the present disclosure tested one shift register unit integrated in a liquid crystal display panel. The single-gate transistor (hereinafter referred to as transistor) and the double-gate transistor included in the shift register unit are both N-type transistors. The following table shows the data for testing a double-gate transistor.

A fixed voltage (V) received by the second control electrode	Threshold voltage (V)
		-15	5.22
-10	3.5
		-5	1.83
0	0.12
		2	-0.56
4	-1.21
		5	-1.57
6	-1.93
		8	-2.59
10	-3.31
		15	-4.99

From the above table of test data, it can be seen that the threshold voltage of the double-gate transistor is raised from 0.12V to 1.83V when the fixed voltage applied to the second control gate of the double-gate transistor is-5V. Since the dual-gate transistors are used as switching transistors, a slight increase in threshold voltage has acceptable effect on reduction of driving capability of the dual-gate transistors in an on state, and has more significant effect on improvement of off degree of the dual-gate transistors in an off state.

In some embodiments, referring to fig. 1, a shift register unit includes: an input circuit 1, an output circuit 2 and a first reset circuit 3.

The INPUT circuit 1 is used to set the voltage of the first node PU to an effective voltage under the control of the cascade signal INPUT terminal INPUT. The single-gate transistor and the double-gate transistor in the shift register unit shown in fig. 1 are both N-type transistors, and the effective voltage is a high-level voltage.

The output circuit 2 is used for transmitting the voltage signal of the clock signal terminal CLK to the first signal output terminal OUT under the control of the first node PU.

The first RESET circuit 3 is configured to RESET the first node PU and the first signal output terminal OUT under the control of the first RESET signal terminal RESET.

In some embodiments, the input circuit 1 includes: the first transistor M1 of the double-gate type has a first control electrode connected to the cascade signal INPUT terminal INPUT, a second control electrode connected to the first fixed voltage terminal VDDN, a first electrode connected to the power supply terminal VDD, and a second electrode connected to the first node PU.

In some embodiments, the output circuit 2 includes: the first output transistor M3 has a control electrode connected to the first node PU, a first electrode connected to the clock signal terminal CLK, and a second electrode connected to the first signal output terminal OUT.

In some embodiments, the first reset circuit 3 includes: a third transistor M4 and a second transistor M2 of a double gate type. A first control electrode of the second transistor M2 is connected to the first RESET signal terminal RESET, a second control electrode thereof is connected to the first voltage regulation terminal, a first electrode thereof is connected to the first node PU, and a second electrode thereof is connected to the second fixed voltage terminal LVGL. A control electrode of the third transistor M4 is connected to the first RESET signal terminal RESET, a second electrode thereof is connected to the first signal output terminal OUT, and a second electrode thereof is connected to the second fixed voltage terminal LVGL.

The shift register unit further includes a bootstrap capacitor C1, two ends of which are respectively connected to the first node PU and the first signal output terminal OUT.

When a plurality of shift register units shown in fig. 1 are cascaded to obtain a gate driving circuit, the first signal output terminal OUT is connected to both the gate line to drive the gate line and the cascade signal INPUT terminal INPUT of the next shift register unit to provide a cascade INPUT signal.

In other embodiments of the present disclosure, the shift register unit includes at least: an input circuit 1, an output circuit 2, and a first reset circuit 3.

An INPUT circuit 1 for setting the voltage of the first node PU to an effective voltage under the control of the cascade signal INPUT terminal INPUT.

In some embodiments, the input circuit 1 includes: the first transistor M1, the first transistor M1 is a double-gate transistor, the first control electrode and the first electrode of the first transistor M1 are connected to the cascade signal INPUT terminal INPUT, the second electrode thereof is connected to the first node PU, and the second control electrode thereof is connected to the first fixed voltage terminal VDDN.

The first RESET circuit 3 is configured to RESET the voltages at the first node PU and the first signal output terminal OUT under the control of the first RESET signal terminal RESET.

In some embodiments, the first reset circuit 3 includes: a second transistor M2 and a third transistor M4. The second transistor M2 is a double-gate transistor, and has a first control electrode connected to the first RESET signal terminal RESET, a second control electrode connected to the first fixed voltage terminal VDDN, and a first electrode and a second electrode connected to the first node PU and the second fixed voltage terminal LVGL, respectively. A control electrode of the third transistor M4 is connected to the first RESET signal terminal RESET, and a first electrode and a second electrode thereof are connected to the first signal output terminal OUT and the second fixed voltage terminal LVGL, respectively.

And an output circuit 2 for transferring the voltage of the clock signal terminal CLK to the first and second signal output terminals OUT and OUT _ C under the control of the voltage of the first node PU. In the display substrate, the first signal output terminal OUT is used to drive one gate line, for example, and the second signal output terminal OUT _ C provides a cascade input signal for a next stage of shift register unit, for example.

In some embodiments, the output circuit 2 includes: a first output transistor M3 and a second output transistor M11. The control electrode of the first output transistor M3 is connected to the first node PU, the first electrode thereof is connected to the clock signal terminal CLK, the second electrode thereof is connected to the first signal output terminal OUT, the control electrode of the second output transistor M11 is connected to the first node PU, the first electrode thereof is connected to the clock signal terminal CLK, and the second electrode thereof is connected to the second signal output terminal OUT _ C.

In some embodiments, the shift register cell further comprises: the second RESET circuit 4 is configured to RESET the voltage of the first node PU under the control of the second RESET signal terminal T _ RESET.

In the display substrate, the second RESET signal terminal T _ RESET is used to RESET the first nodes PU of all the shift register units.

In some embodiments, the second reset module comprises: and a fourth transistor M15. The fourth transistor M15 is a double-gate transistor, and has a first gate connected to the second RESET signal terminal T _ RESET, a second gate connected to the first fixed voltage terminal VDDN, and a first gate and a second gate connected to the first node PU and the second fixed voltage terminal LVGL, respectively.

In some embodiments, the shift register cell further comprises: a first pull control circuit 5 and a first pull circuit 6, the first pull control circuit 5 is used for controlling the voltage of the second node PD1, the first pull circuit 6 is used for setting the voltage of the first node PU to an invalid voltage under the control of the voltage of the second node PD 1. In the shift register unit shown in fig. 3, the transistors and the dual-gate transistors are both N-type transistors, and the inactive voltage is a low level voltage.

In some embodiments, the first pull circuit 6 includes: an eighth transistor M8A. The eighth transistor M8A is a double-gate transistor, and has a first control electrode connected to the second node PD1, a second control electrode connected to the first fixed voltage terminal VDDN, and a first electrode and a second electrode connected to the first node PU and the second fixed voltage terminal LVGL, respectively.

In some embodiments, the first pull circuit 6 further comprises: a ninth transistor M12A and a tenth transistor M13A. A control electrode of the ninth transistor M12A is connected to the second node PD1, a first electrode thereof is connected to the second signal output terminal OUT _ C, a second electrode thereof is connected to the second fixed voltage terminal LVGL, a control electrode of the tenth transistor M13A is connected to the second node PD1, a first electrode thereof is connected to the first signal output terminal OUT, and a second electrode thereof is connected to the third fixed voltage terminal VGL.

In some embodiments, the first pull control circuit 5 includes: a fifth transistor M5A, a sixth transistor M6A, and a seventh transistor M7A. A control electrode and a first electrode of the fifth transistor M5A are connected to the first control terminal VDDo, and a second electrode thereof is connected to the second node PD 1. A control electrode of the sixth transistor M6A is connected to the first node PU, and a first electrode and a second electrode thereof are connected to the second node PD1 and the second fixed voltage terminal LVGL, respectively. A control electrode of the seventh transistor M7A is connected to the cascade signal INPUT terminal INPUT, and a first electrode and a second electrode thereof are connected to the second node PD1 and the second fixed voltage terminal LVGL, respectively.

In the circuit diagram shown in fig. 3, the fifth transistor M5A is used to set the second node PD1 high under the control of the first control terminal VDDo. The sixth transistor M6A is used to put the second node low under the control of the first node PU. The seventh transistor M7A is used to set the second node low under the control of the cascade signal INPUT.

In some embodiments, the shift register cell further comprises: a second pull control circuit 7 and a second pull circuit 8, the second pull control circuit 7 being configured to control the voltage of the third node PD2, the second pull circuit 8 being configured to set the voltage of the first node PU to an inactive voltage under the control of the voltage of the third node PD 2.

As such, the voltages of the second node PD1 and the third node PD2 may be alternately set to an effective voltage, thereby preventing fatigue of the associated transistors.

The second pull circuit 8 includes: a fourteenth transistor M8B. The fourteenth transistor M8B is a dual-gate transistor, and has a first gate connected to the third node PD2, a second gate connected to the first fixed voltage terminal VDDN, and a first and second gates connected to the first node PU and the second fixed voltage terminal LVGL, respectively.

In some embodiments, the second pull circuit 8 further comprises: a fifteenth transistor M12B and a sixteenth transistor M13B, wherein a control electrode of the fifteenth transistor M12B is connected to the third node PD2, a first electrode thereof is connected to the second signal output terminal OUT _ C, a second electrode thereof is connected to the second fixed voltage terminal LVGL, and a control electrode of the sixteenth transistor M13B is connected to the third node PD2, a first electrode thereof is connected to the first signal output terminal OUT, and a second electrode thereof is connected to the third fixed voltage terminal VGL.

In some embodiments, the second pull control circuit 7 includes: an eleventh transistor M5B, a twelfth transistor M6B, and a thirteenth transistor M7B. The eleventh transistor M5B has a control electrode and a first electrode connected to the second control terminal VDDe, and a second electrode connected to the third node PD 2. A control electrode of the twelfth transistor M6B is connected to the first node PU, a first electrode thereof is connected to the third node PD2, and a second electrode thereof is connected to the first fixed voltage terminal VDDN. The thirteenth transistor M7B has a control electrode connected to the cascade signal INPUT terminal INPUT, a first electrode connected to the third node PD2, and a second electrode connected to the first fixed voltage terminal VDDN.

In some embodiments, the shift register cell further comprises: and a bootstrap capacitor C1 connected between the first node PU and the first signal output terminal OUT.

Fig. 4 is a waveform diagram of the first node PU and the first signal output terminal OUT obtained by driving the shift register unit shown in fig. 3. No matter the operating frequency of the shift register unit is 60Hz, 30Hz or 10Hz (at this time, the time that the first node PU is maintained at a high level is longest, and the time that the electric charge of the first node PU leaks along the double-gate transistor connected to the first node PU is also longest), the leakage current of the first node PU can be effectively suppressed, and the effective voltage of the first node PU is kept at a stable high-level voltage, so that the first output transistor M3 can keep a good conduction state in a conduction stage, and further, the falling edge of the first signal output end OUT is ensured to be steep.

The embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of cascaded shift register units, and at least one shift register unit in the plurality of shift register units is the shift register unit.

Embodiments of the present disclosure also provide a display substrate including the gate driving circuit of the foregoing embodiments. The display substrate is, for example, a liquid crystal display substrate or a light emitting diode display substrate. The light emitting diode display substrate is, for example, an organic light emitting diode display substrate or a micro light emitting diode display substrate.

The embodiment of the present disclosure further provides a display device, and the display substrate is provided. The display device is any component or product with a display function. The display device is, for example, a display panel, a display module, a mobile phone, a tablet computer, a display, an electronic billboard, a vehicle-mounted navigator, a ground display screen, etc.

The embodiments in the disclosure are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments.

The scope of the present disclosure is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present disclosure by those skilled in the art without departing from the scope and spirit of the present disclosure. It is intended that the present disclosure also cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A shift register cell, comprising: an output circuit (2) configured to pass a clock signal provided by a clock signal terminal (CLK) at least to a first signal output terminal (OUT) under control of a voltage of a first node (PU);

the shift register unit further comprises a plurality of transistors of which the first electrodes or the second electrodes are connected with the first node (PU), at least one transistor in the plurality of transistors is a double-gate transistor, the first control electrode of the transistor is used for controlling the on-off state of the transistor, and the second control electrode of the transistor is connected with the fixed voltage end to receive a fixed voltage signal, so that the leakage current of the transistor in the off state is restrained.

2. The shift register unit according to claim 1, wherein the shift register unit comprises: a first transistor (M1), the first transistor (M1) being a double gate transistor, a first control electrode and a first electrode of the first transistor (M1) being connected to the cascade signal INPUT (INPUT), a second electrode thereof being connected to the first node (PU), and a second control electrode thereof being connected to the first fixed voltage terminal (VDDN).

3. The shift register unit according to claim 1, wherein the shift register unit comprises: a second transistor (M2), the second transistor (M2) being a double gate type transistor having a first control electrode connected to a first RESET signal terminal (RESET), a second control electrode connected to a first fixed voltage terminal (VDDN), and a first electrode and a second electrode connected to the first node (PU) and the second fixed voltage terminal (LVGL), respectively.

4. The shift register cell of claim 3, further comprising: a third transistor (M4) having a control electrode connected to the first RESET signal terminal (RESET), and a first electrode and a second electrode connected to the first signal output terminal (OUT) and the second fixed voltage terminal (LVGL), respectively.

5. The shift register cell of claim 1, further comprising: a fourth transistor (M15), the fourth transistor (M15) being a double gate type transistor having a first gate connected to the second RESET signal terminal (T _ RESET), a second gate connected to the first fixed voltage terminal (VDDN), and first and second gates connected to the first node (PU) and the second fixed voltage terminal (LVGL), respectively.

6. The shift register cell of claim 1, further comprising: a first pull control circuit (5) and a first pull circuit (6), the first pull control circuit (5) for controlling the voltage of a second node (PD1), the first pull circuit (6) for setting the voltage of the first node (PU) to an inactive voltage under the control of the voltage of the second node (PD 1);

the first pull circuit (6) comprises: an eighth transistor (M8A), the eighth transistor (M8A) being a double-gate transistor, a first control electrode of which is connected to the second node (PD1), a second control electrode of which is connected to the first fixed voltage terminal (VDDN), and a first electrode and a second electrode of which are connected to the first node (PU) and the second fixed voltage terminal (LVGL), respectively.

7. The shift register cell of claim 6,

the output circuit (2) includes: a first output transistor (M3) and a second output transistor (M11);

a control electrode of the first output transistor (M3) is connected to the first node (PU), a first electrode thereof is connected to the clock signal terminal (CLK), and a second electrode thereof is connected to the first signal output terminal (OUT);

a control electrode of the second output transistor (M11) is connected to the first node (PU), a first electrode thereof is connected to the clock signal terminal (CLK), and a second electrode thereof is connected to a second signal output terminal (OUT _ C);

the first pull circuit (6) further comprises: a ninth transistor (M12A) and a tenth transistor (M13A);

a control electrode of the ninth transistor (M12A) is connected to the second node (PD1), a first electrode thereof is connected to the second signal output terminal (OUT _ C), and a second electrode thereof is connected to a second fixed voltage terminal (LVGL);

a control electrode of the tenth transistor (M13A) is connected to the second node (PD1), a first electrode thereof is connected to the first signal output terminal (OUT), and a second electrode thereof is connected to a third fixed voltage terminal (VGL).

8. The shift register cell according to claim 7, wherein the first pull control circuit (5) comprises: a fifth transistor (M5A), a sixth transistor (M6A), and a seventh transistor (M7A);

a control electrode and a first electrode of the fifth transistor (M5A) are connected to a first control terminal (VDDo), and a second electrode thereof is connected to the second node (PD 1);

a control electrode of the sixth transistor (M6A) is connected to the first node (PU), and a first electrode and a second electrode thereof are connected to the second node (PD1) and a second fixed voltage terminal (LVGL), respectively;

a control electrode of the seventh transistor (M7A) is connected to a cascade signal INPUT terminal (INPUT), and a first electrode and a second electrode thereof are connected to the second node (PD1) and the second fixed voltage terminal (LVGL), respectively.

9. The shift register cell of claim 6, further comprising: a second pull control circuit (7) and a second pull circuit (8), the second pull control circuit (7) for controlling a voltage of a third node (PD2), the second pull circuit (8) for setting a voltage of the first node (PU) to an inactive voltage under control of a voltage of the third node (PD 2);

the second pull circuit (8) comprises: a fourteenth transistor (M8B), the fourteenth transistor (M8B) being a double gate type transistor, having a first gate connected to the third node (PD2), a second gate connected to the first fixed voltage terminal (VDDN), and first and second gates connected to the first node (PU) and the second fixed voltage terminal (LVGL), respectively.

10. The shift register cell according to claim 9, wherein the second pull circuit (8) further comprises: a fifteenth transistor (M12B) and a sixteenth transistor (M13B), a control electrode of the fifteenth transistor (M12B) is connected to the third node (PD2), a first electrode thereof is connected to the second signal output terminal (OUT _ C), a second electrode thereof is connected to the second fixed voltage terminal (LVGL), a control electrode of the sixteenth transistor (M13B) is connected to the third node (PD2), a first electrode thereof is connected to the first signal output terminal (OUT), and a second electrode thereof is connected to the third fixed voltage terminal (VGL).

11. The shift register cell according to claim 9, wherein the second pull control circuit (7) comprises: an eleventh transistor (M5B), a twelfth transistor (M6B), and a thirteenth transistor (M7B);

a control electrode and a first electrode of the eleventh transistor (M5B) are connected to a second control terminal (VDDe), and a second electrode thereof is connected to the third node (PD 2);

a control electrode of the twelfth transistor (M6B) is connected to the first node (PU), a first electrode thereof is connected to the third node (PD2), and a second electrode thereof is connected to the first fixed voltage terminal (VDDN);

a control electrode of the thirteenth transistor (M7B) is connected to a cascade signal INPUT terminal (INPUT), a first electrode thereof is connected to the third node (PD2), and a second electrode thereof is connected to the first fixed voltage terminal (VDDN).

12. The shift register cell of claim 1, further comprising: a bootstrap capacitor (C1) connected between the first node (PU) and the first signal output terminal (OUT).

13. The shift register unit according to claim 1, wherein the fixed voltage terminal provides a negative fixed voltage to increase a threshold voltage of the dual-gate transistor whose own second control gate is connected to the fixed voltage terminal, wherein the dual-gate transistor whose own second control gate is connected to the fixed voltage terminal is an N-type transistor;

14. A gate driver circuit comprising a cascade of a plurality of shift register cells, at least one of the plurality of shift register cells being a shift register cell according to any one of claims 1 to 13.

15. A display substrate comprising the gate driver circuit according to claim 14.

16. A display device comprising the display substrate according to claim 15.