CN114721908B

CN114721908B - On-chip power consumption control circuit, chip and power consumption control method

Info

Publication number: CN114721908B
Application number: CN202210375316.3A
Authority: CN
Inventors: 刘贤华
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2022-04-11
Filing date: 2022-04-11
Publication date: 2022-12-06
Anticipated expiration: 2042-04-11
Also published as: CN114721908A; CN115658440A; CN115658440B

Abstract

The present disclosure provides an on-chip power consumption control circuit, including: a voltage control signal generation circuit configured to: generating a PWM signal and PWM information in response to the received PWM control information; a clock signal generation circuit configured to: generating a clock signal and frequency information in response to the received frequency control information; a control information generation circuit configured to: the PWM control information and the frequency control information are updated in response to the received PWM information, the frequency information, and at least one signal inversion ratio. In addition, the disclosure also provides a chip comprising the on-chip power consumption control circuit and a power consumption control method applicable to the on-chip power consumption control circuit.

Description

On-chip power consumption control circuit, chip and power consumption control method

Technical Field

The present disclosure relates to the field of electrical technologies, and in particular, to an on-chip power consumption control circuit, and also to a chip including the on-chip power consumption control circuit and a power consumption control method applicable to the on-chip power consumption control circuit.

Background

With the development of electronic technology, whether data centers, workstations, or personal computers or mobile computing devices, power consumption management of chips such as GPUs/CPUs has always been an important aspect of product design that needs to be continuously perfected and improved. In general, the power consumption of an electronic system is directly related to the operating Voltage and clock Frequency of its main functional modules, and thus Dynamic Voltage and Frequency Scaling (DVFS) is a main approach for system-level power consumption management. The DVFS is basically designed in such a way that the working voltage and the clock frequency of a chip are dynamically adjusted according to the calculation requirements of an application program, the voltage and the clock frequency are increased when the calculation load is large and high performance is required, so that the performance is ensured to be met, and the voltage and the clock frequency are reduced to the maximum extent when the calculation load is small and high performance is not required, so that the power consumption is reduced, and therefore, the purpose of saving the power consumption as much as possible while ensuring the system performance can be achieved.

However, for the existing power consumption control system, on one hand, it mainly relies on software to perform control (e.g. calculation of relevant control values, etc.), while there is a certain execution delay in executing software instructions, and on the other hand, it may include multiple links with high delay, such as power consumption detection, power consumption comparison, etc. Therefore, the existing power consumption control system cannot enable the power consumption control to quickly approach the power consumption target, so that the power consumption control on the actual system often oscillates, and the performance of the system is not stable enough.

Disclosure of Invention

According to a first aspect of the present disclosure, there is provided an on-chip power consumption control circuit including: a voltage control signal generation circuit configured to: generating a PWM signal and PWM information in response to the received PWM control information; a clock signal generation circuit configured to: generating a clock signal and frequency information in response to the received frequency control information; a control information generation circuit configured to: updating the PWM control information and the frequency control information in response to the received PWM information, the frequency information, and at least one signal inversion ratio.

According to some exemplary embodiments, the control information generation circuit further receives a temperature measurement and is configured to: updating the PWM control information and the frequency control information in response to the received PWM information, the frequency information, the temperature measurement, and at least one signal turnover ratio.

According to some exemplary embodiments, the control information generating circuit includes: a state information update circuit configured to: generating a current voltage value, a current frequency value, and a current temperature value in response to the received PWM information, the frequency information, and the temperature measurement value; a power consumption calculation circuit configured to: calculating a current power consumption estimate in response to the received current voltage value, the current frequency value, the current temperature value, and the at least one signal rollover ratio; a voltage frequency calculation circuit configured to: generating a voltage frequency control value in response to the received current power consumption estimate value; a voltage frequency coordination control circuit configured to: updating the PWM control information and the frequency control information in response to the received voltage frequency control value.

According to some exemplary embodiments, the state information updating circuit includes: a voltage value update circuit configured to: generating the current voltage value in response to the received PWM information; a frequency value update circuit configured to: generating the current frequency value in response to the received frequency information; a temperature value update circuit configured to: generating the current temperature value in response to the temperature measurement.

According to some exemplary embodiments, the voltage value update circuit includes: a PWM information delay circuit configured to: generating time-delay PWM information in response to the received PWM information; a voltage lookup table circuit configured to: and responding to the received time delay PWM information, and looking up a table to generate the current voltage value.

According to some exemplary embodiments, the delay time of the PWM information delay circuit is dynamically adjustable based on the PWM information.

According to some exemplary embodiments, the PWM information delay circuit includes: a first register configured to: generating previous PWM information in response to the received PWM information; a first subtractor configured to: generating a PWM information difference value based on the PWM information and the previous PWM information; a first multiplier configured to: and multiplying the PWM information difference value by a PWM information difference value adjusting coefficient to generate a delay time value. A first delayer configured to: delaying the PWM information in response to the received PWM information and the delay time value to generate the delayed PWM information.

According to some exemplary embodiments, the previous PWM information is previous PWM information.

According to some exemplary embodiments, the frequency value updating circuit includes: a second delayer configured to: generating delayed frequency information in response to the received frequency information; a frequency lookup table circuit configured to: and responding to the received delay frequency information, and looking up a table to generate the current frequency value.

According to some exemplary embodiments, a delay time of the second delay is configurable.

According to some exemplary embodiments, the temperature value updating circuit includes: a second multiplier configured to: multiplying the temperature measurement value by a first temperature value adjusting coefficient, and outputting an operation result; a first adder configured to: and adding a second temperature value adjusting coefficient to the operation result of the second multiplier to generate the current temperature value.

According to some exemplary embodiments, the temperature value update circuit comprises a temperature look-up table circuit configured to: in response to receiving the temperature measurement, a table lookup generates the current temperature value.

According to some exemplary embodiments, the power consumption calculation circuit includes: an overall signal inversion ratio calculation circuit configured to: generating an overall signal rollover ratio based on the received at least one signal rollover ratio; a current power consumption estimation circuit configured to: generating the current power consumption estimate based on the received overall signal turnover ratio, the current voltage value, the current frequency value, and the current temperature value.

According to some exemplary embodiments, the overall signal inversion ratio calculation circuit includes: at least one multiplier in one-to-one correspondence with the at least one signal inversion ratio, wherein each of the at least one multiplier is configured to multiply the corresponding signal inversion ratio by a corresponding signal inversion ratio adjustment coefficient and output an operation result; a second adder configured to: summing the operation results of the at least one multiplier and outputting the operation results; a second register configured to: saving the received operation result of the second adder, and outputting the operation result of the second adder as the overall signal inversion ratio.

According to some exemplary embodiments, the current power consumption estimation circuit comprises: a third multiplier configured to: multiplying the current temperature value by a first power consumption calculation coefficient, and outputting an operation result; a third adder configured to: adding 1 to the operation result of the third multiplier and outputting the operation result; a fourth multiplier configured to: multiplying an operation result of the third adder by a second power consumption calculation coefficient, and outputting the operation result; a fifth multiplier configured to: multiplying the overall signal turnover ratio by the current voltage value and outputting an operation result; a sixth multiplier configured to: multiplying the current frequency value by a third power consumption calculation coefficient, and outputting an operation result; a seventh multiplier configured to: multiplying the operation result of the fifth multiplier by the operation result of the sixth multiplier, and outputting the operation result; a fourth adder configured to: summing the operation result of the fourth multiplier and the operation result of the seventh multiplier, and outputting the operation result; an eighth multiplier configured to: multiplying the operation result of the fourth adder by the current voltage value, and outputting an operation result; a third register configured to: saving the received operation result of the eighth multiplier, and outputting the operation result of the eighth multiplier as the current power consumption estimation value.

According to some exemplary embodiments, the voltage frequency calculation circuit includes: a first selector configured to: responding to the received mode information, and selecting one of the received current power consumption estimated value and a preset bypass mode power consumption estimated value to be output as a power consumption input value; a voltage frequency control value look-up table circuit configured to: responding to the received voltage frequency calculation value, and looking up a table to generate the voltage frequency control value; an arithmetic circuit configured to: generating a first operation result and a second operation result in response to the received power consumption input value and the voltage frequency calculation value; a first comparator configured to: responsive to the received power consumption input value being greater than or equal to a first power consumption threshold, asserting an output first power consumption superstandard signal; and, in response to the received power consumption input value being less than a first power consumption threshold, invalidating the first power consumption superstandard signal; a second comparator configured to: responsive to the received power consumption input value being greater than or equal to a second power consumption threshold, asserting an output second power consumption superstandard signal; and, in response to the received power consumption input value being less than a second power consumption threshold, invalidating the second power consumption superstandard signal; a second selector configured to: the method comprises the steps of responding to the fact that a received first power consumption exceeding signal is effective, selecting a preset operation result to be output as the voltage frequency calculation value, responding to the fact that only a received second power consumption exceeding signal is effective, selecting the received second operation result to be output as the voltage-frequency calculation value, and responding to the fact that the first power consumption exceeding signal and the second power consumption exceeding signal are both ineffective, selecting the received first operation result to be output as the voltage frequency calculation value.

According to some exemplary embodiments, the arithmetic circuit includes: a second subtractor configured to: generating a power consumption difference value between the received power consumption input value and a preset target power consumption value, and outputting the power consumption difference value; a ninth multiplier configured to: multiplying the received power consumption difference value by a first calculation coefficient, and outputting an operation result; a fourth register configured to: generating a previous power consumption difference value in response to the received power consumption difference value; a tenth multiplier configured to: multiplying the received previous power consumption difference value by a second calculation coefficient, and outputting an operation result; a fifth register configured to: generating a previous power consumption difference value in response to the received previous power consumption difference value; an eleventh multiplier configured to: multiplying the received power consumption difference values of the first two times by a third calculation coefficient, and outputting a calculation result; a sixth register configured to: generating a previous voltage frequency calculation value in response to the received voltage frequency calculation value; a twelfth multiplier configured to: multiplying the received previous voltage frequency calculation value by a first feedback coefficient, and outputting an operation result; a seventh register configured to: generating first two voltage frequency calculated values in response to the received first voltage frequency calculated value; a thirteenth multiplier configured to: multiplying the received first twice voltage frequency calculation value by the second feedback coefficient, and outputting an operation result; a fifth adder configured to: summing an operation result of the ninth multiplier, an operation result of the tenth multiplier, an operation result of the eleventh multiplier, an operation result of the twelfth multiplier, and an operation result of the thirteenth multiplier to generate the first operation result; and a shifter configured to shift the first operation result to the right in response to the received first operation result to generate the second operation result.

According to some exemplary embodiments, the voltage frequency coordination control circuit includes: a voltage frequency valuator circuit configured to: generating a current voltage control value and a current frequency control value in response to the received voltage frequency control value; a third delayer configured to: generating a delayed voltage control value in response to the received current voltage control value; an eighth register configured to: generating previous voltage control value information in response to the received PWM control information; a third comparator configured to: responsive to the received current voltage control value being greater than or equal to the received previous voltage control value, asserting an output first conditional signal, and responsive to the received current voltage control value being less than the received previous voltage control value, deasserting the output first conditional signal; a third selector configured to: outputting the received current voltage control value as the PWM control information in response to the received first condition signal being valid, and outputting the received delay voltage control value as the PWM control information in response to the received first condition signal being invalid; a fourth comparator configured to: asserting an output second condition signal in response to the received current voltage control value being less than or equal to the received previous voltage control value, and de-asserting the output second condition signal in response to the received current voltage control value being greater than the received previous voltage control value; a ninth register configured to: generating a previous frequency control value in response to the received current frequency control value; a fifth comparator configured to: asserting an output third conditional signal in response to the received current frequency control value being less than or equal to the received previous frequency control value, and de-asserting the output third conditional signal in response to the received current frequency control value being greater than the received previous frequency control value; an OR gate configured to: generating a fourth conditional signal in response to receiving the second conditional signal and the third conditional signal; a fourth delayer configured to: generating a delayed frequency control value in response to the received current frequency control value; a fourth selector configured to: outputting the received current frequency control value as the frequency control information in response to the received fourth condition signal being valid, and outputting the received delayed frequency control value as the PWM control information in response to the received fourth condition signal being invalid.

According to some exemplary embodiments, the delay times of the third and fourth delays are configurable.

According to some exemplary embodiments, the voltage control signal generating circuit includes: a fifth selector configured to: selecting one output from the received PWM control information and preset bypass mode PWM control information in response to a received mode signal, and generating the PWM information; a PWM signal generator configured to: generating the PWM signal in response to an output of the fifth selector.

According to some exemplary embodiments, the clock signal generating circuit includes: a sixth selector configured to: selecting one output from the received frequency control information and preset bypass mode frequency control information in response to a received mode signal to generate the frequency information; a frequency information valuating circuit configured to: generating a first control value and a second control value in response to an output of the sixth selector; a phase locked loop configured to generate an original clock signal; a frequency divider configured to: dividing the original clock signal in response to the received first control value to generate a divided clock signal; a gating circuit configured to: generating a gating signal in response to the received second control value and the divided clock signal; an AND gate circuit configured to: generating the clock signal in response to the received gating signal and the divided clock signal.

According to some exemplary embodiments, the clock signal generation circuit is configured to cause the frequency of the clock signal to be:

wherein, F _clock Is the frequency of said clock signal, F _VCO Is the frequency of the original clock signal, freq _ n is the first control value, freq _ i is the second control value, and M is a preset gating adjustment parameter, wherein freq _ n, freq _ i, and M are all integers greater than 0, and freq _ i is less than M.

According to a second aspect of the present disclosure, there is provided a chip comprising at least one on-chip power consumption control circuit according to exemplary embodiments of the first aspect of the present disclosure.

According to some exemplary embodiments, the chip is a GPU chip.

According to a third aspect of the present disclosure, there is provided a power consumption control method applied to an on-chip power consumption control circuit according to exemplary embodiments of the first aspect of the present disclosure, the power consumption control method including: generating a PWM signal and PWM information based on the received PWM control information; generating a clock signal and frequency information based on the received frequency control information; obtaining at least one signal turn-over ratio; updating the PWM control information and the frequency control information based on the PWM information, the frequency information, and the at least one signal inversion ratio.

The on-chip power consumption control circuit provided by the disclosure is completely realized in the chip in a configurable hardware circuit mode, low-speed off-chip communication and analog-to-digital conversion links in the traditional technical scheme are eliminated, and a fast and fine closed-loop control loop is realized on the chip, so that the update cycle of the state of the control system can be microsecond magnitude or even below. Whereas conventional-level control systems rely on-board feedback loops and software-based control, the control period is often on the order of milliseconds. Therefore, the real-time performance of the on-chip power consumption control circuit provided by the disclosure is obviously improved, so that the power consumption control performance is also obviously improved, and the cost of an off-chip power consumption detection chip is also saved.

According to the clock signal generation circuit of the on-chip power consumption control circuit provided by the disclosure, the switching of the clock frequency can be completed within several clock cycles based on a mode of combining dynamic clock frequency division and clock pulse gating. According to the clock signal generating circuit provided by the disclosure, compared with the traditional phase-locked loop regulation, the dynamic regulation is quicker, compared with the method of layering a plurality of frequency dividers, the clock control is finer, and the structure is simpler and the cost is lower. Therefore, the clock signal generation circuit provided according to the present disclosure facilitates faster and more accurate adjustment to an optimal power consumption state by accomplishing smooth transitions of power supply and clock curves through fast and fine control.

A plurality of hardware links of the on-chip power consumption control circuit provided according to the present disclosure are either parameter configurable or look-up table configurable, thereby providing an interface for offline parameter training and adjustment. Moreover, each hardware link supports a bypass mode, so that development and debugging can be performed in a software mode.

In addition, the on-chip power consumption control circuit provided by the disclosure can take a power consumption value as a control target, thereby supporting power consumption capping in a maximum performance mode, simultaneously supporting dynamic power consumption control in a passive and active prediction mode in a non-maximum performance mode, and also considering fine adjustment driven by a timing event and emergency control of an abnormal event.

Drawings

So that the manner in which the above recited features, characteristics and advantages of the present disclosure can be understood in detail, a more particular description of embodiments of the present disclosure, briefly summarized above, may be had by reference to the appended drawings, in which; in the drawings:

fig. 1 schematically shows, in block diagram form, the structure of a power consumption control system for a GPU chip in the related art;

figure 2a schematically illustrates, in block diagram form, the structure of an on-chip power consumption control circuit according to some exemplary embodiments of the present disclosure;

FIG. 2b schematically illustrates, in block diagram form, the structure of an on-chip power consumption control circuit in accordance with further exemplary embodiments of the present disclosure;

fig. 3 schematically shows in block diagram form the structure of a control information generation circuit in the on-chip power consumption control circuit shown in fig. 2 a;

fig. 4 schematically shows, in block diagram form, the structure of a state information updating circuit in the control information generating circuit shown in fig. 3;

fig. 5 schematically shows the structure of the PWM information delay circuit in the voltage value update circuit shown in fig. 4;

fig. 6 schematically shows, in block diagram form, the structure of a power consumption calculation circuit in the control information generation circuit shown in fig. 3;

fig. 7 schematically shows the structure of an overall signal inversion ratio calculation circuit in the power consumption calculation circuit shown in fig. 6;

fig. 8 schematically shows the structure of a current power consumption estimation circuit in the power consumption calculation circuit shown in fig. 6;

fig. 9 schematically shows, in block diagram form, the structure of a voltage frequency calculation circuit in the control information generation circuit shown in fig. 3;

fig. 10 schematically shows the structure of an arithmetic circuit in the voltage frequency calculation circuit shown in fig. 9;

fig. 11 schematically shows the structure of a voltage-frequency coordination control circuit in the control information generation circuit shown in fig. 3;

fig. 12 schematically shows the structure of a voltage frequency dereferencing circuit in the voltage frequency coordination control circuit shown in fig. 11;

fig. 13 schematically shows the structure of a voltage control signal generation circuit in the on-chip power consumption control circuit shown in fig. 2a and 2 b;

fig. 14 schematically shows a structure of a clock signal generation circuit in the on-chip power consumption control circuit shown in fig. 2a and 2 b;

FIG. 15 schematically shows the timing of part of signals in the clock signal generation circuit shown in FIG. 14;

FIG. 16 schematically illustrates, in block diagram form, the structure of a chip in accordance with some exemplary embodiments of the present disclosure;

fig. 17 schematically illustrates, in flow chart form, a power consumption control method in accordance with some exemplary embodiments of the present disclosure.

It is to be understood that the matter shown in the figures is merely schematic and thus it is not necessarily drawn to scale. Further, throughout the drawings, the same or similar features are indicated by the same or similar reference numerals.

Detailed Description

The following description provides specific details of various exemplary embodiments of the present disclosure so that those skilled in the art can fully understand and implement the technical solutions according to the present disclosure.

First, some terms involved in the embodiments of the present disclosure are explained to facilitate understanding by those skilled in the art:

system-on-a-chip (SOC): refers to the integration of a complete system on a single chip. A complete SOC typically includes a chip core (e.g., a Central Processing Unit (CPU)), memory, and peripheral circuits, among others. Due to unprecedented high-efficiency integration performance, SOC is a major solution to replace integrated circuits and has become a necessary trend for current microelectronic chip development.

Signal inversion ratio: and in a time period with a certain time length, the ratio of the time length of the signal inversion to the time length of the time period. In the chip, the power consumption of each functional block may be estimated based on a signal inversion ratio of a signal at each functional block. In general, the higher the signal inversion ratio, the greater the power consumption of the functional block, and the lower the signal inversion ratio, the less the power consumption of the functional block. As an example, the signal inversion ratio of a signal can be calculated by the following formula:

formula 1

In the above equation, act is the signal inversion ratio, T is the total duration of the time period for determining the signal inversion ratio, T is the duration of one inversion cycle of the signal in which inversion occurs, and n is the number of inversion cycles in which inversion occurs.

Referring to fig. 1, a structure of a power consumption control system for a GPU chip in the related art is schematically shown in a block diagram. As shown in fig. 1, the power consumption control system 100 includes a GPU chip 110, a voltage detection chip 120, a power control chip 130, and a precision resistor 140. The GPU chip 110 includes a GPU core 111, a clock generator 112, a Micro Control Unit (MCU) 113, an I2C interface 114, and a Pulse Width Modulation (PWM) generator 115. The power control chip 130 receives the PWM signal from the PWM generator 115 and generates a core voltage to be supplied to the GPU core 111 based on the PWM signal. The clock generator 112 generates a clock signal having a specific clock frequency and supplies the clock signal to the GPU core 111. The voltage detection chip 120 may measure the potential across the precision resistor 140, thereby measuring the core voltage and the corresponding current provided by the power control chip 130 to generate a voltage measurement value and a current measurement value. The MCU 113 runs power consumption control software to monitor the operating conditions of the GPU chip 110. The MCU 113 may communicate with the voltage detection chip 120 through the I2C interface 114 to obtain voltage and current measurements. Thus, the MCU 113 can calculate the current power consumption of the GPU chip 110 based on the acquired voltage measurement values and current measurement values. In order to make the current power consumption reach the preset power consumption, the MCU 113 may compare the current power consumption of the GPU chip 110 with the preset power consumption, based on a difference therebetween, the MCU 113 may calculate a core voltage and a clock frequency that need to be adjusted, and transmit corresponding voltage control signals and clock control signals to the PWM generator 115 and the clock generator 112, respectively. The PWM generator 115 regenerates the PWM signal based on the received voltage control signal and transmits it to the power control chip 130. Thus, the power control chip 130 may generate an updated core voltage and provide it to the GPU core 111. Further, the clock generator 112 may regenerate a clock signal having an updated clock frequency based on the received clock control signal and provide it to the GPU core 111.

However, the power consumption control system 100 is a control system using software master control, and the real-time performance and accuracy of system adjustment are not high. The high delay of the power consumption control system 100 may come from power consumption detection, power consumption comparison, control calculation, control delay and other links. For example, for the power consumption detection stage, the voltage detection chip 120 outside the chip needs to measure and perform analog-to-digital conversion on the potential at the precision resistor 140, and on the other hand, the MCU 113 needs to communicate with the voltage detection chip 120 through a slow interface (e.g., I2C interface 114) to obtain the measurement result. Both of these aspects result in a delay at the power consumption detection stage. In addition, the power consumption control software running on the MCU 113 needs to perform various power consumption-related calculations and perform corresponding controls, and the calculations and controls themselves are based on a certain time interval and there is a certain execution delay, and therefore, the time interval thereof is difficult to reduce. From the above analysis, the power consumption control system 100 may have the following problems: the power consumption control cannot quickly approach the power consumption target, so that the power consumption control on the actual system often oscillates, and the system performance is not stable enough. In addition, the voltage detection chip 120 may increase the cost of the power consumption control system 100 and may cause the structure of the power consumption control system 100 to become complicated.

Referring to fig. 2a, the structure of an on-chip power consumption control circuit according to some exemplary embodiments of the present disclosure is schematically illustrated in block diagram form. As shown in fig. 2a, the on-chip power consumption control circuit 200 includes a control information generation circuit 210, a voltage control signal generation circuit 220, and a clock signal generation circuit 230. The voltage control signal generation circuit 220 is configured to: in response to the received PWM control information PWM _ ctrl, a PWM signal PWM and PWM information PWM _ hw are generated. The PWM signals PWM are passed to the off-chip respective power chips to generate respective voltage signals that are provided to the chip cores. The PWM information PWM _ hw includes characteristic data related to the generated PWM signal PWM and is thus supplied as feedback information to the control information generating circuit 210. The clock signal generation circuit 230 is configured to: the clock signal core _ clock and the frequency information freq _ hw are generated in response to the received frequency control information freq _ ctrl. The clock signal core _ clock has a particular clock frequency and is passed to the chip core. Similarly, the frequency information freq _ hw includes characteristic data related to the generated clock signal core _ clock, and is also supplied to the control information generating circuit 210 as feedback information. The control information generation circuit 210 is configured to: the PWM control information PWM _ ctrl and the frequency control information freq _ ctrl are updated in response to the received PWM information PWM _ hw, the frequency information freq _ hw, the temperature measurement value temp, and the at least one signal inversion ratio act _1 to act _ i.

The components of the on-chip power consumption control circuit 200, i.e., the control information generation circuit 210, the voltage control signal generation circuit 220, and the clock signal generation circuit 230, are all implemented inside a chip in the form of hardware circuits, for example, may be implemented inside a corresponding GPU or CPU chip for controlling the power consumption of the chip. However, it should be understood that the on-chip power consumption control circuit 200 may also be implemented on any other suitable chip, and the disclosure is not limited thereto. As described above, the on-chip power consumption control circuit 200 acquires the corresponding feedback information (i.e., the PWM information PWM _ hw and the frequency information freq _ hw) at the generation links of the voltage control signal and the clock signal (i.e., the voltage control signal generation circuit 220 and the clock signal generation circuit 230), rather than supplying these feedback information to the control information generation circuit 210. Thus, the on-chip power consumption control circuit 200 can implement on-chip closed-loop control, thereby eliminating the need for off-chip low-speed links (e.g., voltage detection chip and analog-to-digital conversion link, etc.). Therefore, the on-chip power consumption control circuit 200 can complete the update of data and the calculation and update of each control information on the order of the system clock of the chip, thereby being able to greatly reduce the sampling and control period.

As described above, the power consumption control circuit 200 according to the present disclosure also receives the temperature measurement value temp and then uses this information to generate the PWM control information PWM _ ctrl and the frequency control information freq _ ctrl. Generally speaking, in the working process of the chip, compared with the voltage control signal and the clock signal, the change of the chip temperature is very slow, so that the dynamic power consumption of the chip is not significantly affected, and therefore, the sampling and control period of each control information is not delayed by the way of measuring the temperature value by the sensor in the on-chip power consumption control circuit 200. In contrast, the power consumption control circuit 200 can achieve more thorough consideration and more accurate control of the power consumption of the chip due to consideration of the temperature factor.

Referring to fig. 2b, structures of on-chip power consumption control circuits according to further exemplary embodiments of the present disclosure are schematically illustrated in block diagram form. As shown in fig. 2b, the on-chip power consumption control circuit 201 is different from the on-chip power consumption control circuit 200 shown in fig. 2a in that the control information generation circuit 210' in the on-chip power consumption control circuit 201 does not receive the temperature measurement value. As already mentioned above, the chip temperature changes very slowly compared to the voltage control signal and the clock signal, so that it does not have a significant impact on the dynamic power consumption of the chip, and therefore, in some application scenarios, the power consumption can be controlled considering only the changes of the voltage control signal and the clock signal, without considering the temperature impact. Thus, the structure of the on-chip power consumption control circuit 201 can be relatively simpler. The rest of the circuit structures and functions in the on-chip power consumption control circuit 201 are the same as those of the corresponding parts in the on-chip power consumption control circuit 200, and are not described herein again.

Referring to fig. 3, a structure of a control information generation circuit in the on-chip power consumption control circuit shown in fig. 2a is schematically shown in a block diagram form, according to some exemplary embodiments of the present disclosure. As shown in fig. 3, the control information generation circuit 210 includes a state information update circuit 211, a power consumption calculation circuit 212, a voltage frequency calculation circuit 213, and a voltage frequency coordination control circuit 214. The state information update circuit 211 is configured to: in response to the received PWM information PWM _ hw, frequency information freq _ hw and temperature measurement value temp, a current voltage value curr _ V, a current frequency value curr _ F and a current temperature value curr _ T are generated. The power consumption calculation circuit 212 is configured to: in response to the received current voltage value curr _ V, the current frequency value curr _ F, the current temperature value curr _ T, and the at least one signal turnover ratio act _1 to act _ i, a current power consumption estimate pwr _ hw is calculated. The voltage frequency calculation circuit 213 is configured to: in response to the received current power consumption estimate pwr _ hw, a voltage frequency control value vf _ ctrl is generated. A voltage frequency coordination control circuit 214 configured to: the PWM control information PWM _ ctrl and the frequency control information freq _ ctrl are updated in response to the received voltage frequency control value vf _ ctrl. Subsequently, as described above, the voltage control signal generation circuit 220 and the clock signal generation circuit 230 generate the PWM signal PWM and PWM information PWM _ hw based on the updated PWM control information PWM _ ctrl and generate the clock signal core _ clock and frequency information freq _ hw based on the updated frequency control information freq _ ctrl, respectively.

It should be understood that the structure of the control information generation circuit shown in fig. 3 is merely an exemplary circuit provided according to some exemplary embodiments of the present disclosure, and does not limit the present disclosure thereto. The following description will be made separately for each circuit shown in fig. 3.

Referring to fig. 4, a structure of a state information updating circuit in the control information generating circuit shown in fig. 3 is schematically shown in a block diagram form according to some exemplary embodiments of the present disclosure. As shown in fig. 4, the state information updating circuit 211 includes a voltage value updating circuit 211a, a frequency value updating circuit 211b, and a temperature value updating circuit 211c. The voltage value update circuit 211a is configured to: in response to the received PWM information PWM _ hw, a current voltage value curr _ V is generated. The frequency value updating circuit 211b is configured to: in response to the received frequency information freq _ hw, a current frequency value curr _ F is generated. Temperature value update circuit 211c is configured to: in response to the temperature measurement temp, a current temperature value curr _ T is generated.

With continued reference to FIG. 4, the voltage value update circuit 211a further includes a PWM information delay circuit 211-1 and a voltage lookup table circuit 211-2. The PWM information delay circuit 211-1 is configured to: in response to the received PWM information PWM _ hw, delayed PWM information PWM _ de is generated. The voltage lookup table circuit 211-2 is configured to: and responding to the received time delay PWM information PWM _ de, and looking up a table to generate a current voltage value curr _ V. It should be understood that the reason for performing the delay operation on the received PWM information PWM _ hw is that the off-chip power supply chip needs a certain time to generate and provide the corresponding voltage signal to the chip after receiving the PWM signal, so if the received PWM information PWM _ hw is not delayed, the current voltage value curr _ V determined by the voltage value updating circuit 211a may not accurately reflect the voltage currently applied to the chip. Therefore, in order to make the current voltage value curr _ V determined by the voltage value updating circuit 211a accurately reflect the voltage currently applied to the chip, a corresponding delay operation needs to be performed on the received PWM information PWM _ hw. Furthermore, according to some exemplary embodiments of the present disclosure, the delay time of the PWM information delay circuit 211-1 performing the delay operation on the received PWM information PWM _ hw may be dynamically adjustable based on the received PWM information PWM _ hw. Furthermore, according to other exemplary embodiments of the present disclosure, the voltage value updating circuit may perform a corresponding calculation on the delayed PWM information to determine the current voltage value, so that a lookup table circuit may not be required.

Referring to fig. 5, a structure of a PWM information delay circuit in the voltage value update circuit shown in fig. 4 is schematically shown, according to some exemplary embodiments of the present disclosure. As shown in fig. 5, the PWM information delay circuit 211-1 includes a first register 211-11, a first subtractor 211-12, a first multiplier 211-13, and a first delay 211-14. The first register 211-11 is configured to: in response to the received PWM information PWM _ hw, previous PWM information PWM _ old is generated. The first subtractor 211-12 is configured to: based on the PWM information PWM _ hw and the previous PWM information PWM _ old, a PWM information difference value is generated. The first multiplier 211-13 is configured to: and multiplying the PWM information difference value by a PWM information difference value adjusting coefficient d0 to generate a delay time value. The first delayer 211-14 is configured to: the PWM information PWM _ hw is delayed in response to the received PWM information PWM _ hw and the delay time value to generate delayed PWM information PWM _ de. It can be seen that the PWM information delay circuit 211-1 shown in fig. 5 can dynamically adjust the delay time value of the first delay circuit 211-14 based on the difference between the PWM information PWM _ hw and the previous PWM information PWM _ old, thereby enabling the current voltage value curr _ V determined by the voltage value update circuit 211a to more accurately reflect the current voltage applied to the chip. Further, the PWM information difference adjustment coefficient d0 may be determined based on experience or experimental data, and can be set in advance by software.

It is to be understood that in the context of the present disclosure, delaying a signal or information means delaying the signal or information by one or more clock pulses within one control period, whereas a term such as "previous" means that the corresponding information or data is temporally information or data in a control period preceding the current control period. Thus, in the present disclosure, "delayed" and "previous" have different meanings and correspond to different operations, e.g., delayed operations may be implemented using a delayer, while previous information is typically generated using a register. It should also be understood that the term "previous" may include a variety of situations, and specifically, the previous information refers to information in one control period located before and immediately adjacent to the current control period, and the previous information refers to a second control period located before and immediately before the current control period. For example, if T (n) represents the current control period, then T (n-1) represents the previous control period, T (n-2) represents the previous two control periods, and so on. Therefore, in the PWM information delay circuit 211-1 shown in fig. 5, the previous PWM information PWM _ old represents the PWM information of the PWM information PWM _ hw in the control period before the current control period, which may be the previous PWM information or the previous two PWM information. In some exemplary embodiments according to the present disclosure, the previous PWM information PWM _ old may refer to a previous PWM information. Also, as a non-limiting example, the First register 211-11 may be a First In First Out (FIFO) register, and thus, it may Output previous PWM information in response to the received PWM information in each control period.

Referring back to fig. 4, the frequency value updating circuit 211b includes a second delayer 211-3 and a frequency lookup table circuit 211-4. The second delayer 211-3 is configured to: in response to the received frequency information freq _ hw, delayed frequency information freq _ de is generated. The frequency lookup table circuit 211-4 is configured to: in response to the received delay frequency information freq _ de, a table is looked up to generate a current frequency value curr _ F. Similarly, the reason for performing the delay operation on the received frequency information freq _ hw is that the clock signal circuit 230 also needs a certain time to generate and provide the corresponding clock signal to the chip after receiving the frequency control information freq _ ctrl, so if the received frequency information freq _ hw is not delayed, the current frequency value curr _ F determined by the frequency value updating circuit 211b may not accurately reflect the frequency of the clock signal currently applied to the chip. Therefore, in order to enable the current frequency value curr _ F determined by the frequency value updating circuit 211b to accurately reflect the frequency of the clock signal currently applied to the chip, a corresponding delay operation needs to be performed on the received frequency information freq _ hw. In some exemplary embodiments of the present disclosure, the delay time of the second delayer 211-3 is configurable, which can be preset by software to facilitate debugging. According to other exemplary embodiments of the present disclosure, the frequency value updating circuit may perform corresponding calculations on the delayed frequency information to determine the current frequency value, such that a look-up table circuit may not be required.

The temperature value updating circuit 211c includes a second multiplier 211-5 and a first adder 211-6. The second multiplier 211-5 is configured to: and multiplying the temperature measurement value temp by a first temperature value adjustment coefficient t1, and outputting an operation result. First adder 211-6 is configured to: the operation result of the second multiplier 211-5 is added with the second temperature value adjustment coefficient T2 to generate the current temperature value curr _ T. It should be understood that the first temperature value adjustment coefficient t1 and the second temperature value adjustment coefficient t2 can be determined based on experience or experimental data, and can be preset by software to facilitate debugging. Further, according to still other exemplary embodiments of the present disclosure, the temperature value update circuit may include a temperature look-up table circuit configured to: in response to the received temperature measurement, a look-up table generates a current temperature value.

Referring to fig. 6, a structure of a power consumption calculation circuit in the control information generation circuit shown in fig. 3 is schematically shown in a block diagram form according to some exemplary embodiments of the present disclosure. As shown in fig. 6, the power consumption calculation circuit 212 includes an overall signal inversion ratio calculation circuit 212a and a current power consumption estimation circuit 212b. The overall signal inversion ratio calculation circuit 212a is configured to: based on the received at least one signal inversion ratio act _1 to act _ i, an overall signal inversion ratio alpha is generated. The current power consumption estimation circuit 212b is configured to: based on the received overall signal turnover ratio alpha, the current voltage value curr _ V, the current frequency value curr _ F and the current temperature value curr _ T, a current power consumption estimate pwr _ hw is determined. The signal inversion ratios act _1 to act _ i are signal inversion ratios of key signals at each functional module on the chip, which reflect the current operating condition of each functional module and thus can be used to determine the dynamic power consumption of the chip. The signal inversion ratios act _1 to act _ i may be periodically acquired from the respective functional modules by the corresponding acquisition circuits, or may be periodically provided by the respective functional modules. In some exemplary embodiments of the present disclosure, the overall signal turnover ratio calculation circuit 212a may perform a linear fit on the received at least one signal turnover ratio act _1 to act _ i to generate the overall signal turnover ratio alpha.

Referring to fig. 7, a structure of the overall signal inversion ratio calculation circuit shown in fig. 6 is schematically shown, according to some exemplary embodiments of the present disclosure. As shown in fig. 7, the overall signal inversion ratio calculation circuit 212a includes: at least one multiplier 212-01 to 212-0i, a second adder 212-1 and a second register 212-2. At least one multiplier 212-01 to 212-0i is in one-to-one correspondence with at least one signal inversion ratio act _1 to act _ i, and each multiplier is configured to multiply the corresponding signal inversion ratio by a corresponding signal inversion ratio adjustment coefficient and output an operation result. That is, at least one multiplier 212-01 to 212-0i is used to multiply at least one signal inversion ratio act _1 to act _ i with a corresponding one of at least one signal inversion ratio adjustment coefficient q1 to qi, respectively, and output the operation result. The second adder 212-1 is configured to: the operation results of at least one of the multipliers 212-01 to 212-0i are summed and the operation results are output. The second register 212-2 is configured to: the received operation result of the second adder 212-1 is saved and the operation result of the second adder 212-1 is output as the overall signal inversion ratio alpha. Thus, the process by which the exemplary overall signal inversion ratio calculation circuit 212a shown in fig. 7 linearly fits at least one of the signal inversion ratios act _1 to act _ i to generate the overall signal inversion ratio alpha may be represented by the following equation: alpha = q1 × act _1+ q2 × act _2+. + qi × act _ i. Further, it is also understood that the at least one signal turnover ratio adjustment coefficient q1 to qi may be determined based on empirical or experimental data and can be preset by software to facilitate debugging.

Referring to fig. 8, a structure of a current power consumption estimation circuit in the power consumption calculation circuit shown in fig. 6 is schematically shown, according to some exemplary embodiments of the present disclosure. As shown in fig. 8, the current power consumption estimation circuit 212b includes: a third multiplier 212-3, a third adder 212-4, a fourth multiplier 212-5, a fifth multiplier 212-7, a sixth multiplier 212-10, a seventh multiplier 212-8, a fourth adder 212-6, an eighth multiplier 212-11, and a third register 212-12. The third multiplier 212-3 is configured to: the current temperature value curr _ T is multiplied by a first power consumption calculation coefficient p1, and the operation result is output. The third adder 212-4 is configured to: the operation result of the third multiplier 212-3 is added by 1 and the operation result is output. The fourth multiplier 212-5 is configured to: the operation result of the third adder 212-4 is multiplied by the second power consumption calculation coefficient p2, and the operation result is output. The fifth multiplier 212-7 is configured to: the overall signal inversion ratio alpha is multiplied by the current voltage value curr _ V, and the operation result is output. The sixth multiplier 212-10 is configured to: the current frequency value curr _ F is multiplied by a third power consumption calculation coefficient p3, and the operation result is output. The seventh multiplier 212-8 is configured to: the operation result of the fifth multiplier 212-7 is multiplied by the operation result of the sixth multiplier 212-10, and the operation result is output. The fourth adder 212-6 is configured to: the operation result of the fourth multiplier 212-5 and the operation result of the seventh multiplier 212-8 are summed, and the operation result is output. The eighth multiplier 212-11 is configured to: the operation result of the fourth adder 212-6 is multiplied by the current voltage value curr _ V, and the operation result is output. The third register 212-12 is configured to: the received operation result of the eighth multiplier 212-11 is saved and the operation result of the eighth multiplier 212-11 is output as the current power consumption estimation value pwr _ hw.

It can be seen that the current power consumption estimation circuit 212b shown in fig. 8 calculates the current power consumption estimation value pwr _ hw according to the following formula:

pwr _ hw = curr _ V × (p 2 × (1 + p1 × curr _ T) + (curr _ F × curr _ V × alpha × p 3)) formula 2

In the above formula, curr _ V × p2 × (1 + p1 × curr _ T) represents the static power consumption of the chip, which reflects the basic power consumption condition of the chip under certain voltage and temperature conditions; curr _ V × curr _ F × curr _ V × alpha × p 3) then represents the dynamic power consumption of the chip, which reflects the power consumption due to each functional module when performing the corresponding function, e.g. when performing various calculations. Therefore, the on-chip power consumption control circuit can implement dynamic power consumption control aiming at different power consumption conditions of the chip.

It should be understood that the first, second, and third power consumption calculation coefficients p1, p2, and p3 may be determined based on empirical or experimental data, and can all be preset by software to facilitate debugging. Further, in some exemplary embodiments of the present disclosure, the second register 212-2 and the third register 212-12 may be configured to be updated according to a system operation clock (e.g., a clock signal provided to a chip) instead of a control cycle, thereby enabling optimization of timing in implementation for complex calculations.

Referring to fig. 9, a structure of a voltage frequency calculation circuit in the control information generation circuit shown in fig. 3 is schematically shown in a block diagram form according to some exemplary embodiments of the present disclosure. As shown in fig. 9, the voltage frequency calculation circuit 213 includes: a first selector 213a, an arithmetic circuit 213b, a first comparator 213c, a second comparator 213d, a second selector 213e, and a voltage frequency control value lookup table circuit 213f. The first selector 213a is configured to: and responding to the received mode information mode, selecting one of the received current power consumption estimated value pwr _ hw and the preset bypass mode power consumption estimated value pwr _ sw as a power consumption input value pwr _ in. The voltage frequency control value lookup table circuit 213f is configured to: in response to the received voltage frequency calculation value y [ n ], a lookup table generates a voltage frequency control value vf _ ctrl. The operation circuit 213b is configured to: the first operation result y1 and the second operation result y2 are generated in response to the received power consumption input value pwr _ in and the voltage frequency calculation value y [ n ]. The first comparator 213c is configured to: the output first power consumption superscalar signal sel-1 is asserted in response to the received power consumption input value pwr _ in being greater than or equal to the first power consumption threshold cap1, and the output first power consumption superscalar signal sel-1 is de-asserted in response to the received power consumption input value pwr _ in being less than the first power consumption threshold cap 1. The second comparator 213d is configured to: the output second power consumption superscalar signal sel-2 is asserted in response to the received power consumption input value pwr _ in being greater than or equal to the second power consumption threshold cap2, and the output second power consumption superscalar signal sel-2 is de-asserted in response to the received power consumption input value pwr _ in being less than the second power consumption threshold cap 2. The second selector 213e is configured to: the method comprises the steps of responding to the received first power consumption exceeding signal sel-1 to be effective, selecting a preset operation result y0 to be output as a voltage frequency calculation value y [ n ], responding to the received second power consumption exceeding signal sel-2 to be effective, selecting the received second operation result y2 to be output as the voltage frequency calculation value y [ n ], and responding to the first power consumption exceeding signal sel-1 and the second power consumption exceeding signal sel-2 to be ineffective, selecting the received first operation result y1 to be output as the voltage frequency calculation value y [ n ].

The operating mode information mode indicates the operating condition of the on-chip power consumption control circuit 200, which may be pre-configured by software. When the operating mode information mode indicates that the on-chip power consumption control circuit 200 is in, for example, a debugging operating condition, the first selector 213a selects the bypass mode power consumption estimated value pwr _ sw to output as the power consumption input value pwr _ in, so as to facilitate debugging of the on-chip power consumption control circuit 200. When the operating mode information mode indicates that the on-chip power consumption control circuit 200 is in a normal operating condition, the first selector 213a selects the current power consumption estimated value pwr _ hw to output as the power consumption input value pwr _ in. It should be understood that the operating mode information mode may be a signal having any suitable form as long as it can have two different states to indicate the debug mode and the normal mode, respectively, and it is sufficient for the first selector 213a to make a corresponding selection, which is not limited by the present disclosure. As a non-limiting example, the operating mode information mode may indicate a debug operating condition with a logic state "1" or a high signal, and a normal operating condition with a logic state "0" or a low signal, or vice versa.

In the voltage frequency calculation circuit 213 shown in fig. 9, the voltage frequency control value vf _ ctrl is table-checked and generated in response to the received voltage frequency calculation value y [ n ] by the voltage frequency control value lookup table circuit 213f. In other exemplary embodiments of the present disclosure, the voltage frequency control value vf _ ctrl may also be calculated and generated by performing corresponding calculation on the voltage frequency calculation value y [ n ]. The present disclosure is not limited as to the manner in which the corresponding voltage frequency control value vf _ ctrl is obtained from the voltage frequency calculation value y [ n ]. It should also be noted that in the solution of the present disclosure, the voltage frequency control value vf _ ctrl includes control information relating to both the voltage control value and the frequency control value. As a non-limiting example, the value of the high byte or high nibble in the voltage frequency control value vf ctrl may be a voltage control value and the value of the low byte or low nibble may be a frequency control value, or vice versa.

The first power consumption threshold value cap1 and the second power consumption threshold value cap2 are both power consumption threshold values that can be preset by software so as to enable the on-chip power consumption control circuit 200 according to the present disclosure to support handling of a power consumption abnormal condition. In addition, the first power consumption threshold value cap1 and the second power consumption threshold value cap2 can be set by software, so that debugging is facilitated. As a non-limiting example, the first power consumption threshold cap1 may be an emergency threshold and the second power consumption threshold cap2 may be a secondary emergency threshold. Therefore, if the current power consumption exceeds the first power consumption threshold cap1, it indicates that the chip enters a very urgent power consumption state, and therefore, special intervention must be taken to reduce the chip power consumption as soon as possible; if the current power consumption exceeds the second power consumption threshold cap2 and does not exceed the first power consumption threshold cap1, a certain intervention may be applied only on the basis of the conventional control to reduce the chip power consumption. For example, in the circuit shown in fig. 9, if the current power consumption is greater than or equal to the first power consumption threshold value cap1, the second selector 213e directly outputs the preset operation result y0 as the voltage frequency calculation value y [ n ], and if the current power consumption is greater than or equal to the second power consumption threshold value cap2 but less than the first power consumption threshold value cap1, the second selector 213e outputs the second operation result y2 as the voltage frequency calculation value y [ n ], and the second operation result y2 is less than the first operation result y1 calculated under normal conditions. It should be understood that the first comparator 213c and the second comparator 213d may be any suitable comparator, and the disclosure is not limited thereto.

As a non-limiting example, the second selector 213e may be a selector with dual select terminals that select accordingly in response to the conditions of the first power consumption superscalar signal sel-1 and the second power consumption superscalar signal sel-2. It should be appreciated that in the above non-limiting embodiment, the first power superscalar signal sel-1 has a higher priority than the second power superscalar signal sel-2. Specifically, as long as the first power consumption exceeding signal sel-1 is asserted, the second selector 213e handles a power consumption abnormal condition related to the emergency threshold, for example, outputting the preset operation result y0 as the voltage frequency calculation value y [ n ]. In the case where the second power consumption exceeding signal sel-2 is active, the second selector 213e may handle the power consumption abnormal condition related to the sub-critical threshold, for example, the second operation result y2 may be outputted as the voltage frequency calculation value y [ n ], only when the first power consumption exceeding signal sel-1 is inactive. When both the first power consumption exceeding signal sel-1 and the second power consumption exceeding signal sel-2 are inactive, the first operation result y1 is output as the voltage frequency calculation value y [ n ]. Further, it should also be understood that in the context of the present disclosure, active of a signal means that the signal is in a logic state "1" or high, and inactive of a signal means that the signal is in a logic state "0" or low.

Referring to fig. 10, a structure of an operation circuit in the voltage frequency calculation circuit shown in fig. 9 is schematically shown, according to some exemplary embodiments of the present disclosure. As shown in fig. 10, the arithmetic circuit 213b includes: a second subtractor 213-1, a ninth multiplier 213-4, a fourth register 213-2, a tenth multiplier 213-5, a fifth register 213-3, an eleventh multiplier 213-6, a sixth register 213-7, a twelfth multiplier 213-9, a seventh register 213-8, a thirteenth multiplier 213-10, a fifth adder 213-11 and a shifter 213-12. The second subtractor 213-1 is configured to: and generating a power consumption difference value e [ n ] between the received power consumption input value pwr _ in and a preset target power consumption value pwr _ obj, and outputting the power consumption difference value e [ n ]. The ninth multiplier 213-4 is configured to: the received power consumption difference e [ n ] is multiplied by a first calculation coefficient b0, and an operation result is output. The fourth register 213-2 is configured to: in response to the received power consumption difference e [ n ], a previous power consumption difference e [ n-1] is generated. The tenth multiplier 213-5 is configured to: and multiplying the received previous power consumption difference value e [ n-1] by a second calculation coefficient b1, and outputting an operation result. The fifth register 213-3 is configured to: the previous power consumption difference e [ n-2] is generated in response to the received previous power consumption difference e [ n-1]. The eleventh multiplier 213-6 is configured to: and multiplying the received power consumption difference value e [ n-2] of the first two times by a third calculation coefficient b2, and outputting an operation result. The sixth register 213-7 is configured to: in response to the received voltage frequency calculation value y [ n ], a previous voltage frequency calculation value y [ n-1] is generated. The twelfth multiplier 213-9 is configured to: the received previous voltage frequency calculation value y [ n-1] is multiplied by a first feedback coefficient a1, and the operation result is output. The seventh register 213-8 is configured to: the first two voltage-frequency calculation values y [ n-2] are generated in response to the received previous voltage-frequency calculation value y [ n-1]. The thirteenth multiplier 213-10 is configured to: the received first two voltage frequency calculation values y [ n-2] are multiplied by a second feedback coefficient a2, and the operation result is output. Fifth adder 213-11 is configured to: the operation result of the ninth multiplier 213-4, the operation result of the tenth multiplier 213-5, the operation result of the eleventh multiplier 213-6, the operation result of the twelfth multiplier 213-9 and the operation result of the thirteenth multiplier 213-10 are summed to generate the first operation result y1. Shifter 213-12 is configured to: in response to the received first operation result y1, the first operation result y1 is shifted to the right by sft digits to generate a second operation result y2. The number of shift bits sft is software configurable to facilitate debugging.

It should be understood that the shift-to-right operation of the shifter 213-12 is equivalent to performing a division operation on the received first operation result y1, i.e. y2 = y 1/(2) ^sft ). However, in other exemplary embodiments of the present disclosure, the shifter may be replaced with a multiplier that multiplies the received first operation result y1 by a corresponding coefficient to obtain a second operation result y2. It should also be understood that the operation circuit 213b uses the voltage frequency calculation value y [ n ] output by the second selector 213e in addition to the power consumption input value pwr _ in output by the first selector 213a as an input during the operation for generating the first operation result y1 and the second operation result y2]As an input. Therefore, the operation circuit 213b calculates the voltage frequency by y [ n ]]As feedback information is used in the operation process, thereby enabling closed-loop control to be implemented in the voltage frequency calculation circuit 213, which can generate a more accurate calculation result. It should also be understood that n, n-1 and n-2 are understood herein to be the current control period, the previous control period and the previous two control periods. In addition, the preset target power consumption value pwr _ obj is a power consumption target setting value of the current system, which may be preset by software. As a non-limiting example, the software may periodically derive a new power consumption estimate for the new performance requirement based on historical performance statistics of the chip core (e.g., GPU chip core) and the next new load estimation information, and then the software may compare the new power consumption estimate with the maximum power consumption value allowed by the system, and set the smaller of the two as a preset target power consumption value pwr _ obj in the on-chip power consumption control circuit in advance.

Therefore, based on the voltage frequency calculation circuit 213 according to the present disclosure, when the system-on-chip is operating below the maximum performance and power consumption, the power consumption target can be calculated and set to the power consumption target just satisfying the performance requirement of the system-on-chip, so that waste of power consumption can be avoided, and when the power consumption required for the operation of the system-on-chip exceeds the allowed maximum power consumption value, the actual power consumption can be clamped at the maximum power consumption value.

Referring to fig. 11, a structure of a voltage frequency coordination control circuit in the control information generation circuit shown in fig. 3 is schematically shown in a block diagram form according to some exemplary embodiments of the present disclosure. As shown in fig. 11, the voltage frequency coordination control circuit 214 includes: a voltage frequency value taking circuit 214a, a third delay 214-1, a third comparator 214-2, a third selector 214-3, an eighth register 214-4, a fourth comparator 214-5, an OR gate 214-6, a fifth comparator 214-7, a ninth register 214-8, a fourth selector 214-9, and a fourth delay 214-10. The voltage frequency valuator circuit 214a is configured to: in response to the received voltage frequency control value vf _ ctrl, a current voltage control value curr _ volt and a current frequency control value curr _ freq are generated. The third delayer 214-1 is configured to: the delayed voltage control value volt _ de is generated in response to the received current voltage control value curr _ volt. The eighth register 214-4 is configured to: the previous voltage control value information prev _ volt is generated in response to the received PWM control information PWM _ ctrl. The third comparator 214-2 is configured to: the output first conditional signal cond0 is asserted in response to the received present voltage control value curr _ volt being greater than or equal to the received previous voltage control value prev _ volt, and the output first conditional signal cond0 is de-asserted in response to the received present voltage control value curr _ volt being less than the received previous voltage control value prev _ volt. The third selector 214-3 is configured to: the received current voltage control value curr _ volt is output as the PWM control information PWM _ ctrl in response to the received first condition signal cond0 being valid, and the received delay voltage control value volt _ de is output as the PWM control information PWM _ ctrl in response to the received first condition signal cond0 being invalid. The fourth comparator 214-5 is configured to: the output second condition signal cond1 is asserted in response to the received current voltage control value curr _ volt being less than or equal to the received previous voltage control value prev _ volt, and the output second condition signal cond1 is de-asserted in response to the received current voltage control value curr _ volt being greater than the received previous voltage control value prev _ volt. The ninth register 214-8 is configured to: in response to the received current frequency control value curr _ freq, a previous frequency control value prev _ freq is generated. The fifth comparator 214-7 is configured to: the output third condition signal cond2 is asserted in response to the received current frequency control value curr _ freq being less than or equal to the received previous frequency control value prev _ freq, and the output third condition signal cond2 is de-asserted in response to the received current frequency control value curr _ freq being greater than the received previous frequency control value prev _ freq. OR gate 214-6 is configured to: the fourth condition signal cond3 is generated in response to the received second condition signal cond1 and third condition signal cond 2. The fourth delayer 214-10 is configured to: in response to the received current frequency control value curr _ freq, a delayed frequency control value freq _ de is generated. The fourth selector 214-9 is configured to: in response to the received fourth condition signal cond3 being active, the received current frequency control value curr _ freq is output as the frequency control information freq _ ctrl, and in response to the received fourth condition signal cond3 being inactive, the received delay frequency control value freq _ de is output as the PWM control information PWM _ ctrl.

It should be understood that the third and fourth delays 214-1 and 214-10 are used to delay the current voltage control value curr _ volt and the current frequency control value curr _ freq, respectively, by a number of clock cycles. The delay times of the third delay 214-1 and the fourth delay 214-10 need not be the same, but are software settable to facilitate debugging.

With the above circuits, the voltage-frequency coordination control circuit 214 can coordinate the control values related to the voltage and the frequency, which are obtained from the voltage-frequency control value vf _ ctrl, at a predetermined timing, so as to generate the required PWM control information PWM _ ctrl and the frequency control information freq _ ctrl, respectively.

Referring to fig. 12, a structure of a voltage frequency dereferencing circuit in the voltage frequency coordination control circuit shown in fig. 11 is schematically shown according to some exemplary embodiments of the present disclosure. As shown in fig. 12, the voltage frequency sampling circuit 214a includes a sampling and gate circuit 214-01 and a sampling shifter 214-02. The value AND gate 214-01 is configured to: and logically AND-ing the received voltage frequency control value vf _ ctrl and the value coefficient lowbits to generate a current voltage control value curr _ volt. The value shifter 214-02 is configured to: the received voltage frequency control value vf _ ctrl is shifted to generate the current frequency controller curr _ freq. As a non-limiting example, assuming that the voltage frequency control value vf _ ctrl is 8 bits in number, the and circuit 214-01 is configured to output the value of four bits lower than the voltage frequency control value vf _ ctrl as the current voltage control value curr _ volt, so that the value of the value coefficient lowbits may be "0F", and the value shifter 214-02 outputs the value of four bits higher than the voltage frequency control value vf _ ctrl as the current frequency control value curr _ freq by shifting the voltage frequency control value vf _ ctrl to the right by the number of bits highbits of 4 bits. It should be understood that the voltage frequency dereferencing circuit shown in fig. 12 is only an example, and thus, such a setting is also possible that the value of the voltage frequency control value vf _ ctrl lower nibble is output as the current frequency control value curr _ freq, and the value of the voltage frequency control value vf _ ctrl higher nibble is output as the current voltage control value curr _ volt.

Referring to fig. 13, a structure of a voltage control signal generation circuit in the on-chip power consumption control circuit shown in fig. 2a and 2b is schematically shown, according to some exemplary embodiments of the present disclosure. As shown in fig. 13, the voltage control signal generation circuit 220 includes a fifth selector 220a and a PWM signal generator 220b. The fifth selector 220a is configured to: in response to the received mode signal mode, one output is selected from the received PWM control information PWM _ ctrl and the preset bypass mode PWM control information PWM _ sw, and the PWM information PWM _ hw is generated. The PWM signal generator 220b is configured to: the PWM signal PWM is generated in response to the output of the fifth selector 220 a. The PWM signal PWM can then be supplied to the corresponding power supply chip to generate a suitable voltage signal. As previously mentioned, the operating mode information mode indicates the operating condition of the on-chip power consumption control circuit 200, which may be pre-configured by software. It should be understood that the operation mode information mode may be a signal having any suitable form as long as it can have two different states to indicate the debugging operation condition and the normal operation condition, respectively, and it is sufficient for the fifth selector 220a to make a corresponding selection, which is not limited by the present disclosure. Further, it should also be understood that the PWM signal generator 220b may be any suitable PWM generating device known in the art, and the present disclosure is not limited thereto.

Referring to fig. 14, a structure of a clock signal generation circuit in the on-chip power consumption control circuit shown in fig. 2a and 2b is schematically shown, according to some exemplary embodiments of the present disclosure. As shown in fig. 14, the clock signal generation circuit 230 includes a sixth selector 230a, a frequency information evaluation circuit 230b, a phase-locked loop 230c, a frequency divider 230d, a gating circuit 230e, and an and circuit 230f. The sixth selector 230a is configured to: in response to the received mode signal mode, one of the received frequency control information freq _ ctrl and the preset bypass mode frequency control information freq _ sw is selected and output to generate frequency information freq _ hw. The frequency information evaluation circuit 230b is configured to: the first control value freq _ n and the second control value freq _ i are generated in response to the output of the sixth selector 230 a. Phase locked loop 230c is configured to generate the raw clock signal VCO. Divider 230d is configured to: the original clock signal VCO is divided in response to the received first control value freq _ n to generate a divided clock signal clock _ div. Gating circuit 230e is configured to: the gate signal gate is generated in response to the received second control value freq _ i and the divided clock signal clock _ div. The and circuit 230f is configured to: the clock signal core _ clock is generated in response to the received gate signal gate and the divided clock signal clock _ div.

It should be understood that the first control value freq _ n and the second control value freq _ i are used to implement coarse grain control and fine grain control of the frequency of the clock signal core _ clock, respectively. Specifically, the first control value freq _ n is provided to the frequency divider 230d for implementing frequency division of the original clock signal VCO generated by the phase locked loop 230c, and the second control value freq _ i is provided to the gating circuit 230e for implementing clock pulse gating of the divided clock signal clock _ div. Therefore, the frequency of the finally generated clock signal core _ clock is as follows:

formula 3

In the above formula, F _clock Is the frequency, F, of the finally generated clock signal core _ clock _VCO Is the frequency of the original clock signal VCO, freq _ n is the first control value, freq _ i is the second control value, and M is the preset adjustment parameter. freq _ n may be an integer such as 4, 5, 6, 7, 8, 9, 10, \ 8230, etc.; m can also be an integer, such as 64, 128, 256, \8230, etc., where M represents the minimum step size that can be adjusted, with larger values giving smaller steps; freq _ i can take the value of M-1, M-2, M-3, \8230, M-M and the like, and M is an integer. In general, freq _ n cannot be made very large to achieve fine frequency control directly, and freq _ i cannot be made very small (i.e., m cannot be made very large), since it is considered that the frequency of the original clock signal VCO output by the phase locked loop 230c cannot be too large, otherwise it may cause relatively small clock pulse width at low frequency, resulting in timing problems at low voltage. By mutual complementation of the first control value freq _ n and the second control value freq _ i, a fast control of the subdivided clock frequency can be achieved. Furthermore, in practice, the parameter m is usually chosen to make a smooth transition between adjacent coarse-grained division numbers, such as the following downconversion sequence: f _VCO /freq_n, F _VCO /M*(M-1)/freq_n, F _VCO /M*(M-2)/freq_n, F _VCO /M*(M-3)/freq_n, …, F _VCO /M*(M-m)/freq_n, F _VCO /(freq_n+1),F _VCO /M*(M-1)/(freq_n+1),F _VCO M (M-2)/(freq _ n + 1), \8230, etc.

Gating circuit 230e may uniformly control the pulses of the gated clock to smooth transient currents using state machine control based on counting. For example, F _VCO Every M clock cycles,/M x (M-1)/freq _ n, gating off 1 clock pulse; f _VCO (M-2)/freq _ n is every M/2 clock cycles, gating off 1 clock pulse; f _VCO (M-3)/freq _ n is every M/3 clock cycles, gating off 1 clock pulse; f _VCO Every M/4 clock cycles,/freq _ n, 1 clock pulse is gated off, and so on.

Referring to fig. 15, the timing of the gating signal gate, the divided clock signal clock _ div, and the clock signal core _ clock are schematically illustrated, according to some demonstrative embodiments of the present disclosure. As shown in fig. 15, in this example, the adjustment parameter M is set to 64, and the second control value freq _ i is set to 63. Therefore, under the action of the gate signal gate, one clock signal in every 64 clock pulses of the frequency-divided clock signal clock _ div is gated off, so as to obtain the corresponding 63 clock pulses in the clock signal core _ clock. In this way, by the second control value freq _ i, fine control of the frequency of the clock signal core _ clock can be achieved.

Referring to fig. 16, the structure of a chip according to some exemplary embodiments of the present disclosure is schematically illustrated in block diagram form. As shown in fig. 16, the chip 300 may include the on-chip power consumption control circuit 200 as described in the previous exemplary embodiments. In other exemplary embodiments of the present disclosure, the chip 300 may include at least one on-chip power consumption control circuit 200 as described in the previous exemplary embodiments, thereby enabling allocation of power consumption target indicators of individual subsystems or functional modules according to performance requirements by software. Further, it should be understood that chip 300 may be any suitable chip, such as a GPU chip, a CPU chip, etc., as long as it is capable of applying the power consumption control circuit according to the present disclosure. The present disclosure does not limit the type of chip.

Referring to fig. 17, a power consumption control method according to some exemplary embodiments of the present disclosure is schematically illustrated in the form of a flowchart. It is to be understood that the power consumption control method 500 shown in fig. 17 can be applied to the on-chip power consumption control circuit 201 described according to the exemplary embodiment of the present disclosure. As shown in fig. 17, the power consumption control method 500 includes

steps

510, 520, 530, and 540:

at step 510, generating a PWM signal and PWM information based on the received PWM control information;

generating a clock signal and frequency information based on the received frequency control information, in step 520;

at step 530, obtaining at least one signal inversion ratio;

at step 540, PWM control information and frequency control information are updated based on the PWM information, the frequency information, and the at least one signal inversion ratio.

The power consumption control method 500 obtains corresponding feedback information (i.e., PWM information and frequency information) in the generation steps of the PWM signal and the clock signal (i.e., steps 510 and 520), thereby implementing on-chip closed-loop control inside the chip, thereby eliminating the need for off-chip low-speed links (e.g., a voltage detection chip, an analog-to-digital conversion link, etc.). Therefore, the power consumption control method 500 can complete the updating of data and the calculation and updating of various control information on the order of the system clock of the chip, thereby greatly reducing the sampling and control period. It is further noted that the power consumption control method 500 also receives at least one signal inversion ratio to regenerate the PWM control information and the frequency control information. At least one signal turnover ratio is a signal turnover ratio of a signal at each functional module of the chip, which reflects a power consumption condition of each functional module under a current working condition, and is beneficial to determining dynamic power consumption of the chip. Thus, based on consideration of the temperature factor and the at least one signal inversion ratio, the power consumption control method 500 according to the present disclosure can achieve more accurate control of the power consumption of the chip.

Further, in other exemplary embodiments of the present disclosure, the power consumption control method 500 obtains at least one signal inversion ratio and a temperature measurement value in step 530, and updates PWM control information and frequency control information based on the PWM information, the frequency information, the temperature measurement value, and the at least one signal inversion ratio in step 540. In consideration of the temperature, the power consumption control method 500 can achieve more thorough consideration and more accurate control of the power consumption of the chip. The power consumption control method according to this exemplary embodiment can be applied to the on-chip power consumption control circuit 200 described according to the various exemplary embodiments of the present disclosure.

The terminology used in the present disclosure is for the purpose of describing embodiments in the present disclosure only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises" and "comprising," when used in this disclosure, specify the presence of stated features but do not preclude the presence or addition of one or more other features. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various features, these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the description of the present specification, the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

It should be understood that the adders, subtractors, multipliers, comparators, shifters, selectors, registers, delays, etc. described in this disclosure are hardware circuits that can be implemented in any suitable technology known in the art, such as, but not limited to, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays, field programmable gate arrays, etc. The present disclosure is not so limited.

It should be understood that the steps of a method illustrated or otherwise described herein in a flowchart are merely exemplary and are not meant to imply that the steps of a method illustrated or described must be performed in the order illustrated or described. Rather, various steps of the methods shown in the flowcharts or otherwise described herein may be performed in a different order than presented in the present disclosure or may be performed concurrently. Further, the methods shown in the flowcharts or otherwise described herein may include other additional steps as desired.

Although the present disclosure has been described in detail in connection with some exemplary embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present disclosure is limited only by the accompanying claims.

Claims

1. An on-chip power consumption control circuit comprising:

a voltage control signal generation circuit including a fifth selector and a PWM signal generator, wherein:

the fifth selector is configured to: responding to the received mode signal, and selecting one of the received PWM control information and preset bypass mode PWM control information to be output as PWM information;

the PWM signal generator is configured to: generating a PWM signal in response to the PWM information output from the fifth selector;

the clock signal generating circuit comprises a sixth selector, a frequency information dereferencing circuit, a phase-locked loop, a frequency divider, a gating circuit and an AND gate circuit, wherein:

the sixth selector is configured to: responding to the received mode signal, and selecting one of the received frequency control information and preset bypass mode frequency control information to be output as frequency information;

the frequency information valuating circuit is configured to: generating a first control value and a second control value in response to the frequency information output by the sixth selector;

the phase locked loop is configured to generate a raw clock signal;

the frequency divider is configured to: dividing the original clock signal in response to the received first control value to generate a divided clock signal;

the gating circuitry is configured to: generating a gating signal in response to the received second control value and the divided clock signal;

the AND gate circuit is configured to: generating the clock signal in response to the received gating signal and the divided clock signal;

the control information generating circuit comprises a voltage value updating circuit, a frequency value updating circuit, a temperature value updating circuit, a power consumption calculating circuit, a voltage frequency calculating circuit and a voltage frequency coordination control circuit, wherein:

the voltage value update circuit is configured to: generating a current voltage value in response to the received PWM information;

the frequency value update circuit is configured to: generating a current frequency value in response to the received frequency information;

the temperature value update circuit is configured to: generating a current temperature value in response to the received temperature measurement;

the power consumption calculation circuit is configured to: calculating a current power consumption estimate in response to the received current voltage value, the current frequency value, the current temperature value, and at least one signal upset ratio;

the voltage frequency calculation circuit is configured to: generating a voltage frequency control value in response to the received current power consumption estimation value;

the voltage frequency coordination control circuit is configured to: updating the PWM control information and the frequency control information in response to the received voltage frequency control value.

2. The on-chip power consumption control circuit of claim 1, wherein the voltage value update circuit comprises:

a PWM information delay circuit configured to: generating delayed PWM information in response to the received PWM information;

a voltage lookup table circuit configured to: and responding to the received time delay PWM information, and looking up a table to generate the current voltage value.

3. The on-chip power consumption control circuit of claim 2, wherein the delay time of the PWM information delay circuit is dynamically adjustable based on the PWM information.

4. The on-chip power consumption control circuit of claim 3, wherein the PWM information delay circuit comprises:

a first register configured to: generating previous PWM information in response to the received PWM information;

a first subtractor configured to: generating a PWM information difference value based on the PWM information and the previous PWM information;

a first multiplier configured to: multiplying the PWM information difference value by a PWM information difference value adjustment coefficient to generate a delay time value;

a first delayer configured to: delaying the PWM information in response to the received PWM information and the delay time value to generate the delayed PWM information.

5. The on-chip power consumption control circuit of claim 4, wherein the previous PWM information is a previous PWM information.

6. The on-chip power consumption control circuit of claim 1, wherein the frequency value update circuit comprises:

a second delayer configured to: generating delayed frequency information in response to the received frequency information;

a frequency lookup table circuit configured to: and responding to the received delay frequency information, and looking up a table to generate the current frequency value.

7. The on-chip power consumption control circuit of claim 6, wherein the delay time of the second delay is configurable.

8. The on-chip power consumption control circuit of claim 1, wherein the temperature value update circuit comprises:

a second multiplier configured to: multiplying the temperature measurement value by a first temperature value adjusting coefficient, and outputting an operation result;

a first adder configured to: and adding a second temperature value adjusting coefficient to the operation result of the second multiplier to generate the current temperature value.

9. The on-chip power consumption control circuit of claim 1, wherein the temperature value update circuit comprises a temperature look-up table circuit configured to: in response to receiving the temperature measurement, a table lookup generates the current temperature value.

10. The on-chip power consumption control circuit of claim 1, wherein the power consumption calculation circuit comprises:

an overall signal inversion ratio calculation circuit configured to: generating an overall signal inversion ratio based on the at least one received signal inversion ratio;

a current power consumption estimation circuit configured to: generating the current power consumption estimate based on the received overall signal turnover ratio, the current voltage value, the current frequency value, and the current temperature value.

11. The on-chip power consumption control circuit of claim 10, wherein the overall signal turnover ratio calculation circuit comprises:

at least one multiplier in one-to-one correspondence with the at least one signal inversion ratio, wherein each of the at least one multiplier is configured to multiply the corresponding signal inversion ratio by a corresponding signal inversion ratio adjustment coefficient and output an operation result;

a second adder configured to: summing the operation results of the at least one multiplier and outputting the operation results;

a second register configured to: saving the received operation result of the second adder, and outputting the operation result of the second adder as the overall signal inversion ratio.

12. The on-chip power consumption control circuit of claim 10, wherein the current power consumption estimation circuit comprises:

a third multiplier configured to: multiplying the current temperature value by a first power consumption calculation coefficient, and outputting an operation result;

a third adder configured to: adding 1 to the operation result of the third multiplier and outputting the operation result;

a fourth multiplier configured to: multiplying an operation result of the third adder by a second power consumption calculation coefficient, and outputting the operation result;

a fifth multiplier configured to: multiplying the overall signal turnover ratio by the current voltage value and outputting an operation result;

a sixth multiplier configured to: multiplying the current frequency value by a third power consumption calculation coefficient, and outputting an operation result;

a seventh multiplier configured to: multiplying the operation result of the fifth multiplier by the operation result of the sixth multiplier, and outputting the operation result;

a fourth adder configured to: summing the operation result of the fourth multiplier and the operation result of the seventh multiplier, and outputting the operation results;

an eighth multiplier configured to: multiplying the operation result of the fourth adder by the current voltage value, and outputting the operation result;

a third register configured to: saving the received operation result of the eighth multiplier, and outputting the operation result of the eighth multiplier as the current power consumption estimation value.

13. The on-chip power consumption control circuit of claim 1, wherein the voltage frequency calculation circuit comprises:

a first selector configured to: responding to the received mode information, and selecting one of the received current power consumption estimated value and a preset bypass mode power consumption estimated value to be output as a power consumption input value;

a voltage frequency control value look-up table circuit configured to: responding to the received voltage frequency calculation value, and looking up a table to generate the voltage frequency control value;

an operational circuit configured to: generating a first operation result and a second operation result in response to the received power consumption input value and the voltage frequency calculation value;

a first comparator configured to: responsive to the received power consumption input value being greater than or equal to a first power consumption threshold, asserting an output first power consumption superstandard signal; and, in response to the received power consumption input value being less than a first power consumption threshold, invalidating the first power consumption superstandard signal;

a second comparator configured to: responsive to the received power consumption input value being greater than or equal to a second power consumption threshold, asserting an output second power consumption superstandard signal; and, in response to the received power consumption input value being less than a second power consumption threshold, invalidating the second power consumption superstandard signal;

a second selector configured to: the method comprises the steps of responding to the fact that a received first power consumption exceeding signal is effective, selecting a preset operation result to be output as the voltage frequency calculation value, responding to the fact that only a received second power consumption exceeding signal is effective, selecting the received second operation result to be output as the voltage-frequency calculation value, and responding to the fact that the first power consumption exceeding signal and the second power consumption exceeding signal are both ineffective, selecting the received first operation result to be output as the voltage frequency calculation value.

14. The on-chip power consumption control circuit of claim 13, wherein the operational circuit comprises:

a second subtractor configured to: generating a power consumption difference value between the received power consumption input value and a preset target power consumption value, and outputting the power consumption difference value;

a ninth multiplier configured to: multiplying the received power consumption difference value by a first calculation coefficient, and outputting an operation result;

a fourth register configured to: generating a previous power consumption difference value in response to the received power consumption difference value;

a tenth multiplier configured to: multiplying the received previous power consumption difference value by a second calculation coefficient, and outputting an operation result;

a fifth register configured to: generating a previous power consumption difference value in response to the received previous power consumption difference value;

an eleventh multiplier configured to: multiplying the received power consumption difference values of the first two times by a third calculation coefficient, and outputting a calculation result;

a sixth register configured to: generating a previous voltage frequency calculation value in response to the received voltage frequency calculation value;

a twelfth multiplier configured to: multiplying the received previous voltage frequency calculation value by a first feedback coefficient, and outputting an operation result;

a seventh register configured to: generating a first two times voltage frequency calculation value in response to the received previous time voltage frequency calculation value;

a thirteenth multiplier configured to: multiplying the received first twice voltage frequency calculation value by a second feedback coefficient, and outputting an operation result;

a fifth adder configured to: summing an operation result of the ninth multiplier, an operation result of the tenth multiplier, an operation result of the eleventh multiplier, an operation result of the twelfth multiplier, and an operation result of the thirteenth multiplier to generate the first operation result; and

a shifter configured to shift the first operation result to the right in response to the received first operation result to generate the second operation result.

15. The on-chip power consumption control circuit of claim 1, wherein the voltage frequency coordination control circuit comprises:

a voltage frequency valuator circuit configured to: generating a current voltage control value and a current frequency control value in response to the received voltage frequency control value;

a third delayer configured to: generating a delayed voltage control value in response to the received current voltage control value;

an eighth register configured to: generating previous voltage control value information in response to the received PWM control information;

a third comparator configured to: responsive to the received current voltage control value being greater than or equal to the received previous voltage control value, asserting an output first conditional signal, and responsive to the received current voltage control value being less than the received previous voltage control value, deasserting the output first conditional signal;

a third selector configured to: outputting the received current voltage control value as the PWM control information in response to the received first condition signal being valid, and outputting the received delay voltage control value as the PWM control information in response to the received first condition signal being invalid;

a fourth comparator configured to: asserting an output second condition signal in response to the received current voltage control value being less than or equal to the received previous voltage control value, and de-asserting the output second condition signal in response to the received current voltage control value being greater than the received previous voltage control value;

a ninth register configured to: generating a previous frequency control value in response to the received current frequency control value;

a fifth comparator configured to: asserting an output third conditional signal in response to the received current frequency control value being less than or equal to the received previous frequency control value, and de-asserting the output third conditional signal in response to the received current frequency control value being greater than the received previous frequency control value;

an OR gate configured to: generating a fourth condition signal in response to the received second and third condition signals;

a fourth delayer configured to: generating a delayed frequency control value in response to the received current frequency control value;

a fourth selector configured to: outputting the received current frequency control value as the frequency control information in response to the received fourth condition signal being valid, and outputting the received delayed frequency control value as the PWM control information in response to the received fourth condition signal being invalid.

16. The on-chip power consumption control circuit of claim 15, wherein the delay times of the third and fourth delays are each configurable.

17. The on-chip power consumption control circuit of claim 1, wherein the clock signal generation circuit is configured to cause the clock signal to have a frequency of:

wherein, F _clock Is said clock signalFrequency of number, F _VCO Is the frequency of the original clock signal, freq _ n is the first control value, freq _ i is the second control value, and M is a preset gating adjustment parameter, wherein freq _ n, freq _ i, and M are all integers greater than 0, and freq _ i is less than M.

18. A chip comprising at least one on-chip power consumption control circuit as claimed in any one of claims 1 to 17.

19. The chip of claim 18, wherein the chip is a GPU chip.

20. A power consumption control method applied to the on-chip power consumption control circuit as claimed in claim 1, comprising:

generating the PWM signal and the PWM information based on the received PWM control information;

generating the clock signal and the frequency information based on the received frequency control information;

obtaining the at least one signal turnover ratio and the temperature measurement;

updating the PWM control information and the frequency control information based on the PWM information, the frequency information, the at least one signal inversion ratio, and the temperature measurement.