CN115298636A - Method and device for measuring power of processor core - Google Patents
Method and device for measuring power of processor core Download PDFInfo
- Publication number
- CN115298636A CN115298636A CN202080098654.6A CN202080098654A CN115298636A CN 115298636 A CN115298636 A CN 115298636A CN 202080098654 A CN202080098654 A CN 202080098654A CN 115298636 A CN115298636 A CN 115298636A
- Authority
- CN
- China
- Prior art keywords
- power
- processor
- processor core
- power consumption
- estimated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The application discloses a method and a device for measuring power of a processor core, relates to the technical field of chips, and can reduce errors between estimated power and actual power of the processor core. The method comprises the following steps: determining the sum of the estimated power of a plurality of processor cores contained in the processor according to the estimated power of each processor core in the processor; determining a sum of actual powers of a plurality of processor cores in a processor; and calibrating the estimated power of each processor core according to the estimated power sum and the actual power sum to obtain the calibrated power of each processor core. The method and the device can be used for calibrating the estimated power of each processor core of the multi-core processor.
Description
The present application relates to the field of chip technologies, and in particular, to a method and an apparatus for measuring processor core power.
The processor may include a plurality of processor cores. In the design of the shared power domain of the plurality of processor cores, the plurality of processor cores share the same power domain (power supply network and power supply circuit), and the processor can obtain the actual power sum of the plurality of processor cores according to the voltage and the current of the power domain. Meanwhile, the processor can also obtain the estimated power of each processor core according to a plurality of strategies which can calculate the estimated power. And the estimated power of each processor core may be used to adjust the frequency and voltage of each processor core. The voltage and the current of the power domain can be read by a monitoring device in the power supply device, and the actual power consumption value of the power domain can be calculated based on the actually read voltage and current values of the power domain, so that the power consumption management of the processor is realized.
At present, the estimation strategy for the estimated power of the processor core can be essentially understood as follows: the estimation is based on a power consumption model of activity coefficients and power consumption coefficients of each processor core. For example, in an estimation strategy, the processor core may be divided into different modules, the number of times each module is activated in a preset period is an activity coefficient of each module, and the power generated when each module is activated once in the preset period is a power consumption coefficient of each module. However, in a preset period, each time a module is activated, the power consumption coefficient generated by the module is not a constant value, that is, the power consumption coefficients generated by two activated modules may be different. The power consumption coefficient of a module is the average power consumption obtained by fitting the power consumption coefficient generated when the module is activated for multiple times in a preset period in a linear regression mode, that is, the average power consumption obtained by fitting is used as the power consumption coefficient of a module in a preset period. Therefore, in a preset period, an error exists between the estimated power of the processor core obtained through the activity coefficient and the power consumption coefficient of each module of the processor core and the actual power. When the estimated power of each processor core has a large error with the actual power, the estimated power error has a large effect, which may cause the sum of the actual powers of the processors to exceed the power limit of the maximum supply current of the processors, and may also cause the power of the processors to be underutilized, thereby causing the performance of the processors to be reduced.
Disclosure of Invention
The embodiment of the application provides a method and a device for measuring power of a processor core, which can reduce the error between the estimated power and the actual power of the processor core.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
in a first aspect, a method for measuring power of a processor core is provided, including: determining the total estimated power of a plurality of processor cores contained in a processor core processor according to the estimated power of each processor core in the processor; determining the sum of the actual power of a plurality of processor cores in a processor core processor; and calibrating the estimated power of each processor core according to the estimated power sum and the actual power sum to obtain the calibrated power of each processor core.
In other words, the estimated power of each processor core can be calibrated according to the relative relationship between the estimated power sum and the actual power sum. Therefore, the calibrated power of each processor core can more accurately reflect the actual power of each processor core after calibration, the error between the estimated power and the actual power of the multi-core processor can be reduced, the power margin required to be reserved can be reduced, the processor can obtain the maximum performance in the design as far as possible, and the more efficient power consumption management of the processor is realized.
In one possible design, the method further includes: and adjusting the frequency and the voltage of each processor core according to the calibration power of each processor core.
Because the estimated power after calibration, that is, the calibrated power is closer to the actual power of each processor core than the estimated power before calibration, the performance of the processor can be better exerted when the voltage and the frequency of the processor core are adjusted according to the calibrated power.
In one possible design, calibrating the estimated power of each processor core as a function of the processor core estimated power sum and the processor core actual power sum comprises: determining a calibration coefficient according to the estimated power sum of the processor core and the actual power sum of the processor core; and calibrating the estimated power of each processor core according to the calibration coefficient of the processor core.
The calibration factor may be, for example, the ratio η of the sum of the actual powers to the sum of the estimated powers. When the value of the actual power sum is η times the value of the estimated power sum, it can be approximated that the actual power of each processor core is also η times the estimated power. Therefore, the calibration power of the processor core can be obtained according to the estimated power and the eta value of the processor core, and the calibration power is closer to the actual power of the processor core relative to the estimated power. When the estimated power is closer to the actual power, the power margin can be set smaller, so that the processor performance is better.
In one possible design, determining an estimated power sum of a plurality of processor cores included in a processor according to an estimated power of each processor core in the processor includes: determining the estimated power sum of the plurality of processor cores according to the estimated power of each processor core in the processor and the static power of the power domains of the plurality of processor cores; the static power of the power domains of the plurality of processor cores refers to power consumption generated by leakage current of the power domains of the plurality of processor cores.
Because the estimated power sum and the actual power sum still have errors, when the estimated power sum is calculated, if the static power of the power domains of the processor cores is also considered, the estimated power sum of the plurality of processor cores can be used for representing the real power condition more accurately.
In one possible design, prior to determining the estimated power sum for the plurality of processor cores, the method further includes: an estimated power for each processor core is determined. That is, the estimated power for each processor core may be determined prior to determining the estimated power sum.
In one possible design, determining the estimated power for each processor core includes: determining an estimated power of each processor core from the active power of each processing core and the base power of each processor core; wherein the active power is indicative of power consumed by the at least one power consumption characterizing signal of each processing core when in an active state, and the base power is indicative of power consumed by each processor core when the at least one power consumption characterizing signal of each processing core is not in an active state.
This is to consider that the power consumption characterizing signal selected for each processor core may not cover all power consumption events of the processor core (even if it can cover B, the value of B is 0), so that when the base power is obtained, the estimated power of each processor core can be obtained according to the active power and the base power, so that the estimated power can reflect the actual power of the processor core more accurately.
In one possible design, the active power of each processor core is determined by: and obtaining the active power according to the activity coefficient of at least one power consumption characterization signal of each processor core and the power consumption coefficient of at least one power consumption characterization signal, wherein the activity coefficient of each power consumption characterization signal is used for reflecting the coefficient of each power consumption characterization signal in an active state, and the power consumption coefficient of each power consumption characterization signal is used for reflecting the power consumption consumed by each power consumption characterization signal in the active state. For example, the activity coefficient and the power consumption coefficient of each power consumption characterization signal may be multiplied, and then the products corresponding to each power consumption characterization signal are summed, so as to obtain the activity power of one processor core.
In one possible design, the method further includes: and adjusting the power consumption coefficient of at least one power consumption characterization signal of each processor core according to the actual power sum and the activity coefficient of at least one power consumption characterization signal of each processor core.
Generally, when the power consumption coefficient is obtained, the power consumption coefficient is obtained by measuring the estimated power of each processor core and fitting the estimated power and the activity coefficient. However, the estimated power obtained by measurement always has errors, and therefore, if the power consumption coefficient obtained by fitting the actual power sum is used, the estimated power obtained by calculating the power consumption coefficient is relatively more accurate.
In a second aspect, an apparatus for measuring power of a processor core is provided, including: the frequency controller is used for determining the total estimated power of a plurality of processor cores contained in the processor according to the estimated power of each processor core in the processor obtained by the power consumption monitor; the frequency controller is also used for determining the sum of the actual power of a plurality of processor cores in the processor; and the frequency controller is also used for calibrating the estimated power of each processor core according to the estimated power sum and the actual power sum so as to obtain the calibrated power of each processor core. The beneficial effects of the second aspect can be seen in the description of the first aspect on the method for measuring the power of the processor core.
In one possible design, the frequency controller is further configured to: and adjusting the frequency and the voltage of each processor core according to the calibration power of each processor core.
In one possible design, the frequency controller is to: determining a calibration coefficient according to the estimated power sum and the actual power sum; and calibrating the estimated power of each processor core according to the calibration coefficient.
In one possible design, the frequency controller is configured to: determining the sum of the estimated power of the plurality of processor cores according to the estimated power of each processor core in the processor and the static power of the power domains of the plurality of processor cores; the static power of the power domains of the plurality of processor cores refers to power consumption generated by leakage current of the power domains of the plurality of processor cores.
In one possible design, the power consumption monitor is to: an estimated power for each processor core is determined.
In one possible design, the power consumption monitor is to: determining an estimated power of each processor core from the active power of each processing core and the base power of each processor core; wherein the active power is indicative of power consumed by the at least one power consumption characterizing signal of each processing core when in an active state and the base power is indicative of power consumed by each processor core when the at least one power consumption characterizing signal of each processing core is not in an active state.
In one possible design, the power consumption monitor is to: and obtaining the active power according to the activity coefficient of at least one power consumption characterization signal of each processor core and the power consumption coefficient of at least one power consumption characterization signal, wherein the activity coefficient of each power consumption characterization signal is used for reflecting the coefficient of each power consumption characterization signal in an active state, and the power consumption coefficient of each power consumption characterization signal is used for reflecting the power consumption consumed by each power consumption characterization signal in the active state.
In one possible design, the frequency controller is further configured to: and adjusting the power consumption coefficient of at least one power consumption characterization signal of each processor core according to the actual power sum and the activity coefficient of at least one power consumption characterization signal of each processor core.
In a third aspect, a computer readable storage medium is provided, comprising a program or instructions, which when executed by a processor, performs the method as described in the first aspect and any one of the possible designs of the first aspect.
In a fourth aspect, there is provided a computer program product for causing an electronic device to perform the method as set forth in the first aspect and any one of the possible designs of the first aspect, when the computer program product is run on a computer.
In a fifth aspect, a communication device is provided, comprising a device according to any of the possible designs of the second aspect or the second aspect.
In a sixth aspect, a chip is provided, which comprises the apparatus according to the second aspect or any one of the possible designs of the second aspect.
Fig. 1 is a communication device applicable to a process provided by an embodiment of the present application;
fig. 2 is a schematic structural diagram of a processor according to an embodiment of the present application;
fig. 3 is a flowchart of a method for measuring power of a processor core according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a method for determining a power consumption coefficient and a base power according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a silicon dissipation factor calibration according to an embodiment of the present disclosure;
fig. 6 is a block diagram of a computing system according to an embodiment of the present application.
The method and the device can be applied to various processors with multi-processor core common power domain design. Obtaining the estimated power consumption of each processor core of the processor is a necessary condition for efficient power management of the processor.
Due to the design of the multi-processor core common power domain, the actual power of each processor core cannot be directly obtained through measurement, and therefore, the power of each processor core needs to be estimated through a certain strategy. However, the power of each processor core obtained by the power estimation method is prone to have an error with the actual power of each processor core, so that the method is used for further correcting the estimated power, and the corrected calibrated power of each processor core is more approximate to the actual power of each processor core compared with the estimated power before correction.
As shown in fig. 1, the processor provided in the present application may be applied to various communication devices, which may be, for example, a chip or a terminal device. The chip may be a system on chip (SoC) with multiple processor cores. The terminal device may be a mobile terminal, such as a mobile phone 11, a pad12, a notebook computer 13, or the like; the terminal device may also be a non-mobile terminal, such as a desktop computer 14. If the terminal device is a mobile terminal, the processor may be a multi-processor core processor, and the multi-processor core processor may be, for example, an SoC.
Fig. 2 is a diagram illustrating a processor 20 with a common power domain design for multiple processor cores according to an embodiment of the present disclosure. Take the example where the processor 20 includes 4 processor cores (processor core 0, processor core 1, processor core 2, and processor core 3). Processor 20 may include a processor core power plane 21 and a non-processor core power plane 22. It should be noted that the processor 20 shown in fig. 2 is only one example of a processor, and that the processor may also include other power plane designs. The processor core power plane 21 may include 4 processor cores, a power consumption monitor 211 corresponding to each processor core, a power supply circuit 212, and a frequency controller 213. The non-processor core power plane 22 may include external caches, internal memory, general purpose units, accelerators, and input/output control units & interface units. It should be noted that the power consumption monitor 211 may be located on other power planes in practical applications.
The power consumption monitors 211 may obtain estimated powers preliminarily estimated for the processor cores by periodically monitoring the behavior of the power consumption characterizing signals of the corresponding processor cores, and send the estimated powers to the frequency controller 213, and the frequency controller 213 may be configured to aggregate the estimated powers sent by the power consumption monitors 211, and finally determine the sum of the estimated powers when the processor 20 operates, so as to provide data support for the frequency and voltage adjustment of the processor 20. In the processor 20 shown in fig. 2, the frequency controller 213 is located in the processor core power plane 21, but in some other applications the frequency controller 213 may be located in other power planes. The power supply circuit 212 may provide the voltage and current of the processor core power plane 21 to the frequency controller 213, and the frequency controller 213 may obtain the actual power sum currently of each processor core of the processor 20 according to the voltage and current.
For the above mentioned, the present application may further correct the estimated power, so that the estimated power of each processor core after correction is more similar to the actual power of each processor core than the estimated power before correction, and in the embodiment of the present application, the specific scheme may be: the frequency controller 213 may calibrate the estimated power of each processor core according to the actual power sum obtained from the voltage and the current provided by the power supply circuit 212 and the estimated power sum obtained from the estimated power sent by the power consumption monitor 211, so as to obtain the calibrated power of each processor core. Because the estimated power sum may have an error relative to the actual power sum, when a relative relationship of the error of the estimated power sum and the actual power sum is obtained according to the estimated power sum and the actual power sum, a calibration power closer to the actual power of each processor core can be obtained according to the relative relationship and the estimated power of each processor core. That is to say, when the estimated power of each processor core is obtained, the estimated power of each processor core may be further calibrated, so that the frequency controller 213 may adjust the frequency and the voltage of each processor core during operation according to the more accurate calibrated power.
In the embodiment of the present application, the software architecture of the frequency controller 213 may be modified to implement the scheme of the present application, for example, firmware for implementing the scheme of the present application is added to the frequency controller 213; the hardware architecture of the frequency controller 213 can also be modified to implement the solution of the present application; the solution of the present application may also be implemented by modifying both the software architecture and the hardware architecture of the frequency controller 213, which is not limited in the present application.
The scheme of the present application is further explained below.
An embodiment of the present application provides a method for measuring power of a processor core, as shown in fig. 3, the method includes:
301. an estimated power of a plurality of processor cores of a processor is determined.
In some embodiments, steps 301 to 304 may be performed periodically, that is, the estimated power of each processor core may be calibrated once per preset period. The preset period may be, for example, 100us, or may be other values, which is not limited in this application.
In some embodiments, when the processor 20 runs the program, each power consumption monitor 211 may perform periodic power estimation for the corresponding processor core, resulting in an estimated power of each processor core at each preset period. The estimated power may be an active power of the corresponding processor core. The active power is indicative of the power consumed by at least one power consumption characterizing signal of each processing core when in an active state. Wherein, for a power consumption characterizing signal, the active state thereof may be that the power consumption characterizing signal is in a flip or high state.
Wherein the active power of each processor core may be determined by: and obtaining the active power according to the power consumption coefficient of the at least one power consumption characterization signal and the activity coefficient of the at least one power consumption characterization signal of each processor core. For any processor core, one processor core can correspond to a plurality of power consumption characterization signals, and one power consumption characterization signal corresponds to one activity coefficient and one power consumption coefficient; for a processor core, the power consumption characterization signals are signals participating in statistics of estimated power of the processor core, and the activity coefficient of each power consumption characterization signal is used for reflecting the coefficient when each power consumption characterization signal is in an active state. For example, a power consumption characterizing signal, the corresponding activity factor may be understood as the number of transitions or the number of clock cycles at a high level of the power consumption characterizing signal. The power consumption coefficient of each power consumption characterization signal is used for reflecting the power consumption consumed by each power consumption characterization signal when the power consumption characterization signals are in an active state.
Wherein the power consumption coefficient for determining the active power may be determined by a linear fitting in advance. For example, the estimated power (active power) of each processor core may be determined computationally according to equation one below:
P m ＝C 0 W 0 +C 1 W 1 +C 2 W 2 +…+C n W n wherein, P m Represents the estimated power of the mth processor core in a preset period, C 0 、C 1 、C 2 …C n Representing the activity coefficients, W, corresponding to the n power consumption characterization signals of the mth processor core 0 、W 1 、W 2 …W n And representing power consumption coefficients corresponding to the n power consumption characterization signals of the mth processor core respectively. m and n are integers greater than or equal to 0.
302. The estimated power sum of a plurality of processor cores included in a processor is determined according to the estimated power (active power) of each processor core in the processor.
And adding the estimated power of each processor core to obtain the sum of the estimated power of the plurality of processor cores.
In some embodiments, the power consumption monitor 211 may send the estimated power of the corresponding processor core to the frequency controller 213, and the frequency controller 213 calculates the sum of the estimated powers of the plurality of processor cores of the processor according to the received estimated powers of the plurality of processor cores.
For example, the estimated power sum may be calculated as formula two: p total ＝P 0 +P 1 +P 2 …+P m Wherein P is total Represents the sum of estimated powers, P, of a plurality of processor cores in a preset period 0 、P 1 、P 2 …P m And representing the estimated power corresponding to the m +1 processor cores respectively.
In some embodiments, in calculating the estimated power sum, the static power of the processor core power plane 21 may also be monitored while monitoring the coefficient of power consumption of each processor core at every preset period. For the processor core power plane 21, static power, i.e., leakage power consumption, refers to power consumption generated by leakage currents of the power domains of the plurality of processor cores in the processor core power plane 21. The static power consumption may be obtained in various ways. In some embodiments, the static power consumption may be derived from the leakage current formula, i.e., P leak ＝f(V，T)，P leak Which represents the static power of the processor core power plane 21 for a predetermined period, i.e. the static power is calculated based on the relationship between the voltage and the temperature of the processor core power plane 21. Thus, the calculation of the estimated power sum can be also as in equation three: p total ＝P 0 +P 1 +P 2 …+P m +P leak . Static power P leak The addition of (2) can enable the estimated power sum of the multiple processor cores to more accurately represent the real power situation.
In some embodiments, the voltage and temperature at which the quiescent power is obtained may be provided by the power supply circuit 212 to the frequency controller 213, and the quiescent power calculated by the frequency controller 213 based on the voltage and temperature.
303. A sum of actual powers of a plurality of processor cores in a processor is determined.
In some embodiments, during a preset period, the supply voltage V and the supply current I of the power domain of the processor core power plane 21 may be obtained according to the formula four: p total ' = VI, and calculating to obtain the actual power consumption sum of the plurality of processor cores in a preset period. Wherein, P total ' represents the sum of the actual power consumptions of the plurality of processor cores in a preset period.
In some embodiments, the power supply circuit 212 may obtain the power supply voltage V and the power supply current I, provide the obtained power supply voltage V and the obtained power supply current I to the frequency controller 213, and calculate the actual power consumption sum P of the plurality of processor cores by the frequency controller 213 according to the power supply voltage V and the power supply current I total '。
304. And calibrating the estimated power of each processor core according to the estimated power sum and the actual power sum to obtain the calibrated power of each processor core.
In some embodiments, the estimated power of each processor core may be calibrated according to a relative relationship between the estimated power sum and the actual power sum, so as to obtain a calibrated power of each processor core after calibration.
In some embodiments, the estimated power sum P obtained in a preset period can be used as the basis total And the sum of the actual powers P total ' obtaining a calibration coefficient η, for example, the calibration coefficient η is calculated as formula five: η = P total '/P total . Estimating power P of each processor core according to calibration coefficient eta m Calibrating to obtain the calibrated power P of each processor core m '。
Wherein, the value of η may be a value greater than or equal to 1, or may be a value less than 1.
In some embodiments, when the calibration coefficient η is obtained, the actual power sum P may be accounted for total ' is the estimated power sum P total Eta times of. Similarly, the actual power of each processor core may be considered to be approximately the estimated power P of the corresponding processor core m Eta times of. Thus, the estimated power P of each processor core is calibrated with a calibration coefficient η m The calibrated power P of each processor core can be obtained m ', the calibration power P m ' relative estimated Power P m The actual power of each processor core can be reflected more accurately. Thus, the calibrated power P for each processor core m ' can be calculated as formula six: p m '＝η*P m . That is, the calibration power P of each processor core m ' is the estimated power P of the corresponding processor core m Eta times of.
For example, the calibration factor is 1.1, i.e., the actual power sum is 1.1 times the estimated power sum. Suppose estimated power P of the m-th processor core m At 5w, the actual power of the mth processor core is considered to be about 1.1 times the estimated power, and therefore, the calibration power P of the mth processor core is determined according to the formula six m ' is 5.5w. This calibration power of 5.5w is closer to the actual power of the mth processor core.
Step 304 may be performed by the frequency controller 213.
305. And adjusting the frequency and the voltage of each processor core according to the calibration power of each processor core.
The frequency controller 213 may send the resulting calibrated power for each processor core to the power consumption monitor 211 for each processor core. Each power consumption monitor 211 may adjust the frequency and voltage of the corresponding processor core based on the resulting calibration power.
Therefore, when the estimated power of each processor core of the multi-core processor is obtained, the estimated power of each processor core can be calibrated according to the relative relation between the total actual power of the plurality of processor cores and the total estimated power of the plurality of processor cores, so that the calibrated power of each processor core can reflect the actual power of each processor core more accurately, the error between the estimated power and the actual power of each processor core estimated for the multi-core processor can be reduced, and more efficient power consumption management is realized. For example, when the estimated power of the processor core is smaller than the actual power and the error between the estimated power and the actual power is larger, the processor can continue to control the processor core to operate, but the actual power may already reach the power consumption limit of the overcurrent control, and when the calibrated estimated power is obtained by using the method, the actual power of the processor core can be effectively prevented from reaching the power consumption limit; when the estimated power of the processor core is larger than the actual power, the estimated power of the processor core is excessively estimated, but the actual power does not reach the estimated power value, so that more power margins are unused.
The above steps 301-305 may occur for calibration of the estimated power of each processor core in the chip when the chip has been applied to the terminal device.
Considering that the power consumption characterizing signal selected for each processor core may not cover all power consumption events of the processor core, the base power of each processor core may also be considered in calculating the estimated power of each processor core. The base power may be understood as the power consumed by each processor core when the at least one power consumption characterizing signal of each processor core is not in an active state. The base power may be obtained during pre-silicon simulation of the chip. Thus, in some embodiments, prior to step 301, a pre-silicon simulation of the chip may be performed to obtain the base power of the multiple processor cores. Therefore, before step 301, as shown in fig. 4, the method may further include:
401. and determining a power consumption characterization signal corresponding to each processor core and a test case used in simulation.
In some embodiments, when selecting the power consumption characterization signal, the selection should be performed based on a principle of reducing the number of signals as much as possible on the basis of covering all power consumption scenes.
In some embodiments, the power consumption characterizing signal may be selected from the following criteria: clock gating signals controlling a plurality of registers; signals that are of a characteristic significance to a power consumption event, such as transmit signals of a transmit queue.
In some embodiments, the test case selection needs to cover all power consumption scenarios that may occur in principle. Once the power consumption scene coverage of the test case is incomplete, the power consumption coefficient obtained by fitting may deviate from the true value too much.
Step 401 may be performed by a designer.
402. And acquiring data points corresponding to each processor core when the processor runs the test case, wherein the data points comprise activity coefficients corresponding to a plurality of power consumption characterization signals of each processor core and estimated power of each processor core.
In some embodiments, the data points used by each processor core to fit the base power may be obtained by running a test case through PTPX (prime-time PX) simulation. For the mth processor core, the data point includes activity coefficients corresponding to the n power consumption characterization signals for the mth processor core: c 0 、C 1 、C 2 …C n And an estimated power P corresponding to the mth processor core m ”。
In some embodiments, step 402 may be performed by the power consumption monitor 211 for each processor core.
403. And performing linear regression fitting according to the data points of each processor core to obtain the power consumption coefficient and the basic power of each processor core.
For the mth processor core, according to the activity coefficients corresponding to the n power consumption characterization signals of the mth processor core: c 0 、C 1 、C 2 …C n And performing linear regression fitting on the estimated power corresponding to the mth processor core to obtain a power consumption coefficient W corresponding to the mth processor core 0 、W 1 、W 2 …W n And a foundationAnd (4) power B.
Namely, while linear regression fitting is carried out to obtain the power consumption coefficient, the basic power B corresponding to each processor core can also be obtained through fitting. For a processor core, the base power can also be understood as the power consumed by n power consumption characterization signals of the processor core when the n power consumption characterization signals are not turned over or are in a low level state in a preset period.
When the power consumption characterization signal selected for each processor core can cover all power consumption events of the processor core, the value of B is 0, and therefore when the basic power is obtained, the estimated power of each processor core can be determined according to the active power of each processor core and the basic power of each processor core, and the estimated power can reflect the actual power of the processor core more accurately. That is, the formula one in step 301 may be replaced with:
P m ＝C 0 W 0 +C 1 W 1 +C 2 W 2 +…+C n W n +B m ，B m and the base power of the mth processor core in a preset period is represented.
In some embodiments, step 403 may be performed by the power consumption monitor 211 for each processor core.
If the power consumption coefficient and the base power obtained by performing the pre-silicon simulation in steps 401 to 403 are obtained, the power consumption coefficient may be calibrated once after silicon. The calibration at this time may be calibration of the power consumption coefficient when the chip is not yet applied to an actual terminal device. The calibration of the power consumption coefficients may occur before step 301 and after step 403, that is, after the power consumption coefficient and the base power corresponding to each processor core are obtained through simulation before silicon, and before the estimated power of the processor cores is calibrated, the power consumption coefficients of the processor cores are calibrated.
Thus, after step 403, the method further comprises step 404:
404. and calibrating the power consumption coefficient of each processor core.
The calibration is similar to the principle of obtaining the power consumption coefficient in steps 401 to 403.
In the application, the influence caused by the error of the power consumption coefficient of the simulation before the silicon and the simulation after the silicon can be eliminated by calibrating the power consumption coefficient after the silicon.
In the embodiment of the present application, after step 305, that is, after the estimated power is calibrated, the power consumption coefficient may also be continuously calibrated, where the calibration of the power consumption coefficient is when the chip is applied to the terminal device. As shown in fig. 5. Accordingly, the method may further comprise:
306. and adjusting the power consumption coefficient of at least one power consumption characterization signal of each processor core according to the actual power sum of the plurality of processor cores and the activity coefficient of at least one power consumption characterization signal of each processor core.
It can also be understood that the power consumption coefficient of each processor core is calibrated according to the sum of the actual power of the plurality of processor cores and the activity coefficient corresponding to each processor core.
In some embodiments, the period for calibrating the consumption coefficient may be greater than the preset period for calibrating the estimated power described above. For example, when the period of the pfc is the first period, the first period may be a sum of time lengths of a plurality of preset periods.
In some embodiments, the plurality of processor cores of the processor core power plane 21 may be taken as a whole, i.e. at each first cycle the real power sum P of the plurality of processor cores may be utilized total ' and a coefficient of activity C of power consumption characterizing signals of a plurality of processor cores mn Performing linear regression fitting to obtain a power consumption coefficient W corresponding to each power consumption characterization signal mn And a base power B'. C mn And the activity coefficient of the nth power consumption characterization signal representing the mth processor core. W mn And the power consumption coefficient of the nth power consumption characterization signal of the mth processor core is represented. B' is the sum of the base powers of the plurality of processor cores in the first cycle.
At this time, P total '、C mn And W mn The relationship of (c) can be expressed as:
P total '＝C 00 W 00 +C 01 W 01 +C 02 W 02 +…+C 0n W 0n +C 10 W 10 +C 11 W 11 +C 12 W 12 +…+C 1n W 1n +…+C m0 W m0 +C m1 W m1 +C m2 W m2 +…+C mn W mn +B'。
that is, P can be paired total '、C 00 、C 01 、C 02 …C 0n 、C 10 、C 11 、C 12 …C 1n …C m0 、C m1 、C m2 …C mn Performing linear regression fitting to obtain W 00 、W 01 、W 02 …W 0n 、W 10 、W 11 、W 12 …W 1n …W m0 、W m1 、W m2 …W mn And B'.
In some embodiments, the power consumption monitoring unit 211 corresponding to each processor core may obtain the activity coefficient C of the corresponding processor core mn And C is mn Sent to the frequency controller 213, and the frequency controller 213 processes the data according to the activity coefficient C mn And the actual power sum P obtained in step 303 total ' obtaining coefficient of Power consumption W mn 。
307. And determining the estimated power of each processor core in the next preset period according to the calibrated power consumption coefficient.
Therefore, the power consumption coefficient can be calibrated in real time according to the power consumption data of the chip during real-time working, and the more accurate estimated power of each processor core can be calculated according to the power consumption coefficient obtained through real-time calibration.
The method of the embodiment of the present application is described in detail above with reference to fig. 3, 4 and 5. A block diagram of a computing system of an embodiment of the present application is described below in conjunction with fig. 6. FIG. 6 illustrates a block diagram of a computing system 100 according to an embodiment of the present application.
Computing system 60 may include one or more Central Processing Units (CPUs) or processors 602-1 through 602-p (which may be referred to herein as "processors 602" or "processor 602"). The processor 602 may communicate via a bus (or interconnection network) 604. The processors 602 may include a general purpose processor, a network processor (that processes data communicated over a computer network 603), or other types of a processor (including a Reduced Instruction Set Computer (RISC) processor or a Complex Instruction Set Computer (CISC)). Further, the processors 602 may have a single or multiple core design. The processors 602 with a multiple core design may integrate different types of processor cores onto the same Integrated Circuit (IC) die. Further, the processors 602 with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors. In an embodiment, the one or more processors 602 may be the same as or similar to the processors of fig. 2.
The computing system 60 of the present application may also include a chipset 606. A chipset 606 may also communicate with the bus 604. The chipset 606 may include a Graphics Memory Controller Hub (GMCH) 608. The GMCH 608 may include a memory controller 110 that communicates with a memory 112. Memory 112 may store data, including sequences of instructions that are executed by processor 602, or any other device included in computing system 60. In one embodiment of the present application, the memory 112 may include one or more volatile storage (or memory) devices such as Random Access Memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Non-volatile memory, such as a hard disk, may also be used. Other devices may communicate via the bus 604, such as multiple CPUs and/or multiple system memories.
The GMCH 608 may also include a graphics interface 114 and a display (not shown) in communication with the graphics accelerator 116. In an embodiment of the application, a display (e.g., a flat-panel display, a cathode-ray tube (CRT), a projection screen, etc.) may communicate with the graphics interface 114 through, for example, a signal converter that converts a digital representation of an image stored in a storage device (e.g., video memory or system memory) into display signals that are interpreted and displayed by the display. The display signals generated by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display.
The computing system 60 of the present application may also include an input/output controller hub (ICH) 120, the ICH 120 may provide an interface to I/O devices that communicate with the computing system 60. The ICH 120 may communicate with a bus 122 through a Peripheral Component Interconnect (PCI) bridge 124, such as a Peripheral Component Interconnect (PCI) bridge, a Universal Serial Bus (USB) controller, or other types of Peripheral bridges or controllers. The peripheral bridge 124 may provide a data path between the processor 602 and peripherals. In addition, multiple buses 122 may communicate with the ICH 120.
In addition, the bus 122 may also communicate with an audio device 126, one or more hard disk drives 128, and one or more network interface devices 130 (which communicate with a computer network 603).
Through the description of the above embodiments, those skilled in the art will understand that, for convenience and simplicity of description, only the division of the above functional modules is used as an example, and in practical applications, the above function distribution may be completed by different functional modules as needed, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical functional division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another device, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may be one physical unit or a plurality of physical units, that is, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partially contributed to by the prior art, or all or part of the technical solutions may be embodied in the form of a software product, where the software product is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (18)
- A method of measuring power of a processor core, comprising:determining the estimated power sum of a plurality of processor cores contained in a processor according to the estimated power of each processor core in the processor;determining a sum of actual power of a plurality of processor cores in the processor;and calibrating the estimated power of each processor core according to the estimated power sum and the actual power sum to obtain the calibrated power of each processor core.
- The method of claim 1, further comprising:and adjusting the frequency and the voltage of each processor core according to the calibration power of each processor core.
- The method of claim 1 or 2, wherein the calibrating the estimated power of each processor core according to the estimated power sum and the actual power sum comprises:determining a calibration coefficient according to the estimated power sum and the actual power sum;and calibrating the estimated power of each processor core according to the calibration coefficient.
- The method according to any one of claims 1-3, wherein determining the estimated power sum of the plurality of processor cores included in the processor according to the estimated power of each processor core in the processor comprises:determining an estimated power sum of the plurality of processor cores according to the estimated power of each processor core in the processor and the static power of the power domains of the plurality of processor cores;the static power of the power domains of the processor cores refers to power consumption generated by leakage current of the power domains of the processor cores.
- The method of any of claims 1-4, wherein prior to determining the estimated power sum for the plurality of processor cores, the method further comprises:an estimated power for each processor core is determined.
- The method of claim 5, wherein determining the estimated power for each processor core comprises:and determining an estimated power for each processing core based on the active power of each processor core and a base power of each processor core, wherein the active power is indicative of the power consumed by at least one power consumption characterizing signal of each processing core when in an active state, and the base power is indicative of the power consumed by at least one power consumption characterizing signal of each processing core when not in the active state.
- The method of claim 6, wherein the active power of each processor core is determined by:and obtaining the active power according to the activity coefficient of at least one power consumption characterization signal of each processor core and the power consumption coefficient of at least one power consumption characterization signal, wherein the activity coefficient of each power consumption characterization signal is used for reflecting the coefficient of each power consumption characterization signal in the active state, and the power consumption coefficient of each power consumption characterization signal is used for reflecting the power consumption consumed by each power consumption characterization signal in the active state.
- The method of claim 7, further comprising:and adjusting the power consumption coefficient of at least one power consumption characterization signal of each processor core according to the actual power sum and the activity coefficient of at least one power consumption characterization signal of each processor core.
- An apparatus to measure processor core power, comprising a power consumption monitor and a frequency controller, wherein:the frequency controller is used for determining the total estimated power of a plurality of processor cores contained in the processor according to the estimated power of each processor core in the processor obtained by the power consumption monitor;the frequency controller is further used for determining the actual power sum of a plurality of processor cores in the processor;the frequency controller is further configured to calibrate the estimated power of each processor core according to the estimated power sum and the actual power sum to obtain a calibrated power of each processor core.
- The apparatus of claim 9, wherein the frequency controller is further configured to:and adjusting the frequency and the voltage of each processor core according to the calibration power of each processor core.
- The apparatus of claim 9 or 10, wherein the frequency controller is configured to:determining a calibration coefficient according to the estimated power sum and the actual power sum;and calibrating the estimated power of each processor core according to the calibration coefficient.
- The apparatus of any of claims 9-11, wherein the frequency controller is configured to:determining an estimated power sum of the plurality of processor cores according to the estimated power of each processor core in the processor and the static power of the power domains of the plurality of processor cores;wherein the static power of the power domains of the plurality of processor cores refers to power consumption generated by leakage current of the power domains of the plurality of processor cores.
- The apparatus of any of claims 9-12, wherein the power consumption monitor is to:an estimated power for each processor core is determined.
- The apparatus of claim 13, wherein the power consumption monitor is to:determining an estimated power of each processor core from the active power of each processing core and the base power of each processor core;wherein the active power is indicative of power consumed by the at least one power consumption characterizing signal of each processing core when in an active state, and the base power is indicative of power consumed by each processor core when the at least one power consumption characterizing signal of each processing core is not in the active state.
- The apparatus of claim 14, wherein the power consumption monitor is to:and obtaining the active power according to the activity coefficient of at least one power consumption characterization signal of each processor core and the power consumption coefficient of at least one power consumption characterization signal, wherein the activity coefficient of each power consumption characterization signal is used for reflecting the coefficient of each power consumption characterization signal in the active state, and the power consumption coefficient of each power consumption characterization signal is used for reflecting the power consumption consumed by each power consumption characterization signal in the active state.
- The apparatus of claim 15, wherein the frequency controller is further configured to:and adjusting the power consumption coefficient of at least one power consumption characterization signal of each processor core according to the actual power sum and the activity coefficient of at least one power consumption characterization signal of each processor core.
- A computer-readable storage medium, comprising a program or instructions, which, when executed by a processor, performs a method according to any one of claims 1 to 8.
- A computer program product, characterized in that it causes an electronic device to perform the method according to any of claims 1 to 8, when the computer program product is run on a computer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/079956 WO2021184248A1 (en) | 2020-03-18 | 2020-03-18 | Method and device for measuring power of processor cores |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115298636A true CN115298636A (en) | 2022-11-04 |
Family
ID=77768388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080098654.6A Pending CN115298636A (en) | 2020-03-18 | 2020-03-18 | Method and device for measuring power of processor core |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115298636A (en) |
| WO (1) | WO2021184248A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220079196A (en) * | 2020-12-04 | 2022-06-13 | 삼성전자주식회사 | Integrated circuit performing dynamic voltage and frequency scaling operation and operating method thereof |
| CN114721908B (en) * | 2022-04-11 | 2022-12-06 | 摩尔线程智能科技(北京)有限责任公司 | On-chip power consumption control circuit, chip and power consumption control method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101177125B1 (en) * | 2005-06-11 | 2012-08-24 | 엘지전자 주식회사 | Method and apparatus for implementing hybrid power management mode in a multi-core processor |
| US8892931B2 (en) * | 2009-10-20 | 2014-11-18 | Empire Technology Development Llc | Power channel monitor for a multicore processor |
| US8631256B2 (en) * | 2010-12-22 | 2014-01-14 | Via Technologies, Inc. | Distributed management of a shared power source to a multi-core microprocessor |
| US9250682B2 (en) * | 2012-12-31 | 2016-02-02 | Intel Corporation | Distributed power management for multi-core processors |
-
2020
- 2020-03-18 CN CN202080098654.6A patent/CN115298636A/en active Pending
- 2020-03-18 WO PCT/CN2020/079956 patent/WO2021184248A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021184248A1 (en) | 2021-09-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5075196B2 (en) | Leakage power estimation | |
| US20200401201A1 (en) | Dynamic Power Consumption Estimation Method, Apparatus, and System | |
| US8707060B2 (en) | Deterministic management of dynamic thermal response of processors | |
| US9563254B2 (en) | System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time | |
| CN115298636A (en) | Method and device for measuring power of processor core | |
| US8260474B2 (en) | Sensor-based thermal specification enabling a real-time metric for compliance | |
| US20110291746A1 (en) | Realtime power management of integrated circuits | |
| US20140195828A1 (en) | Dynamically measuring power consumption in a processor | |
| US10963028B2 (en) | System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time | |
| US20120089856A1 (en) | Method and apparatus for on-demand power management | |
| US9483092B2 (en) | Performance state boost for multi-core integrated circuit | |
| US20130339777A1 (en) | Microprocessor-assisted auto-calibration of voltage regulators | |
| US20110078473A1 (en) | Latency based platform coordination | |
| WO2021073130A1 (en) | Frequency modulation method and apparatus for processor, and computing device | |
| US20220413576A1 (en) | Adaptive On-Chip Digital Power Estimator | |
| JP2013539571A (en) | Current and power management in computer systems | |
| US11934245B2 (en) | Microcontroller energy profiler | |
| CN116818123A (en) | Method and device for detecting chip node temperature and electronic equipment | |
| CN116680131A (en) | Server test system, server test method, electronic device, and storage medium | |
| US20230079292A1 (en) | Method, apparatus, and system for calibrating a processor power level estimate | |
| US20210096906A1 (en) | Interrupt control apparatus, interrupt control method, and computer readable medium | |
| US11941396B2 (en) | Current variation slope control method for multi-core processor, control device and medium | |
| WO2021120015A1 (en) | Power limit determination method and apparatus | |
| JP7446536B1 (en) | Statistical value calculation device, propagation delay measurement system, statistical value calculation method, and statistical value calculation program | |
| US10896276B2 (en) | Timing esimation method and simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |