CN114709299B - A vertical series structure high voltage chip and its manufacturing method - Google Patents

A vertical series structure high voltage chip and its manufacturing method Download PDF

Info

Publication number
CN114709299B
CN114709299B CN202210210851.3A CN202210210851A CN114709299B CN 114709299 B CN114709299 B CN 114709299B CN 202210210851 A CN202210210851 A CN 202210210851A CN 114709299 B CN114709299 B CN 114709299B
Authority
CN
China
Prior art keywords
layer
epitaxial wafer
bonding
substrate
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210210851.3A
Other languages
Chinese (zh)
Other versions
CN114709299A (en
Inventor
贾钊
窦志珍
郭文辉
杨琪
胡家辉
金从龙
顾伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Zhao Chi Semiconductor Co Ltd
Original Assignee
Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Zhao Chi Semiconductor Co Ltd filed Critical Jiangxi Zhao Chi Semiconductor Co Ltd
Priority to CN202210210851.3A priority Critical patent/CN114709299B/en
Publication of CN114709299A publication Critical patent/CN114709299A/en
Application granted granted Critical
Publication of CN114709299B publication Critical patent/CN114709299B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/813—Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/816—Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H10H20/8162—Current-blocking structures

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thyristors (AREA)

Abstract

本发明提供一种垂直串联结构高压芯片及其制作方法，所述方法包括：生长出PN区处均具有高掺杂层的多个外延片，其中外延片中靠近衬底的为第一高掺杂层，远离衬底的为第二高掺杂层；将外延片中第二高掺杂层与硅片进行临时键合；将临时键合后的外延片中的衬底进行去除至露出第一高掺杂层；将其中一衬底去除后的外延片与另一外延片进行等离子轰击活化，且将衬底去除后的外延片中第一高掺杂层与另一外延片中第二高掺杂层相对贴合，并放入键合机进行键合；将键合后的外延片解除临时键合；将解除临时键合后的外延片进行芯片制作工艺，直至制作完成得到高压芯片。本发明解决了现有高压芯片工艺要求高的问题。

The present invention provides a vertical series structure high-voltage chip and a manufacturing method thereof, the method comprising: growing a plurality of epitaxial wafers each having a high-doping layer at a PN region, wherein the epitaxial wafer close to the substrate is the first high-doping layer, and the epitaxial wafer far from the substrate is the second high-doping layer; temporarily bonding the second high-doping layer in the epitaxial wafer to a silicon wafer; removing the substrate in the epitaxial wafer after temporary bonding until the first high-doping layer is exposed; performing plasma bombardment activation on the epitaxial wafer after one substrate is removed and the other epitaxial wafer, and relatively fitting the first high-doping layer in the epitaxial wafer after the substrate is removed and the second high-doping layer in the other epitaxial wafer, and placing them in a bonding machine for bonding; releasing the temporary bonding of the bonded epitaxial wafer; performing a chip manufacturing process on the epitaxial wafer after the temporary bonding is released, until the manufacturing is completed to obtain a high-voltage chip. The present invention solves the problem of high process requirements of existing high-voltage chips.

Description

High-voltage chip with vertical series structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of photoelectricity, in particular to a high-voltage chip with a vertical series structure and a manufacturing method thereof.
Background
In the LED chip industry, high-voltage chips are a new variety, and a common way is to connect packaged low-power LED chips in series, or to integrate the LED chips in series during the manufacture of the LED chips.
The high-voltage chip formed by serially connecting the chips at the packaging end has larger volume, and the high-voltage chip integrated by serially connecting the LED chip ends is a small chip, and achieves the function of the high-voltage chip by transversely serially connecting each electrode, however, the method has higher requirements on the slotting process, the connecting electrode and the insulating effect of the chip ends, and meanwhile, the problem that the composite efficiency of the traditional transversely serially connected high-voltage chip is slightly low is solved.
Disclosure of Invention
Based on the above, the invention aims to provide a high-voltage chip with a vertical series structure and a manufacturing method thereof, so as to fundamentally solve the problem of high process requirements of the existing high-voltage chip.
According to the embodiment of the invention, the manufacturing method of the high-voltage chip with the vertical series structure comprises the following steps:
A plurality of epitaxial wafers with high-doped layers are grown at PN regions, wherein a first high-doped layer is close to the substrate in the epitaxial wafers, and a second high-doped layer is far away from the substrate;
temporarily bonding the second high-doped layer in the epitaxial wafer with the silicon wafer;
removing the substrate in the epitaxial wafer after temporary bonding until the first high-doped layer is exposed;
Carrying out plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer, relatively attaching a first high-doped layer in the epitaxial wafer with the substrate removed and a second high-doped layer in the other epitaxial wafer, and bonding by a bonding machine;
Removing temporary bonding of the bonded epitaxial wafer;
and (3) carrying out a chip manufacturing process on the epitaxial wafer after the temporary bonding is removed until the manufacturing is completed to obtain the high-voltage chip.
In addition, the method for manufacturing the high-voltage chip with the vertical series structure according to the embodiment of the invention can also have the following additional technical characteristics:
Further, before the step of performing the chip manufacturing process on the epitaxial wafer after temporary bonding removal, at least one of the following steps is performed:
Carrying out ion bombardment activation on the epitaxial wafer after the removal of the other substrate and the epitaxial wafer after the temporary bonding is removed, relatively attaching a first high doping layer in the epitaxial wafer after the removal of the substrate and a second high doping layer in the epitaxial wafer after the temporary bonding is removed, and putting the epitaxial wafer into a bonding machine for bonding again;
and (5) removing the temporary bonding of the epitaxial wafer after the re-bonding.
Further, before the step of temporarily bonding the bonded epitaxial wafer, at least one of the following steps is executed:
Removing the substrate in the bonded epitaxial wafer until the first high-doped layer is exposed;
And carrying out plasma bombardment activation on the epitaxial wafer after bonding and removing the substrate and the other epitaxial wafer, relatively attaching the first high-doped layer in the epitaxial wafer after bonding and removing the substrate and the second high-doped layer in the other epitaxial wafer, and putting the epitaxial wafer into a bonding machine for bonding.
Further, the step of temporarily bonding the second high doped layer in the epitaxial wafer to the silicon wafer includes:
waxing the surface of the second high doping layer and/or the surface of the silicon wafer in the epitaxial wafer;
And (3) aligning the epitaxial wafer and the silicon wafer, and placing the epitaxial wafer and the silicon wafer into a temporary bonding machine for pressure bonding, wherein the bonding pressure is 3000-6000 kgf, and the temporary bonding temperature is determined according to the temperature of a used wax hot melting flow point.
Further, the step of performing plasma bombardment activation on the epitaxial wafer after removing the substrate and the other epitaxial wafer comprises the following steps:
Performing plasma bombardment activation on the epitaxial wafer after the substrate is removed and another epitaxial wafer by using a plasma cleaning machine, wherein bombardment ions are Ar ions, and the bombardment time is 5-20 min;
The bonding pressure of bonding the first high-doped layer in the epitaxial wafer after the substrate is removed and the second high-doped layer in the other epitaxial wafer is 12000kgf, the bonding time is 60-120 min, and the bonding temperature is determined according to the temperature that the used wax cannot flow through hot melting.
Further, the doping concentration of the first high-doped layer and the second high-doped layer in the grown epitaxial wafer is larger than 1e19, and the thickness reaches 5000A.
Further, the step of growing the plurality of epitaxial wafers each having the high-doped layer at the PN region further comprises:
carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt;
And polishing the second highly doped layer in the epitaxial wafer after the organic cleaning until the thickness is more than or equal to 50A and less than or equal to 100A.
Further, the step of removing the substrate in the temporarily bonded epitaxial wafer until the first high-doped layer is exposed includes:
Removing the substrate in the epitaxial wafer after temporary bonding;
And polishing the first highly doped layer exposed in the epitaxial wafer after the substrate is removed until the thickness is more than or equal to 50A and less than or equal to 100A.
According to an embodiment of the invention, a high-voltage chip with a vertical series structure comprises:
A GaAs substrate, a buffer layer, a stop layer and an epitaxial structure which are stacked on the GaAs substrate in sequence, wherein the epitaxial structure is formed by repeatedly stacking at least two times;
the epitaxial structure comprises a high-doped N-type contact layer, an N-type transition layer, an N-type current expansion layer, an N-type limiting layer, an N-type blocking layer, a multi-quantum well layer, a P-type blocking layer, a P-type limiting layer, a P-type transition layer and a high-doped P-type current expansion layer which are stacked in sequence.
In addition, the high-voltage chip with the vertical series structure according to the embodiment of the invention can also have the following additional technical characteristics:
The buffer layer is a GaAs layer, the stop layer is a GaInP layer, the highly doped N-type contact layer is a GaAs layer, the N-type transition layer is a GaInP layer, the N-type current expansion layer is an AlGaInP layer, the N-type limiting layer is an AlInP layer, the N-type blocking layer is an AlGaInP layer, the P-type limiting layer is an AlInP layer, the P-type transition layer is an AlGaInP layer, and the highly doped P-type current expansion layer is a GaP layer;
The doping concentration of the high-doped N-type contact layer and the high-doped P-type current expansion layer is larger than 1e19, and the thickness is larger than or equal to 50A and smaller than or equal to 100A.
Compared with the prior art, the method has the advantages that the epitaxial layer can be transferred to the silicon wafer by adopting temporary bonding, the epitaxial layer is prevented from being broken, the next bonding process is convenient, and the multilayer epitaxial wafer can be connected in series in the vertical direction by adopting a vertical bonding mode, so that the high-voltage chip with a vertical structure is formed, the area of the chip is greatly reduced, the difficult problems of slotting the chip, growing an insulating layer and manufacturing a connecting electrode in the prior art are solved, and the problem of high requirement of the conventional high-voltage chip process is solved. Meanwhile, the PN region of the epitaxial wafer is subjected to high doping treatment, so that a tunneling junction can be formed after the epitaxial wafer is bonded, carriers can longitudinally migrate through a tunneling effect, the chip composite efficiency is improved, and the problem that the high-voltage chip with a transverse serial structure is slightly low in composite efficiency is solved.
Drawings
FIG. 1 is a flow chart of a method for fabricating a vertical series structure high voltage chip according to a first embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating a vertical series structure high voltage chip according to a second embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a vertical series structure high voltage chip according to a third embodiment of the present invention;
FIG. 4 is a schematic diagram of a vertical series structure high voltage chip according to a fourth embodiment of the present invention;
the following detailed description will further illustrate the invention with reference to the above-described drawings.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1, a method for manufacturing a vertical serial structure high voltage chip according to a first embodiment of the present invention is shown, and the method specifically includes steps S01-S05.
And step S01, a plurality of epitaxial wafers with high-doped layers are grown at PN regions, wherein a first high-doped layer close to the substrate and a second high-doped layer far from the substrate are arranged in the epitaxial wafers.
In one embodiment of the present invention, the epitaxial wafer may be a common epitaxial wafer in the prior art, and the P layer and the N layer in the epitaxial wafer are required to be subjected to high doping treatment, and the doping concentration in the film layer required to be high doped is greater than 1e19, and the thickness reaches about 5000A (angstrom, 1a=10-10 m).
Specifically, in one example of the present invention, a red-yellow GaAs (gallium arsenide) epitaxial wafer is taken as an example, and the growth process of the red-yellow GaAs epitaxial wafer is shown, firstly, a double-sided polished N-type GaAs single wafer is taken as a substrate, then, an MOCVD (Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition) is adopted to sequentially deposit and grow a GaAs buffer layer, a GaInP (gallium indium phosphide) stop layer, an N-type GaAs contact layer, an N-type GaInP transition layer, an N-type AlGaInP (aluminum indium gallium phosphide) current expansion layer, an N-type AlInP (indium aluminum phosphide) limiting layer, an N-type AlGaInP blocking layer, an MQW multiple quantum well layer, a P-type AlGaInP blocking layer, a P-type AlGaInP limiting layer, a P-type AlGaInP transition layer, a P-type GaP (gallium phosphide) expansion current layer on the upper surface of the GaAs substrate, and finally, the red-yellow GaAs epitaxial wafer is obtained.
Specifically, the P layer and the N layer are both subjected to high doping treatment in the epitaxial wafer growth process, that is, the N-type GaAs contact layer and the P-type GaP extension current layer are both highly doped or heavily doped, and the doping concentration of the existing commonly doped N-type GaAs contact layer and P-type GaP extension current layer is approximately about 1e15 to 1e 18. Therefore, when the grown epitaxial wafer is a GaAs epitaxial wafer, the first highly doped layer close to the substrate is an N-type GaAs contact layer (i.e., gaAs layer), and the second highly doped layer far from the substrate is a P-type GaP extension current layer (i.e., gaP layer).
It should be noted that, in other examples of the present invention, the specific structure in the epitaxial wafer may be provided with more or less or different layers of different orders or different material compositions than the present example, which is provided according to actual use requirements, and is not limited herein specifically. However, the epitaxial wafer structure can be generally simplified into a substrate, an N-type high-doped layer, an N-layer, an MQW multiple quantum well layer, a P-layer and a P-type high-doped layer all the time, wherein the N-type high-doped layer is a GaAs layer and the P-type high-doped layer is a GaP layer.
It will be appreciated that in other embodiments of the invention, other types of substrates may be used to create corresponding epitaxial wafers, such as GaN (gallium nitride) epitaxial wafers, and that other types of substrates may be used, such as P-type substrates, such that generally simplified structures of P-type highly doped layers, P-layers, MQW multiple quantum well layers, N-layers, and N-type highly doped layers are grown on P-type substrates. At this time, the corresponding first high-doped layer close to the substrate is a P-type high-doped layer, and the second high-doped layer far away from the substrate is an N-type high-doped layer, so in the embodiment of the present invention, specific types and types of the first high-doped layer and the second high-doped layer are not explicitly indicated, and corresponding determination is performed according to the positional relationship with the substrate according to the actual production requirements, which is not limited herein.
Further, in the doping process, the N layer is usually doped with a doping impurity containing Si (silicon) or C (carbon), and the P layer is usually doped with a doping impurity containing Mg (magnesium) or Zn (zinc), specifically, for example, in the epitaxial growth, siH4 (silane) is introduced to dope the N layer, cp2Mg (magnesium-cyclopentadienyl, mg (C5H 5) 2) is introduced to dope the P layer.
Further, the step S01 further includes:
carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt;
And polishing the second highly doped layer in the epitaxial wafer after the organic cleaning until the thickness is more than or equal to 50A and less than or equal to 100A.
Specifically, the grown epitaxial wafer is subjected to organic cleaning, so that impurities and dirt on the surface of the epitaxial wafer can be removed, the purity of the surface of the epitaxial wafer is improved, and meanwhile, the second highly doped layer in the epitaxial wafer after organic cleaning is polished until the residual thickness of the polished second highly doped layer is greater than or equal to 50A and less than or equal to 100A, so that the purity and the flatness of the second highly doped layer are maintained, and a proper thickness dimension can be provided for subsequent bonding treatment.
And step S02, performing temporary bonding on the second high-doped layer in the epitaxial wafer and the silicon wafer.
The temporary bonding of the second high-doped layer in the epitaxial wafer and the silicon wafer can be realized through the following steps:
waxing the surface of the second high doping layer and/or the surface of the silicon wafer in the epitaxial wafer;
And (3) aligning the epitaxial wafer and the silicon wafer, and placing the epitaxial wafer and the silicon wafer into a temporary bonding machine for pressure bonding, wherein the bonding pressure is 3000-6000 kgf, and the temporary bonding temperature is determined according to the temperature of a used wax hot melting flow point.
Specifically, high-temperature wax is coated on the surface of a silicon wafer or an epitaxial wafer or both wafers, the silicon wafer and the epitaxial wafer are further aligned and placed into a temporary bonding machine for pressurizing and pressing, the temperature is mainly the flow point of the used temporary bonding wax, and the high-temperature wax can bear a certain temperature, for example, the temperature at the flow point of the high-temperature wax is 270 ℃, the temporary bonding temperature can be set to 250-260 ℃, the pressure is 3000 kgf-6000 kgf (kilogram-force), and the epitaxial wafer and the silicon wafer are temporarily bonded through the high-temperature wax.
It should be noted that, since the epitaxial layer of the epitaxial wafer after the substrate is removed is very thin, generally several micrometers or more than ten micrometers, after the substrate is removed, the epitaxial layer cannot effectively exist alone, and is easy to crack, at this time, the epitaxial layer can be effectively carried on the silicon wafer (or supported by the silicon wafer) through the temporary bonding action of the epitaxial wafer and the silicon wafer by the high-temperature wax, so that the epitaxial layer is prevented from being cracked by transferring the epitaxial layer to the silicon wafer, and the subsequent processes of substrate removal, bonding and the like can be conveniently and effectively performed.
And S03, removing the substrate in the epitaxial wafer after temporary bonding until the first high-doped layer is exposed.
The substrate in the epitaxial wafer after temporary bonding in step S02 can be effectively removed at this time by temporarily bonding the epitaxial wafer and the silicon wafer with high-temperature wax, and the substrate is usually removed by using ammonia hydrogen peroxide, wherein, as described above, a buffer layer and a stop layer may also exist between the substrate and the first highly doped layer, so that the substrate needs to be removed until the first highly doped layer is exposed, that is, the buffer layer and the stop layer need to be removed, so that the first highly doped layer is exposed.
Specifically, the step S03 further specifically includes:
Removing the substrate in the epitaxial wafer after temporary bonding;
And polishing the first highly doped layer exposed in the epitaxial wafer after the substrate is removed until the thickness is more than or equal to 50A and less than or equal to 100A.
That is, after the substrate is removed from the temporarily bonded epitaxial wafer until the first highly doped layer is exposed, polishing the exposed first highly doped layer until the residual thickness of the first highly doped layer is greater than or equal to 50A and less than or equal to 100A, so that the purity and the flatness of the first highly doped layer are maintained, and a proper thickness dimension is provided for the subsequent bonding process.
And S04, performing plasma bombardment activation on the epitaxial wafer with the removed substrate and the other epitaxial wafer, relatively attaching the first high-doped layer in the epitaxial wafer with the removed substrate to the second high-doped layer in the other epitaxial wafer, and bonding by a bonding machine.
Bonding refers to a technology that two pieces of homogeneous or heterogeneous semiconductor materials with clean surfaces and flat atomic levels are subjected to surface cleaning and activation treatment, are directly combined under certain conditions, and are bonded into a whole through Van der Waals force, molecular force and even atomic force.
In one embodiment of the present invention, the performing the plasma bombardment activation on the epitaxial wafer after the removal of the substrate and the other epitaxial wafer specifically includes performing the plasma bombardment activation on the epitaxial wafer after the removal of the substrate and the other epitaxial wafer by using a plasma cleaning machine, wherein the bombardment ion is Ar ion, and the bombardment time is 5-20 min.
The bonding pressure of bonding the first high-doped layer in the epitaxial wafer after the substrate is removed and the second high-doped layer in the other epitaxial wafer is 12000kgf, the bonding time is 60-120 min, and the bonding temperature is determined according to the temperature that the used wax cannot flow through hot melting.
Specifically, a plasma cleaning machine is used for carrying out plasma bombardment activation on the epitaxial wafer after the substrate is removed, which is obtained in the step S03, and the epitaxial wafer after the second high doping layer is polished in the step S01, and Ar ions bombard the two epitaxial wafers for 5-20 min at the moment, so that activation treatment is achieved. And then the first high doping layer in the epitaxial wafer after the substrate is removed, which is prepared in the step S03, and the second high doping layer in the epitaxial wafer after the second high doping layer is polished in the step S01 are relatively attached together and put into a bonding machine for bonding, at the moment, the bonding temperature is required to be controlled within the flowing and unbinding temperature of high-temperature wax which cannot melt the wax, for example, the flowing point temperature of the high-temperature wax is 270 ℃, at the moment, the bonding temperature can be set to 200 ℃, the pressure is 12000kgf, and the time is 60-120 min, so that the high-temperature wax is always in a solid state and still remains temporarily bonded with the silicon wafer, and the problem that the epitaxial wafer and the silicon wafer are unbinding due to the fact that the high-temperature wax is melted due to the overhigh bonding temperature is avoided.
At this time, after the epitaxial wafer after the substrate is removed is bonded with another epitaxial wafer, the bonding is performed so that a structure similar to a PN junction is formed, specifically, an N-layer structure of the epitaxial wafer after the substrate is removed, to which a first high doped layer (such as a GaAs layer in the example) belongs, and a P-layer structure of another epitaxial wafer, to which a second high doped layer (such as a GaP layer in the example) belongs, are formed, and GaAs layers in the N-layer and GaP layers in the P-layer are connected, and an original N-layer structure and an original P-layer structure are added to form a new PN junction. Therefore, an inter-band tunneling junction can be formed between a first high-doped layer in the epitaxial wafer after the substrate is removed and a second high-doped layer in the other epitaxial wafer, wherein the inter-band tunneling refers to the valence band of electrons from the p-type semiconductor layer, the forbidden band is passed, and finally the electrons reach the conduction band of the n-type semiconductor layer, at the moment, carriers can longitudinally migrate through the tunneling effect, and meanwhile, the characteristic of high doping in the embodiment of the invention is combined, so that the composite efficiency can be improved, and the problem that the composite efficiency of a high-voltage chip with a transverse serial structure is slightly low is solved.
And step S05, the bonded epitaxial wafer is subjected to temporary bonding.
After the epitaxial wafer in the step S04 is bonded, the temperature of the epitaxial wafer can be correspondingly increased, so that the high-temperature wax is changed from a solid state to a liquid state when the temperature reaches the flow point of the high-temperature wax, the temporary bonding between the silicon wafer and the epitaxial wafer is released or disconnected, the epitaxial wafer and the silicon wafer are separated, and the vertical serial connection process between the two epitaxial wafers is completed.
And step S06, performing a chip manufacturing process on the epitaxial wafer after temporary bonding is removed until the manufacturing is completed, and obtaining the high-voltage chip.
In the embodiment of the invention, the serial connection process of the epitaxial wafer with the vertical serial connection structure is completed, and the normal chip manufacturing process can be continued until the chip end is manufactured to obtain the high-voltage core. At this time, the epitaxial wafer is manufactured into N electrode, P electrode and the like through the processes of substrate removal, photoetching, etching, film plating, vapor plating, thinning and the like. It should be noted that, the main protection gist of the embodiment of the present invention is that the "epitaxial wafer" with a vertical series structure is obtained by the working procedure of the chip end, and the subsequent process steps such as electrode manufacturing and the common chip process are not different, so the detailed description is not made, and the detailed description can refer to any existing process steps for implementation specifically, and no specific limitation is made herein.
Therefore, the overall flow in the embodiment of the present invention is generally as follows:
And a step a, growing an epitaxial wafer, wherein the doping concentration of the PN region is required to reach at least 1e19 from the high doping concentration of the first high doping layer to the doping concentration of the second high doping layer, and the thickness of the PN region reaches about 5000A.
And b, carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and polishing a second highly doped layer of the epitaxial wafer, wherein the residual thickness of the polished second highly doped layer is less than or equal to 100A and more than or equal to 50A.
And c, temporarily bonding the polished epitaxial wafer with the second high-doped layer by using liquid high-temperature wax.
And d, removing the substrate of the temporarily-bonded epitaxial wafer until the first high-doped layer is exposed, polishing the exposed first high-doped layer, wherein the residual thickness of the polished first high-doped layer is less than or equal to 100A and more than or equal to 50A.
And e, performing plasma bombardment activation on the epitaxial wafer removed by the substrate in the step d and the epitaxial wafer polished in the step b, and then relatively attaching the first high doped layer in the epitaxial wafer removed by the substrate and the second high doped layer in the polished epitaxial wafer together, and putting the first high doped layer and the second high doped layer in the polished epitaxial wafer into a bonding machine for bonding.
Step f, the temporary bonding of the high-temperature wax is released from the bonded epitaxial wafer, so that the epitaxial wafer is separated from the silicon wafer;
And g, performing the conventional chip manufacturing process on the epitaxial wafer subjected to temporary bonding removal.
In summary, the method for manufacturing the vertical serial structure high-voltage chip in the embodiment of the invention can transfer the epitaxial layer onto the silicon wafer by adopting temporary bonding, prevent the epitaxial layer from being broken and facilitate the next bonding process, and can connect the epitaxial layers in series in the vertical direction by adopting a vertical bonding mode so as to form the vertical structure high-voltage chip, thereby greatly reducing the area of the chip and solving the difficult problems of slotting the chip, growing the insulating layer and manufacturing the connecting electrode, and further solving the problem of high requirement of the conventional high-voltage chip process. Meanwhile, the PN region of the epitaxial wafer is subjected to high doping treatment, so that a tunneling junction can be formed after the epitaxial wafer is bonded, carriers can longitudinally migrate through a tunneling effect, the chip composite efficiency is improved, and the problem that the high-voltage chip with a transverse serial structure is slightly low in composite efficiency is solved.
Example two
Referring to fig. 2, a method for manufacturing a vertical serial structure high voltage chip according to a second embodiment of the present invention is shown, and the method specifically includes steps S11 to S18.
And S11, growing a plurality of epitaxial wafers with high-doped layers at PN regions, wherein the epitaxial wafers are close to the substrate and are first high-doped layers, and the epitaxial wafers are far away from the substrate and are second high-doped layers.
And step S12, performing temporary bonding on the second high-doped layer in the epitaxial wafer and the silicon wafer.
And S13, removing the substrate in the epitaxial wafer after temporary bonding until the first high-doped layer is exposed.
And S14, performing plasma bombardment activation on the epitaxial wafer with the removed substrate and the other epitaxial wafer, relatively attaching the first high-doped layer in the epitaxial wafer with the removed substrate to the second high-doped layer in the other epitaxial wafer, and bonding by a bonding machine.
And S15, temporarily bonding the bonded epitaxial wafer.
The specific flow of the steps S11 to S15 is substantially the same as that of the foregoing embodiment, and the specific process may be described with reference to the foregoing embodiment, which is not specifically limited herein.
And S16, performing ion bombardment activation on the epitaxial wafer after the other substrate is removed and the epitaxial wafer after the temporary bonding is removed, relatively attaching a first high doping layer in the epitaxial wafer after the substrate is removed and a second high doping layer in the epitaxial wafer after the temporary bonding is removed, and putting the epitaxial wafer into a bonding machine for bonding again.
Wherein, the epitaxial wafer in step S15 exposes the polished second high doped layer after temporary bonding is released, and in step S12, a plurality of epitaxial wafers may be temporarily bonded to the corresponding silicon wafer, and the substrate in step S13 may be removed continuously. At this time, the epitaxial wafer in the step S15 and another epitaxial wafer removed by the substrate manufactured in the step S13 are subjected to ion bombardment activation, and bonding by a bonding machine is continued again, so that a tandem three-layer epitaxial structure can be obtained by bonding.
And S17, the temporary bonding of the epitaxial wafer after the re-bonding is released.
Accordingly, since the epitaxial wafer removed from the substrate obtained in step S13 is taken in step S16, the epitaxial wafer is temporarily bonded to the silicon wafer, and therefore, after the re-bonding in step S16 is completed, the temporary bonding of the re-bonded epitaxial wafer is also required to be released.
It should be noted that, the steps S16 and S17 are performed at least once, that is, when the steps S16 and S17 are performed only once, the bonding results in a tandem three-layer epitaxy structure. When steps S16 and S17 are repeated twice, a tandem four-layer epitaxial structure is obtained. That is, the high voltage chip with a series double layer is manufactured in the foregoing embodiment, and the high voltage chip with at least three layers and not limited to three layers is manufactured in the present embodiment. For example, how much to connect in series is set according to the power required, if a high voltage chip of 5W is required, 5 epitaxial structures of 1W can be connected in series, and five layers are required to be connected in series vertically, that is, step S16 and step S17 are required to be performed three times. It should be noted that the more the number of vertical series is, the more the problem of low composite efficiency is easy to occur, and the corresponding optimization of epitaxial wafer and chip design is required. Therefore, it sets the number of executions of steps S16 and S17 corresponding to the number of series required for actual use.
And S18, performing a chip manufacturing process on the epitaxial wafer subjected to temporary bonding release until the manufacturing is completed to obtain the high-voltage chip.
The specific flow of step S18 is substantially the same as that of the foregoing embodiment, and may be specifically described with reference to the foregoing embodiment, which is not specifically limited herein.
Therefore, the overall flow in the embodiment of the present invention is generally as follows:
And a step a, growing an epitaxial wafer, wherein the doping concentration of the PN region is required to reach at least 1e19 from the high doping concentration of the first high doping layer to the doping concentration of the second high doping layer, and the thickness of the PN region reaches about 5000A.
And b, carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and polishing a second highly doped layer of the epitaxial wafer, wherein the residual thickness of the polished second highly doped layer is less than or equal to 100A and more than or equal to 50A.
And c, temporarily bonding the polished epitaxial wafer with the second high-doped layer by using liquid high-temperature wax.
And d, removing the substrate of the temporarily-bonded epitaxial wafer until the first high-doped layer is exposed, polishing the exposed first high-doped layer, wherein the residual thickness of the polished first high-doped layer is less than or equal to 100A and more than or equal to 50A.
And e, performing plasma bombardment activation on the epitaxial wafer removed by the substrate in the step d and the epitaxial wafer polished in the step b, and then relatively attaching the first high doped layer in the epitaxial wafer removed by the substrate and the second high doped layer in the polished epitaxial wafer together, and putting the first high doped layer and the second high doped layer in the polished epitaxial wafer into a bonding machine for bonding.
Step f, the temporary bonding of the high-temperature wax is released from the bonded epitaxial wafer, so that the epitaxial wafer is separated from the silicon wafer;
step g, carrying out sub-bombardment activation on the epitaxial wafer removed from the substrate in the other step d and the epitaxial wafer subjected to temporary bonding removal in the step f, and relatively attaching a first high doping layer in the epitaxial wafer subjected to the substrate removal and a second high doping layer in the epitaxial wafer subjected to temporary bonding removal together, and putting the first high doping layer and the second high doping layer in a bonding machine for bonding again;
step h, the temporary bonding of the high-temperature wax is released from the epitaxial wafer after the re-bonding, so that the epitaxial wafer is separated from the silicon wafer;
And i, performing the conventional chip manufacturing process on the epitaxial wafer subjected to temporary bonding removal.
Example III
Referring to fig. 3, a method for manufacturing a vertical serial structure high voltage chip according to a third embodiment of the present invention is shown, and the method specifically includes steps S21 to S28.
And S21, growing a plurality of epitaxial wafers with high-doped layers at PN regions, wherein the epitaxial wafers are close to the substrate and are first high-doped layers, and the epitaxial wafers are far away from the substrate and are second high-doped layers.
And S22, temporarily bonding the second high-doped layer in the epitaxial wafer with the silicon wafer.
And S23, removing the substrate in the epitaxial wafer after temporary bonding until the first high-doped layer is exposed.
And S24, performing plasma bombardment activation on the epitaxial wafer with the removed substrate and the other epitaxial wafer, relatively attaching the first high-doped layer in the epitaxial wafer with the removed substrate to the second high-doped layer in the other epitaxial wafer, and bonding by a bonding machine.
The specific flow of the steps S11 to S24 is substantially the same as that of the foregoing embodiment, and the specific process may be described with reference to the foregoing embodiment, which is not specifically limited herein.
And S25, removing the substrate in the bonded epitaxial wafer until the first high-doped layer is exposed.
In the embodiment of the invention, the epitaxial wafer is bonded and temporarily bonded, and the epitaxial wafer has enough thickness to remove the substrate, so that the substrate in the bonded epitaxial wafer can be removed firstly, the first highly doped layer is exposed, and the first highly doped layer is polished until the residual thickness of the first highly doped layer is greater than or equal to 50A and less than or equal to 100A.
And S26, performing plasma bombardment activation on the epitaxial wafer and the epitaxial wafer after bonding and removing the substrate, relatively attaching the first high doped layer in the epitaxial wafer after bonding and removing the substrate and the second high doped layer in the epitaxial wafer, and placing the epitaxial wafer into a bonding machine for bonding.
In the embodiment of the present invention, since the substrate in the epitaxial wafer is removed to expose the first highly doped layer in step S25, the epitaxial wafer bonded and removed with the substrate and the epitaxial wafer polished by the second highly doped layer may be subjected to plasma bombardment activation and bonding treatment.
It should be noted that, the steps S25 and S26 are performed at least once, that is, when the steps S25 and S26 are performed only once, the bonding results in a tandem three-layer epitaxy structure. When steps S25 and S26 are repeated twice, a tandem four-layer epitaxy structure is obtained. That is, the high voltage chip with a series double layer is manufactured in the foregoing embodiment, and the high voltage chip with at least three layers and not limited to three layers is manufactured in the present embodiment. For example, how much to connect in series is set according to the power required, if a high voltage chip of 5W is required, 5 epitaxial structures of 1W can be connected in series, and five layers are required to be connected in series vertically, that is, step S25 and step S26 are required to be performed three times. It should be noted that the more the number of vertical series is, the more the problem of low composite efficiency is easy to occur, and the corresponding optimization of epitaxial wafer and chip design is required. Therefore, it sets the number of executions of steps S25 and 26 corresponding to the number of series required for actual use.
And step S27, the bonded epitaxial wafer is subjected to temporary bonding.
After the epitaxial wafers with the required layers are connected in series, the flow point of the high-temperature wax is reached by controlling the temperature, so that the high-temperature wax is changed from a solid state to a liquid state when the high-temperature wax is temporarily bonded, the temporary bonding between the silicon wafer and the epitaxial wafers is released or disconnected, the temporary bonding between the silicon wafer and the epitaxial wafers is finally released, the multilayer epitaxial wafers and the silicon wafer are separated, and the vertical series connection process among the epitaxial wafers is completed.
And step S28, performing a chip manufacturing process on the epitaxial wafer after temporary bonding is removed until the manufacturing is completed to obtain the high-voltage chip.
The specific flow of step S28 is substantially the same as that of the foregoing embodiment, and may be specifically described with reference to the foregoing embodiment, which is not specifically limited herein.
Therefore, the overall flow in the embodiment of the present invention is generally as follows:
And a step a, growing an epitaxial wafer, wherein the doping concentration of the PN region is required to reach at least 1e19 from the high doping concentration of the first high doping layer to the doping concentration of the second high doping layer, and the thickness of the PN region reaches about 5000A.
And b, carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and polishing a second highly doped layer of the epitaxial wafer, wherein the residual thickness of the polished second highly doped layer is less than or equal to 100A and more than or equal to 50A.
And c, temporarily bonding the polished epitaxial wafer with the second high-doped layer by using liquid high-temperature wax.
And d, removing the substrate of the temporarily-bonded epitaxial wafer until the first high-doped layer is exposed, polishing the exposed first high-doped layer, wherein the residual thickness of the polished first high-doped layer is less than or equal to 100A and more than or equal to 50A.
And e, performing plasma bombardment activation on the epitaxial wafer removed by the substrate in the step d and the epitaxial wafer polished in the step b, and then relatively attaching the first high doped layer in the epitaxial wafer removed by the substrate and the second high doped layer in the polished epitaxial wafer together, and putting the first high doped layer and the second high doped layer in the polished epitaxial wafer into a bonding machine for bonding.
And f, removing the substrate in the epitaxial wafer bonded in the step e until the first high-doped layer is exposed, polishing the exposed first high-doped layer, wherein the residual thickness of the polished first high-doped layer is less than or equal to 100A and more than or equal to 50A.
And g, performing plasma bombardment activation on the epitaxial wafer bonded and removed from the substrate in the step f and the epitaxial wafer polished in the step b, relatively attaching the first highly doped layer in the epitaxial wafer bonded and removed from the substrate and the second highly doped layer in the polished epitaxial wafer, and putting the epitaxial wafer into a bonding machine for bonding.
Step h, the temporary bonding of the high-temperature wax is released from the epitaxial wafer bonded in the step g, so that the epitaxial wafer is separated from the silicon wafer;
And i, performing the conventional chip manufacturing process on the epitaxial wafer subjected to temporary bonding removal.
Example IV
In another aspect, referring to fig. 4, a vertical serial structure high voltage chip according to a fourth embodiment of the present invention is obtained by manufacturing the vertical serial structure high voltage chip according to the manufacturing method in the foregoing method embodiment, where the vertical serial structure high voltage chip includes:
a GaAs substrate 100, a buffer layer 200, a stop layer 300, and an epitaxial structure 400 stacked in this order on the GaAs substrate 100, repeatedly at least twice;
The epitaxial structure 400 includes a highly doped N-type contact layer 401, an N-type transition layer 402, an N-type current spreading layer 403, an N-type confinement layer 404, an N-type barrier layer 405, a multiple quantum well layer 406, a P-type barrier layer 407, a P-type confinement layer 408, a P-type transition layer 409, and a highly doped P-type current spreading layer 410, which are stacked in order.
In one embodiment of the present invention, the buffer layer 200 is a GaAs layer, the stop layer 300 is a GaInP layer, the highly doped N-type contact layer 401 is a GaAs layer, the N-type transition layer 402 is a GaInP layer, the N-type current spreading layer 403 is an AlGaInP layer, the N-type confinement layer 404 is an AlInP layer, the N-type confinement layer 405 is an AlGaInP layer, the P-type confinement layer 407 is an AlGaInP layer, the P-type confinement layer 408 is an AlInP layer, the P-type transition layer 409 is an AlGaInP layer, the highly doped P-type current spreading layer 410 is a GaP layer, the doping concentrations of the highly doped N-type contact layer 401 and the highly doped P-type current spreading layer 410 are both greater than 1e19, and the thicknesses are both greater than or equal to 50A and less than or equal to 100A.
In summary, in the high-voltage chip with the vertical series structure in the embodiment of the invention, the multi-layer epitaxial wafer can be connected in series in the vertical direction by bonding in the vertical direction, so as to form the high-voltage chip with the vertical structure, greatly reduce the chip area and solve the difficult problems of slotting the chip, growing an insulating layer and manufacturing a connecting electrode, thereby solving the problem of high requirements of the existing high-voltage chip process. Meanwhile, the PN region of each epitaxial wafer is subjected to high doping treatment to obtain a high-doped N-type contact layer and a high-doped P-type current spreading layer, so that a tunneling junction can be formed after the epitaxial wafers are bonded, carriers can longitudinally migrate through a tunneling effect, the chip composite efficiency is improved, and the problem that the high-voltage chip composite efficiency of a transverse serial structure is slightly low is solved.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1.一种垂直串联结构高压芯片制作方法，其特征在于，所述方法包括：1. A method for manufacturing a vertical series structure high voltage chip, characterized in that the method comprises: 生长出PN区处均具有高掺杂层的多个外延片，其中外延片中靠近衬底的为第一高掺杂层，远离衬底的为第二高掺杂层；Growing a plurality of epitaxial wafers each having a high-doping layer at the PN region, wherein the epitaxial wafer close to the substrate is a first high-doping layer, and the epitaxial wafer far from the substrate is a second high-doping layer; 将外延片中第二高掺杂层与硅片进行临时键合；Temporarily bonding the second most highly doped layer in the epitaxial wafer to the silicon wafer; 将临时键合后的外延片中的衬底进行去除至露出第一高掺杂层；Removing the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed; 将其中一衬底去除后的外延片与另一外延片进行等离子轰击活化，且将衬底去除后的外延片中第一高掺杂层与另一外延片中第二高掺杂层相对贴合，并放入键合机进行键合；Plasma bombardment activation is performed on one epitaxial wafer after the substrate is removed and the other epitaxial wafer, and the first high-doped layer in the epitaxial wafer after the substrate is removed is relatively attached to the second high-doped layer in the other epitaxial wafer, and then placed in a bonding machine for bonding; 将键合后的外延片解除临时键合；Release the temporary bonding of the bonded epitaxial wafer; 将解除临时键合后的外延片进行芯片制作工艺，直至制作完成得到高压芯片。The epitaxial wafer after temporary bonding is released is subjected to chip manufacturing process until the high-voltage chip is completed. 2.根据权利要求1所述的垂直串联结构高压芯片制作方法，其特征在于，所述将解除临时键合后的外延片进行芯片制作工艺的步骤之前，还执行至少一次如下步骤：2. The method for manufacturing a vertical series structure high voltage chip according to claim 1, characterized in that before the step of performing a chip manufacturing process on the epitaxial wafer after releasing the temporary bonding, the following steps are performed at least once: 将另一衬底去除后的外延片与解除临时键合后的外延片进行离子轰击活化，且将衬底去除后的外延片中第一高掺杂层与解除临时键合后的外延片中第二高掺杂层相对贴合，并放入键合机进行再次键合；The epitaxial wafer after another substrate is removed and the epitaxial wafer after temporary bonding is released are activated by ion bombardment, and the first high-doped layer in the epitaxial wafer after the substrate is removed and the second high-doped layer in the epitaxial wafer after temporary bonding are relatively attached, and then put into a bonding machine for re-bonding; 将再次键合后的外延片解除临时键合。The epitaxial wafer that has been bonded again is released from temporary bonding. 3.根据权利要求1所述的垂直串联结构高压芯片制作方法，其特征在于，所述将键合后的外延片解除临时键合的步骤之前，还执行至少一次如下步骤：3. The method for manufacturing a vertical series structure high voltage chip according to claim 1, characterized in that before the step of releasing the temporary bonding of the bonded epitaxial wafer, the following steps are performed at least once: 将键合后的外延片中的衬底进行去除至露出第一高掺杂层；Removing the substrate in the bonded epitaxial wafer until the first highly doped layer is exposed; 将键合且去除衬底后的外延片与再一外延片进行等离子轰击活化，且将键合且去除衬底后的外延片中第一高掺杂层与再一外延片中第二高掺杂层相对贴合，并放入键合机进行键合。The epitaxial wafer after bonding and substrate removal and another epitaxial wafer are activated by plasma bombardment, and the first high-doped layer in the epitaxial wafer after bonding and substrate removal and the second high-doped layer in another epitaxial wafer are relatively attached and placed in a bonding machine for bonding. 4.根据权利要求1所述的垂直串联结构高压芯片制作方法，其特征在于，所述将外延片中第二高掺杂层与硅片进行临时键合的步骤包括：4. The method for manufacturing a vertical series structure high voltage chip according to claim 1, characterized in that the step of temporarily bonding the second highly doped layer in the epitaxial wafer to the silicon wafer comprises: 在外延片中第二高掺杂层表面和/或硅片表面进行涂蜡；Applying wax on the surface of the second high-doped layer in the epitaxial wafer and/or the surface of the silicon wafer; 将外延片和硅片对齐放入临时键合机加压键合，其中键合压力为3000kgf～6000kgf，临时键合温度根据所使用的蜡热熔流动点温度进行确定。The epitaxial wafer and the silicon wafer are aligned and placed in a temporary bonding machine for pressure bonding, wherein the bonding pressure is 3000kgf to 6000kgf, and the temporary bonding temperature is determined according to the hot melt flow point temperature of the wax used. 5.根据权利要求1所述的垂直串联结构高压芯片制作方法，其特征在于，所述将其中一衬底去除后的外延片与另一外延片进行等离子轰击活化的步骤包括：5. The method for manufacturing a vertical series structure high voltage chip according to claim 1, characterized in that the step of plasma bombarding and activating the epitaxial wafer after one substrate is removed and the other epitaxial wafer comprises: 使用等离子清洗机对衬底去除后的外延片与另一外延片进行等离子轰击活化，其中轰击离子为Ar离子，轰击时间为5～20min；The epitaxial wafer after substrate removal and another epitaxial wafer are activated by plasma bombardment using a plasma cleaning machine, wherein the bombarding ions are Ar ions and the bombardment time is 5 to 20 minutes; 其中，衬底去除后的外延片中第一高掺杂层与另一外延片中第二高掺杂层进行键合的键合压力为12000kgf，键合时间60～120min，键合温度根据所使用的蜡不会热熔流动的温度进行确定。Among them, the bonding pressure of the first highly doped layer in the epitaxial wafer after the substrate is removed and the second highly doped layer in another epitaxial wafer is 12000kgf, the bonding time is 60 to 120min, and the bonding temperature is determined according to the temperature at which the wax used does not melt and flow. 6.根据权利要求1所述的垂直串联结构高压芯片制作方法，其特征在于，生长的外延片中第一高掺杂层及第二高掺杂层的掺杂浓度均大于1e19，厚度达到5000A。6. The method for manufacturing a vertical series structure high-voltage chip according to claim 1 is characterized in that the doping concentration of the first high-doped layer and the second high-doped layer in the grown epitaxial wafer are both greater than 1e19, and the thickness reaches 5000A. 7.根据权利要求6所述的垂直串联结构高压芯片制作方法，其特征在于，所述生长出PN区处均具有高掺杂层的多个外延片的步骤之后还包括：7. The method for manufacturing a vertical series structure high voltage chip according to claim 6, characterized in that after the step of growing a plurality of epitaxial wafers each having a high doping layer in the PN region, the method further comprises: 对外延片进行有机清洗去除表面杂质及脏污；Perform organic cleaning on the epitaxial wafer to remove surface impurities and dirt; 对有机清洗后的外延片中第二高掺杂层进行抛光处理至厚度大于等于50A且小于等于100A。The second high-doping layer in the organically cleaned epitaxial wafer is polished to a thickness greater than or equal to 50 Å and less than or equal to 100 Å. 8.根据权利要求6所述的垂直串联结构高压芯片制作方法，其特征在于，所述将临时键合后的外延片中的衬底进行去除至露出第一高掺杂层的步骤包括：8. The method for manufacturing a vertical series structure high voltage chip according to claim 6, characterized in that the step of removing the substrate in the temporarily bonded epitaxial wafer to expose the first highly doped layer comprises: 将临时键合后的外延片中的衬底进行去除；Removing the substrate from the temporarily bonded epitaxial wafer; 对衬底去除后的外延片中所露出的第一高掺杂层进行抛光处理至厚度大于等于50A且小于等于100A。The first highly doped layer exposed in the epitaxial wafer after the substrate is removed is polished to a thickness greater than or equal to 50 Å and less than or equal to 100 Å. 9.一种垂直串联结构高压芯片，其特征在于，所述垂直串联结构高压芯片是由权利要求1至8任一项所述的垂直串联结构高压芯片制作方法制作得到，包括：9. A vertical series structure high voltage chip, characterized in that the vertical series structure high voltage chip is manufactured by the vertical series structure high voltage chip manufacturing method according to any one of claims 1 to 8, comprising: GaAs衬底、在所述GaAs衬底上依次堆叠的缓冲层、截止层、及重复层叠至少两次的外延结构；A GaAs substrate, a buffer layer and a cutoff layer sequentially stacked on the GaAs substrate, and an epitaxial structure repeatedly stacked at least twice; 所述外延结构包括依次堆叠的高掺杂N型接触层、N型过渡层、N型电流扩展层、N型限制层、N型阻挡层、多量子阱层、P型阻挡层、P型限制层、P型过渡层、及高掺杂P型电流扩展层。The epitaxial structure includes a highly doped N-type contact layer, an N-type transition layer, an N-type current spreading layer, an N-type limiting layer, an N-type barrier layer, a multi-quantum well layer, a P-type barrier layer, a P-type limiting layer, a P-type transition layer, and a highly doped P-type current spreading layer stacked in sequence. 10.根据权利要求9所述的垂直串联结构高压芯片，其特征在于，所述缓冲层为GaAs层，所述截止层为GaInP层，所述高掺杂N型接触层为GaAs层，所述N型过渡层为GaInP层，所述N型电流扩展层为AlGaInP层，所述N型限制层为AlInP层，所述N型阻挡层为AlGaInP层，所述P型阻挡层为AlGaInP层，所述P型限制层为AlInP层，所述P型过渡层为AlGaInP层，所述高掺杂P型电流扩展层为GaP层；10. The vertical series structure high-voltage chip according to claim 9, characterized in that the buffer layer is a GaAs layer, the cutoff layer is a GaInP layer, the highly doped N-type contact layer is a GaAs layer, the N-type transition layer is a GaInP layer, the N-type current spreading layer is an AlGaInP layer, the N-type limiting layer is an AlInP layer, the N-type barrier layer is an AlGaInP layer, the P-type barrier layer is an AlGaInP layer, the P-type limiting layer is an AlInP layer, the P-type transition layer is an AlGaInP layer, and the highly doped P-type current spreading layer is a GaP layer; 所述高掺杂N型接触层及所述高掺杂P型电流扩展层的掺杂浓度均大于1e19，厚度均大于等于50A且小于等于100A。The doping concentrations of the highly doped N-type contact layer and the highly doped P-type current spreading layer are both greater than 1e19, and the thicknesses are both greater than or equal to 50A and less than or equal to 100A.
CN202210210851.3A 2022-03-03 2022-03-03 A vertical series structure high voltage chip and its manufacturing method Active CN114709299B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210210851.3A CN114709299B (en) 2022-03-03 2022-03-03 A vertical series structure high voltage chip and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210210851.3A CN114709299B (en) 2022-03-03 2022-03-03 A vertical series structure high voltage chip and its manufacturing method

Publications (2)

Publication Number Publication Date
CN114709299A CN114709299A (en) 2022-07-05
CN114709299B true CN114709299B (en) 2025-06-27

Family

ID=82167625

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210210851.3A Active CN114709299B (en) 2022-03-03 2022-03-03 A vertical series structure high voltage chip and its manufacturing method

Country Status (1)

Country Link
CN (1) CN114709299B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117810318B (en) * 2024-02-29 2024-05-07 江西兆驰半导体有限公司 High-voltage Micro-LED chip and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101351900A (en) * 2005-12-30 2009-01-21 奥斯兰姆奥普托半导体有限责任公司 LED semiconductor body and application of LED semiconductor body
CN207602981U (en) * 2017-11-13 2018-07-10 苏州长光华芯光电技术有限公司 Multiple-active-region semiconductor bar chip of laser is accumulated in a kind of

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4042334C2 (en) * 1990-02-27 1993-11-18 Fraunhofer Ges Forschung Process for producing an isolated, single-crystalline silicon island
CN102637681B (en) * 2012-04-28 2014-07-30 厦门市三安光电科技有限公司 Vertical light-emitting device and manufacturing method thereof
CN102779913A (en) * 2012-08-14 2012-11-14 天津三安光电有限公司 Ultra-high-brightness light-emitting diode and preparation method thereof
CN108010996B (en) * 2017-11-29 2019-05-03 扬州乾照光电有限公司 A kind of AlGaInP light-emitting diode and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101351900A (en) * 2005-12-30 2009-01-21 奥斯兰姆奥普托半导体有限责任公司 LED semiconductor body and application of LED semiconductor body
CN207602981U (en) * 2017-11-13 2018-07-10 苏州长光华芯光电技术有限公司 Multiple-active-region semiconductor bar chip of laser is accumulated in a kind of

Also Published As

Publication number Publication date
CN114709299A (en) 2022-07-05

Similar Documents

Publication Publication Date Title
JP7105239B2 (en) Gallium nitride epitaxial structure for power devices
TWI766256B (en) RGB full-color InGaN-based LED and preparation method thereof
JP3822318B2 (en) Semiconductor light emitting device and manufacturing method thereof
EP2600389B1 (en) Method for bonding semiconductor substrates
JP3914615B2 (en) Semiconductor light emitting device and manufacturing method thereof
JP7659909B2 (en) Transfer process for realizing semiconductor devices
WO2006000691A1 (en) Hybrid epitaxy support and method for making same
CN101091234A (en) Method for manufacturing substrates for optoelectronic applications
TW201125162A (en) Photonic device and method of making the same
US8785294B2 (en) Silicon carbide lamina
CN114373838B (en) LED epitaxial wafer with quantum barrier silicon doped structure, growth method and manufacturing method
CN114709299B (en) A vertical series structure high voltage chip and its manufacturing method
CN106384771B (en) AlGaInP-based light emitting diode epitaxial wafer, chip and preparation method
US8916396B2 (en) Method of manufacturing semiconductor element
KR102049248B1 (en) SEPARATION METHOD OF GaN CRYSTAL LAYER USING SACRIFICIAL LAYER
CN102640258B (en) Method of manufacturing nitride semiconductor device
JP5598321B2 (en) Manufacturing method of semiconductor device
CN115206811B (en) Heterogeneous bonding structure and preparation method
CN102891232B (en) Light emitting semiconductor device and manufacture method thereof
CN100449806C (en) Nitride-based semiconductor light-emitting device and manufacturing method thereof
CN101246942A (en) Light-emitting diode and laser manufacturing method and light-emitting diode and laser
JP2002185041A (en) Semiconductor element
JPWO2009048056A1 (en) Compound semiconductor epitaxial wafer and manufacturing method thereof
JP3681540B2 (en) Semiconductor manufacturing method, semiconductor device manufacturing method, and semiconductor substrate manufacturing method
JP5879134B2 (en) Manufacturing method of semiconductor light emitting device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant