CN114709268B - Junction field effect transistor and preparation method thereof - Google Patents
Junction field effect transistor and preparation method thereofInfo
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- CN114709268B CN114709268B CN202210302891.0A CN202210302891A CN114709268B CN 114709268 B CN114709268 B CN 114709268B CN 202210302891 A CN202210302891 A CN 202210302891A CN 114709268 B CN114709268 B CN 114709268B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/83—FETs having PN junction gate electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/051—Manufacture or treatment of FETs having PN junction gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/343—Gate regions of field-effect devices having PN junction gates
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明涉及一种结型场效应晶体管及其制备方法，一种结型场效应晶体管，包括：第一导电类型的基底；至少两层阱区结构，层叠设置于基底；每一层阱区结构包括第二导电类型的第一阱区，以及位于第一阱区的相对两侧的两个第二阱区；其中，第二阱区的导电类型与第二导电类型相反，且与第一导电类型相同；漏极和源极，分别形成于最上一层阱区结构的第一阱区的相对两侧；以及栅极，形成于最上一层阱区结构的两个第二阱区；其中，相邻的两层阱区结构中，相邻的两个第一阱区彼此接触，同一侧的两个第二阱区彼此相连。在获得同样的导电能力的情况下，使用本申请的结型场效应晶体管的结构设计更能节约设计尺寸。
The present invention relates to a junction field effect transistor and a preparation method thereof, wherein the junction field effect transistor comprises: a substrate of a first conductivity type; at least two layers of well region structures, stacked on the substrate; each layer of the well region structure comprises a first well region of a second conductivity type, and two second well regions located on opposite sides of the first well region; wherein the conductivity type of the second well region is opposite to the second conductivity type and the same as the first conductivity type; a drain and a source, respectively formed on opposite sides of the first well region of the top well region structure; and a gate, formed in the two second well regions of the top well region structure; wherein, in two adjacent layers of the well region structure, the two adjacent first well regions are in contact with each other, and the two second well regions on the same side are connected to each other. While obtaining the same conductivity, the structural design of the junction field effect transistor of the present application can save design size.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a junction field effect transistor and a preparation method thereof.
Background
Junction Field-Effect Transistor (JFET) JFETs are formed by forming two highly doped P-regions on the same N-type semiconductor and connecting them together, the electrode being called a gate g, and two electrodes being respectively led out from both ends of the N-type semiconductor, being called a drain d and a source s.
However, the current that can be carried per unit volume of the conventional junction field effect transistor is very limited, resulting in a smaller conductivity of the conventional junction field effect transistor.
Disclosure of Invention
Based on this, it is necessary to provide a junction field effect transistor and a method for manufacturing the same, which are aimed at the problem that the conductivity of the conventional junction field effect transistor is small.
According to an aspect of the present application, there is provided a junction field effect transistor comprising:
A substrate of a first conductivity type;
Each well region structure comprises a first well region with a second conductivity type and two second well regions positioned on two opposite sides of the first well region, wherein the conductivity type of the second well region is opposite to that of the second well region and the same as that of the first well region;
A drain and a source respectively formed on opposite sides of the first well region of the uppermost layer of the well region structure, and
The grid electrode is formed on the two second well regions of the uppermost layer of the well region structure;
In the adjacent two-layer well region structure, two adjacent first well regions are contacted with each other, and two second well regions on the same side are connected with each other.
In one embodiment, the first well region comprises a channel region and two drift regions positioned on two opposite sides of the channel region, and a groove positioned between the drain electrode and the source electrode is formed on the channel region;
The at least two layers of the well region structures comprise an A well region structure positioned at the uppermost layer and at least one layer of a B well region structure positioned below the A well region structure along the stacking direction of the well region structures;
the drain electrode and the source electrode are respectively formed in two drift regions of the first well region in the A well region structure.
In one embodiment, in the a-well structure, a shallow trench isolation structure is disposed in the trench on the first well region to isolate the drain and the source from each other.
In one embodiment, two longitudinal ends of the shallow trench isolation structure extend towards one side away from each other and are respectively in contact with two second well regions in the a-well region structure so as to isolate the two second well regions from each other.
In one embodiment, the gate includes:
the polycrystalline silicon layer is arranged on the shallow groove isolation structure;
The gate electrode layer is arranged on one side of the polycrystalline silicon layer, which is far away from the shallow trench isolation structure;
And the grid electrode connecting layers are respectively formed in the two second well regions of the A well region structure and are in contact with the grid electrode layer.
In one embodiment, an intermediate substrate layer of the first conductivity type is also included;
the middle substrate layer is formed in the groove on the first well region in the B well region structure, and opposite ends of the middle substrate layer extend out of the groove to be inserted between two second well regions on the same side in two adjacent layers of well region structures.
In one embodiment, the intermediate substrate layer is doped with a first dose of ions, and the first well region of the B-well region structure is doped with a second dose of ions;
Wherein the first dose is greater than the second dose.
In one embodiment, in two adjacent well structures, the second well region of one well structure is doped with a third dose of the first type ions, and the second well region of the other well structure is doped with a fourth dose of the first type ions;
the third dose and the fourth dose are respectively set according to the first dose, so that two second well regions on the same side in two adjacent well region structures are connected by means of the intermediate substrate layer.
According to another aspect of the present application, there is provided a method of manufacturing a junction field effect transistor, comprising the steps of:
Providing a substrate of a first conductivity type;
Forming at least two layers of well region structures which are arranged in a stacked manner on the substrate, wherein each well region structure comprises a first well region with a second conductivity type and two second well regions positioned on two opposite sides of the first well region, and the conductivity type of the second well region is opposite to that of the second conductivity type and identical to that of the first conductivity type;
forming a drain electrode and a source electrode on two opposite sides of the first well region of the uppermost layer of the well region structure respectively;
forming a grid electrode on two second well regions of the uppermost layer of well region structure;
In the adjacent two-layer well region structure, two adjacent first well regions are contacted with each other, and two second well regions on the same side are connected with each other.
In one embodiment, before forming the at least two-layer well region structure in a stacked arrangement on the substrate, the preparation method further includes:
forming a buried layer of a first conductivity type on the substrate;
Epitaxially forming an epitaxial layer of a first conductivity type on the buried layer;
The thickness of the epitaxial layer is 2-10 microns.
In one embodiment, the at least two layers of well region structures include an a-well region structure located at an uppermost layer and at least one layer of B-well region structure located below the a-well region structure along a stacking direction of the well region structure, and the forming at least two layers of well region structures stacked on the substrate specifically includes:
Forming an active region on the substrate;
performing mask and ion implantation on the epitaxial layer through the active region to form the B well region structure on the epitaxial layer;
forming an intermediate substrate layer at a trench on the first well region in the B-well region structure;
And performing mask and ion implantation on the intermediate substrate layer to form the A well region structure on the intermediate substrate layer.
The junction field effect transistor and the preparation method thereof have at least the following beneficial effects:
in the junction field effect transistor, the structure of the at least two layers of well regions is equivalent to the length of the conducting channel of the junction field effect transistor, so that the effective conducting area of the junction field effect transistor is increased, and the conducting capability of the junction field effect transistor can be effectively improved. In other words, the structural design using the junction field effect transistor of the present application can save more design size in the case of obtaining the same conductivity.
The preparation method of the junction field effect transistor can obtain the junction field effect transistor which can save the design size.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic diagram showing a partial structure of a junction field effect transistor in an embodiment of the present application;
fig. 2 shows a top view of a junction field effect transistor in an embodiment of the application;
fig. 3 shows a lateral cross-sectional view of a junction field effect transistor in an embodiment of the application;
fig. 4 shows a longitudinal cross-sectional view of a junction field effect transistor in an embodiment of the application;
Fig. 5 is a flowchart showing a method for manufacturing a junction field effect transistor according to an embodiment of the present application;
fig. 6 is a flowchart showing a method of manufacturing a junction field effect transistor according to another embodiment of the present application.
Reference numerals illustrate:
10. Junction field effect transistor 110, substrate 120, well region structure 120a, well region structure 120B, well region structure 121, first well region 1211, channel region 1212, drift region 1213, trench 122, second well region 130, drain 131, drain connecting layer 132, drain electrode layer 140, source 141, source connecting layer 142, source electrode layer 150, gate 151, polysilicon layer 152, gate electrode layer 153, gate connecting layer 160, intermediate substrate layer 170, shallow trench isolation structure. 181. Buried layer 182, epitaxial layer.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section, for example, a first doping type could be termed a second doping type, and, similarly, a second doping type could be termed a first doping type, a doping type different from the second doping type, such as, for example, the first doping type could be P-type and the second doping type could be N-type, or the first doping type could be N-type and the second doping type could be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
In some embodiments, referring to fig. 1 in combination with fig. 2 and 3, the present invention provides a junction field effect transistor 10, which includes a substrate 110 of a first conductivity type, at least two well structures 120, a drain 130, a source 140 and a gate 150.
At least two well structure layers 120 are stacked on the substrate 110, and each well structure 120 includes a first well 121 of a second conductivity type and two second well 122 located at two opposite sides of the first well 121, wherein the second well 122 has a conductivity type opposite to the second conductivity type and the same as the first conductivity type.
In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.
In other embodiments, the first conductivity type is N-type and the second conductivity type is P-type.
Specifically, in the embodiment shown in fig. 1, the first conductivity type is P-type and the second conductivity type is N-type, that is, the conductivity type of the second well region 122 is P-type, and the conductivity type of the first well region 121 is N-type.
The drain 130 and the source 140 are respectively formed on opposite sides of the first well 121 of the uppermost well structure 120, and the gate 150 is formed on the two second wells 122 of the uppermost well structure 120.
In the two adjacent well structures 120, two adjacent first well regions 121 are in contact with each other, and two second well regions 122 on the same side are connected to each other.
In the above-mentioned junction field effect transistor 10, the drain 130 and the source 140 serve as the current input terminal and the output terminal of the junction field effect transistor 10, respectively, and the switching of the junction field effect transistor 10 between the on/off states can be achieved by adjusting the voltage of the gate 150.
Under the condition that the gate 150 is not negatively biased, the current input by the drain 130 (positive electrode) can generate a saturation current between the drain 130 (positive electrode) and the source 140 (negative electrode) under the conduction of the first well region 121 (N type), so that the junction field effect transistor 10 is turned on. With the gate 150 negatively biased with respect to the source 140, the PN junction depletion layer formed by the first well 121 (N-type) and the second well 122 (P-type) in each well structure 120 is widened, thereby compressing the N-type conductivity channel and turning off the junction field effect transistor 10. It can be appreciated that, in the case of the same size, the at least two well structures 120 provided in the junction field effect transistor 10 are equivalent to increasing the length of the conductive channel of the junction field effect transistor 10, so as to increase the effective conductive area of the junction field effect transistor 10, and effectively improve the conductivity of the junction field effect transistor 10. In other words, the structural design using the junction field effect transistor 10 of the present application can save more design size in the case of obtaining the same conductivity.
In some embodiments, referring to fig. 1 and 3 in combination with fig. 4, the first well region 121 includes a channel region 1211 and two drift regions 1212 located on opposite sides of the channel region 1211, and a trench 1213 located between the drain 130 and the source 140 is formed on the channel region 1211. The at least two-layer well region structure 120 includes an a-well region structure 120a located at the uppermost layer and at least one layer of B-well region structure 120B located at the bottom side of the a-well region structure 120a, and the drain 130 and the source 140 are respectively formed in two drift regions 1212 of the first well region 121 in the a-well region structure 120 a. With no negative bias applied to the gate 150, current is input from the drain 130 (positive electrode) and holes or electrons can enter one of the drift regions 1212 and the channel region 1211 into the other drift region 1212, so that drain electrons can be transferred to the other drift region 1212 and finally reach the source 140 under the action of the drain electric field, at which point the junction field effect transistor 10 is in an on state.
In some embodiments, referring to fig. 1, 3 and 4, in the a-well structure 120a, a shallow trench isolation structure 170 is disposed in the trench 1213 on the first well 121 to isolate the drain 130 and the source 140 from each other. The shallow trench isolation structure 170 can isolate the drain 130 and the source 140 from each other, isolate the active region of the drain 130 and the active region of the source 140 from each other, avoid the short circuit between the drain 130 and the source 140, and improve the reliability of the junction field effect transistor 10.
Alternatively, the shallow trench isolation structure 170 may be formed using a shallow trench isolation process (shallow trench isolation, STI). Specifically, the method of forming the shallow trench isolation structure 170 may include forming an isolation oxide layer, nitride deposition, masking layer and isolation trench and etching of the isolation trench, then filling the isolation trench with oxide, and finally removing nitride and polishing the filled oxide to form the shallow trench isolation structure 170.
In some embodiments, referring to fig. 1 and 4, the two longitudinal ends of the shallow trench isolation structure 170 extend toward the sides facing away from each other, and respectively contact the two second well regions 122 in the a-well structure 120a to isolate the two second well regions 122 from each other. Thus, the shallow trench isolation structure 170 can prevent the two second well regions 122 in the a-well region structure 120a from being shifted, and can improve the reliability of the junction field effect transistor 10.
In some embodiments, the gate 150 includes a polysilicon layer 151, a gate electrode layer 152 and a gate connection layer 153, the polysilicon layer 151 is disposed on the shallow trench isolation structure 170, the gate electrode layer 152 is disposed on a side of the polysilicon layer 151 away from the shallow trench isolation structure 170, the gate connection layer 153 is respectively formed on the two second well regions 122 of the a-well region structure 120a, and the gate connection layer 153 is in contact with the gate electrode layer 152. On the one hand, the polysilicon layer 151 is formed on the shallow trench isolation structure 170, so that the gate 150 and the drain 130 can be electrically insulated, and the gate 150 and the source 140 can be electrically insulated, on the other hand, the gate 150 can be ensured to be formed in the two second well regions 122 of the a-well region structure 120a, so that the two second well regions 122 can be connected together and led out of the gate 150.
In some embodiments, the junction field effect transistor 10 further includes an intermediate substrate layer 160 of the first conductivity type, the intermediate substrate layer 160 is formed in the trench 1213 on the first well region 121 in the B-well region structure 120B, and opposite ends of the intermediate substrate layer 160 extend out of the trench 1213 to be interposed between two second well regions 122 on the same side in the adjacent two-layer well region structure 120. It will be appreciated that the intermediate substrate layer 160 is respectively in contact with the two second well regions 122 on the same side of the two adjacent well region structures 120, so that the two second well regions 122 on the same side of the two adjacent well region structures 120 are connected through the intermediate substrate layer 160, so as to ensure that electrons in the second well region 122 in the uppermost well region structure 120 can flow to the second well regions 122 in the other well region structures 120 in sequence when the junction field effect transistor 10 is in use, and further ensure that a PN junction depletion layer formed by the first well region 121 (N-type) and the second well region 122 (P-type) in each well region structure 120 is widened under the condition that the gate 150 is negatively biased with respect to the source 140, which is beneficial to improving the conductivity of the junction field effect transistor 10.
In some embodiments, the intermediate substrate layer 160 is doped with a first dose of ions of a first type and the B well region structure 120B is doped with a second dose of ions of a second type in the first well region 121, wherein the first dose is greater than the second dose. The first type of ion and the second type of ion have opposite conductive types, and the first type of ion is a P-type ion and the second type of ion is an N-type ion, and of course, the first type of ion is an N-type ion and the second type of ion is a P-type ion.
In this embodiment, the first type of ions are P-type ions and the second type of ions are N-type ions, that is, the intermediate substrate layer 160 is doped with P-type ions at a first dose, and the second dose is doped with N-type ions in the first well region 121 of the B-well region structure 120B, so that the first dose is larger than the second dose, and the excessive implantation dose of the first well region 121 can be avoided, which further results in an excessively long diffusion length of the first well region 121, and the N-type ions in the first well region 121 are prevented from "eroding" the P-type ions in the intermediate substrate layer 160, thereby improving the reliability of the junction field effect transistor 10 to a certain extent.
In this embodiment, referring to fig. 3, the groove depth of the groove 1213 on the first well region 121 in the a-well region structure 120a is smaller than the groove depth of the groove 1213 on the first well region 121 in the B-well region structure 120B.
The a-well structure 120a is located on the uppermost layer, the trench 1213 on the first well 121 in the a-well structure 120a is not necessary to provide the intermediate substrate layer 160, and the depth of the trench 1213 on the first well 121 can be made smaller based on the design of structural optimization, so that the occupied volume of the junction field effect transistor 10 can be reduced to a certain extent.
In some embodiments, in two adjacent well structures 120, the second well 122 of one well structure 120 is doped with the first type ions at the third dose, and the second well 122 of the other well structure 120 is doped with the first type ions at the fourth dose. Wherein the third dose and the fourth dose are each set according to the first dose such that two second well regions 122 on the same side of two adjacent well region structures 120 are connected by means of an intermediate substrate layer 160. The second well region 122 may be formed by an ion implantation process, and the third dose and the fourth dose may be set according to the first dose, and it may be appreciated that a relative volume ratio of the two second well regions 122 on the same side of the two adjacent well region structures 120 may be controlled, so that the two second well regions 122 on the same side of the two adjacent well region structures 120 are connected through the intermediate substrate layer 160, so as to avoid a fault occurring between the two adjacent well region structures 120 and affecting the conductive effect of the junction field effect transistor 10.
Optionally, the number of implantation times corresponding to the two second well regions 122 on the same side in the two adjacent well region structures 120 may also be set, so as to better avoid faults between the two adjacent well region structures 120.
Referring to fig. 5, the present invention provides a method for manufacturing a junction field effect transistor, which includes the following steps:
s210, providing the substrate 110 of the first conductivity type. The base 110 may be a silicon wafer substrate.
S220, at least two layers of well structures 120 are formed on the substrate 110, where each well structure 120 includes a first well region 121 of a second conductivity type and two second well regions 122 located on opposite sides of the first well region 121, and the second well region 122 has a conductivity type opposite to the second conductivity type and the same as the first conductivity type.
S230, the drain 130 and the source 140 are formed on opposite sides of the first well 121 of the uppermost well structure 120.
S240, forming a gate 150 on the two second well regions 122 of the uppermost well region structure 120.
In the two adjacent well structures 120, two adjacent first well regions 121 are in contact with each other, and two second well regions 122 on the same side are connected to each other.
In the above example, with the gate 150 negatively biased with respect to the source 140, the PN junction depletion layer formed by the first well region 121 (N-type) and the second well region 122 (P-type) in each layer of the well region structure 120 is widened, thereby compressing the N-type conductivity channel, and thus turning off the junction field effect transistor 10. It can be appreciated that in the above-mentioned junction field effect transistor 10, the at least two well structures 120 are configured to increase the length of the conductive channel of the junction field effect transistor 10, thereby increasing the effective conductive area of the junction field effect transistor 10 and effectively improving the conductivity of the junction field effect transistor 10. In other words, the structural design using the junction field effect transistor 10 of the present application can save more design size in the case of obtaining the same conductivity.
It should be noted that, S210, S220, S230, and S240 are not limited in order, that is, any one of them is executed before or simultaneously, and is also allowed.
In some embodiments, referring to fig. 3, before step S220 of forming at least two well structures 120 in a stacked arrangement on a substrate 110, the method further includes:
forming a buried layer 181 of a first conductivity type on the substrate 110;
An epitaxial layer 182 of the first conductivity type is epitaxially formed on the buried layer 181.
Wherein the thickness of the epitaxial layer 182 is 2-10 microns. If the thickness of the epitaxial layer 182 exceeds micrometers, ions are difficult to penetrate through the epitaxial layer 182 when the at least two well region structures 120 stacked on the epitaxial layer 182 are formed by an ion implantation process, and if the thickness of the epitaxial layer 182 is less than micrometers, it is difficult to be compatible with other EPI-BCD processes. Therefore, the thickness of the epitaxial layer 182 is set to be 2-10 micrometers, so that the reliability of the junction field effect transistor 10 can be improved, and the preparation method of the junction field effect transistor 10 can be compatible with other EPI-BCD processes.
In some embodiments, the method for manufacturing the junction field effect transistor 10 includes the following steps:
S301, providing a substrate 110 of a first conductivity type. The base 110 may be a silicon wafer substrate.
S302, performing high-temperature push-well and P-type ion implantation on the substrate 110 to form the buried layer 181.
And S303, epitaxially forming an epitaxial layer 182 on the buried layer 181.
An active region is formed on the substrate 110 by exposure (masking) and/or etching processes to form a stacked arrangement of at least two well region structures 120 on the epitaxial layer 182. The active regions include a first active region corresponding to the drain electrode 130 and a second active region corresponding to the source electrode 140.
S305, performing mask and ion implantation on the epitaxial layer 182 through the active region to form a B-well region structure 120B on the epitaxial layer 182, wherein the B-well region structure 120B includes a first well region 121 (a first N-type ion implantation layer) and a second well region 122 (a first P-type ion implantation layer) located on opposite sides of the first well region 121. Specifically, the first well region 121 may be an N-type ion implantation layer 1, and the second well region 122 may be a P-type ion implantation layer 1.
S306, P-type ion implantation is performed at the trench 1213 on the first well region 121 in the B-well region structure 120B to form the intermediate substrate layer 160 at the trench 1213.
S307, performing mask and ion implantation on the intermediate substrate layer 160 to form an a-well region structure 120a on the intermediate substrate layer 160, where the a-well region structure 120a includes a first well region 121 and second well regions 122 located on opposite sides of the first well region 121, and specifically, the first well region 121 may be a second N-type ion implantation layer, and the second well region 122 may be a second P-type ion implantation layer.
S308, a Shallow Trench Isolation (STI) is performed at a trench 1213 on the first well 121 in the a-well structure 120a, so as to form a shallow trench isolation structure 170 at the trench 1213, form a gate 150 of a polysilicon structure on the shallow trench isolation structure 170, and form two second well 122 and gate contact holes in the a-well structure 120a, respectively, on which a gate connection layer 153 connected to the gate electrode layer 152 of the gate 150 is formed, so that the gate 150 is formed in the two second well 122 of the a-well structure 120 a.
S309, growing a dielectric ILD layer on the active area to form a drain 130 or a source 140 on the dielectric ILD layer. That is, dielectric ILD layers may be grown on the first active region and the second active region, respectively, so that the drain electrode 130 can be formed on the dielectric ILD layer of the first active region, and the source electrode 140 can be formed on the dielectric ILD layer of the second active region. Wherein the first active region and the second active region respectively correspond to the two first drift regions 1212 of the first well region 121 in the a-well region structure 120a.
And S310, forming a drain contact hole on the growth medium ILD layer of the first active region, and forming a source contact hole on the growth medium ILD layer of the second active region.
S311, the drain electrode layer 132 may be connected to the end of the drain electrode connection layer 131 away from the drain contact hole, so as to form the drain electrode 130. The source connection layer 141 may be interposed in the source contact hole, and the source electrode layer 142 may be connected to an end of the source connection layer 141 remote from the source contact hole to form the source electrode 140. In this way, the drain electrode layer 132 of the drain electrode 130 and the source electrode layer 142 of the source electrode 140 may be respectively used as a current input terminal and an output terminal of the junction field effect transistor 10, so that a current input by the drain electrode 130 (positive electrode) can generate a saturation current between the drain electrode 130 (positive electrode) and the source electrode 140 (negative electrode) under the conduction of the first well region 121 (N-type), so that the junction field effect transistor 10 is turned on.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
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| CA2783659A1 (en) * | 1999-12-21 | 2001-06-28 | Sumitomo Electric Industries, Ltd. | Horizontal junction field-effect transistor |
| JP5191109B2 (en) * | 2006-08-29 | 2013-04-24 | ローム株式会社 | Junction field effect transistor |
| CN103840012A (en) * | 2012-11-22 | 2014-06-04 | 无锡华润上华半导体有限公司 | Junction field-effect transistor (JFET) and preparation method thereof |
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