CN114709243B - Display module, display panel, manufacturing method of display panel and mother board to be cut - Google Patents

Abstract

This disclosure provides a display module, a display panel, a method for manufacturing the same, and a motherboard to be cut. The motherboard includes: a substrate; a wiring structure disposed on one side of the substrate, wherein the portion of the wiring structure located in the pad area includes multiple parallel signal lines; the pad area includes a first region and a second region in the extension direction of the signal lines, the first region being located between the second region and the display area; the portion of the signal lines located in the first region is capable of being bonded to an external circuit board; the portion of the signal lines located in the second region includes multiple insulated line segments in the extension direction of the signal lines. This disclosure can solve the problem of poor dark line quality.

Description

Display module, display panel, manufacturing method of display panel and mother board to be cut

Technical Field

The disclosure relates to the technical field of display, in particular to a display module, a display panel, a manufacturing method of the display panel and a mother board to be cut.

Background

With the development of economy, display panels are becoming more and more widely used in people's lives. The display panel mainly comprises a light emitting structure. The light emitting structure includes two electrodes disposed opposite to each other and a light emitting layer disposed between the two electrodes. The two electrodes are electrically connected to a power source to supply power to the light emitting layer. However, the conventional display panel has a problem of poor dark line.

Disclosure of Invention

The disclosure aims to provide a display module, a display panel, a preparation method of the display module and the display panel, and a mother board to be cut, which can solve the problem of bad dark lines.

According to one aspect of the present disclosure, there is provided a motherboard to be cut including a display region and a peripheral region surrounding the display region, the peripheral region including a pad region and a cutting region, the pad region being located between the cutting region and the display region, the motherboard to be cut including:

A substrate;

the wiring structure is arranged on one side of the substrate, the part of the wiring structure, which is positioned in the bonding pad area, comprises a plurality of signal wires which are arranged in parallel, the bonding pad area comprises a first area and a second area in the extending direction of the signal wires, the first area is positioned between the second area and the display area, the part of the signal wires, which is positioned in the first area, can be in binding connection with an external circuit board, and the part of the signal wires, which is positioned in the second area, comprises a plurality of line segments which are arranged in an insulating manner in the extending direction of the signal wires.

Further, the second area is provided with one or more strip-shaped grooves, the strip-shaped grooves penetrate through the wiring structure in the depth direction of the strip-shaped grooves, and the strip-shaped grooves are different from the extending direction of the signal lines and are arranged in a crossing manner with the signal lines so that the signal lines are divided into a plurality of line segments which are arranged at intervals.

Further, the motherboard to be cut includes:

And the insulating glue fills the strip-shaped grooves.

Further, the insulating glue is photosensitive glue or thermosensitive glue.

Further, the stripe groove extends into the substrate in a depth direction of the stripe groove.

Further, the cutting area is adjacent to the second area, the width of the part of the signal line located in the first area is larger than that of the part of the signal line located in the second area, and the distance between the parting line between the first area and the second area and the strip-shaped groove is larger than that between the strip-shaped groove and the parting line between the second area and the cutting area.

Further, a distance between a boundary line between the first region and the second region and the stripe groove is greater than 145 μm, and a distance between the stripe groove and a boundary line between the second region and the cutting region is 45 μm to 105 μm.

Further, the extending direction of the strip-shaped groove is perpendicular to the extending direction of the signal line.

Further, the number of the pad regions is plural, and the pad regions are distributed at intervals in a direction perpendicular to the extending direction of the signal line;

One of the stripe grooves is disposed to cross the signal lines in at least two of the pad regions, or one of the stripe grooves is disposed to cross the signal lines in only one of the pad regions.

Further, the number of the strip-shaped grooves is multiple, and at least two strip-shaped grooves are arranged at intervals in the extending direction of the signal line.

Further, the motherboard to be cut includes:

the first insulating layer is arranged on the substrate, and the wiring structure is arranged on one side, far away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, far away from the substrate, of the wiring structure, a window is formed in the second insulating layer, and the part, located in the second area, of the signal wire is exposed through the window.

Further, the motherboard to be cut further comprises a thin film transistor, and the thin film transistor comprises:

an active layer disposed on the substrate;

the first gate insulating layer is arranged on the substrate and covers the active layer;

the first gate electrode layer is arranged on one side of the first gate insulating layer, which is far away from the substrate;

a second gate insulating layer covering the first gate electrode layer and the first gate insulating layer;

the second gate electrode layer is arranged on one side of the second gate insulating layer, which is far away from the substrate;

an interlayer insulating layer covering the second gate electrode layer and the second gate insulating layer;

the first source-drain electrode layer is arranged on one side of the interlayer insulating layer away from the substrate and is connected with the active layer;

a first planarization layer covering the first source-drain electrode layer and the interlayer insulating layer;

the signal line comprises a first welding pad, and the first source-drain electrode layer and the first welding pad are arranged on the same layer.

Further, the signal line further includes a second bonding pad and a third bonding pad, the second bonding pad is arranged on the same layer as the second gate electrode layer, the third bonding pad is arranged on the same layer as the first gate electrode layer, the first bonding pad is connected with the second bonding pad, and the second bonding pad is connected with the third bonding pad.

According to one aspect of the present disclosure, there is provided a method of manufacturing a display panel, including:

Providing the mother board to be cut;

And cutting the mother board to be cut along the cutting area to form the display panel.

According to one aspect of the present disclosure, there is provided a display panel prepared by the method of preparing a display panel.

According to one aspect of the present disclosure, there is provided a display module including:

the display panel;

and the external circuit board is in binding connection with the part of the signal line, which is positioned in the first area.

According to the display module, the display panel, the manufacturing method of the display panel and the motherboard to be cut, as the part of the signal wire, which is positioned in the second area, comprises the plurality of line segments which are arranged in an insulating manner in the extending direction of the signal wire, the part of the signal wire, which is positioned in the first area, can be prevented from being subjected to poor short circuit after cutting and carbonization, and further the problem of poor dark line caused by poor short circuit of the signal wire can be solved.

Drawings

Fig. 1 is a schematic diagram of a signal line in the related art.

Fig. 2 is a schematic diagram of a motherboard to be cut according to an embodiment of the present disclosure.

Fig. 3-6 are schematic cross-sectional views of a motherboard to be cut according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a signal line of an embodiment of the present disclosure.

Fig. 8 is a schematic view of section A-A of the structure shown in fig. 2.

Fig. 9 to 12 are schematic diagrams of a display module according to an embodiment of the disclosure.

Fig. 13 to 14 are schematic cross-sectional views of a display module according to an embodiment of the present disclosure.

The reference numerals are 1, a substrate, 2, a first insulating layer, 3, a wiring structure, 4, a second insulating layer, 5, a window, 6, a stripe groove, 7, insulating glue, 8, conductive glue, 9, a pin, 10, a substrate, 11, a back glue, 12, a protective glue, 13, a positive glue, 14, an active layer, 15, a first gate insulating layer, 16, a first gate electrode layer, 17, a second gate insulating layer, 18, a second gate electrode layer, 19, an interlayer insulating layer, 20, a first source/drain electrode layer, 21, a first planarization layer, 22, a second source/drain electrode layer, 23, a second planarization layer, 24, a first electrode, 25, a light emitting layer, 26, a second electrode, 27, a pixel defining layer, 28, a signal line, 281, a first bonding pad, 282, a second bonding pad, 283, a third bonding pad, 29, carbide, 100, a fan-out area, 200, a bonding pad area, 201, a first area, 202, a second area, 300, a cutting area, 400, a display area, a 500, an external circuit board, a 500 and an external circuit board.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus consistent with some aspects of the disclosure as detailed in the accompanying claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one location or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

In the related art, the display panel may be formed by performing laser cutting on a mother substrate to be cut. The motherboard to be cut comprises a substrate and a plurality of signal wires positioned on the substrate. As shown in fig. 1, when an organic substance is present in the substrate, the laser light used for dicing burns the substrate to form carbide 29, and the carbide 29 is conductive and can overlap between the two signal lines 28, so that the signal lines 28 are short-circuited, and further, a dark line defect is likely to occur.

The embodiment of the disclosure provides a motherboard to be cut. As shown in fig. 2, 3, and 7, the mother board to be cut may include a display region 400 and a peripheral region 500. The peripheral region 500 may surround the display region 400. The peripheral region 500 may include a pad region 200, a fan-out region 100, and a cutting region 300. The pad region 200 may be disposed at a distance from the display region 400. The fan-out area 100 may be located between the pad area 200 and the display area 400. The pad region 200 may be located between the cutting region 300 and the display region 400. The motherboard to be cut may comprise a substrate 1 and a trace structure 3, wherein:

The trace structure 3 is disposed on one side of the substrate 1, and a portion of the trace structure 3 located in the pad area 200 includes a plurality of signal lines 28 disposed in parallel. The pad region 200 includes a first region 201 and a second region 202 in the extending direction of the signal line 28. The first region 201 is located between the second region 202 and the display region 400. The portion of the signal line 28 located in the first region 201 can be bonded to the external circuit board 600. The portion of the signal line 28 located in the second region 202 includes a plurality of line segments arranged in an insulating manner in the extending direction of the signal line 28.

In the motherboard to be cut in the embodiment of the disclosure, since the portion of the signal line 28 located in the second area 202 includes a plurality of line segments arranged in an insulating manner in the extending direction of the signal line 28, the problem that the portion of the signal line 28 located in the first area 201 is poor in short circuit after cutting and carbonization can be avoided, and thus the problem of poor dark line caused by the poor short circuit of the signal line 28 can be solved.

The following describes in detail the portions of the motherboard to be cut according to the embodiments of the present disclosure:

As shown in fig. 3, the substrate 1 may be a rigid substrate. The rigid substrate may be a glass substrate, a PMMA (Polymethyl methacrylate ) substrate, or the like. Of course, the substrate 1 may also be a flexible substrate. The flexible substrate may be a PET (Polyethylene terephthalate ) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate, or a PI (Polyimide) substrate, among others. Further, an organic substance may be included in the substrate 1.

As shown in fig. 3, the trace structure 3 is provided on one side of the substrate 1. The motherboard to be cut of the present disclosure may further include a first insulating layer 2 and a second insulating layer 4. The first insulating layer 2 may be disposed on the substrate 1, and the trace structure 3 may be disposed on a side of the first insulating layer 2 facing away from the substrate 1. The second insulating layer 4 may be disposed on a side of the trace structure 3 facing away from the substrate 1.

As shown in fig. 3 and 7, a partial region of the trace structure 3 may be located in the pad region 200, and a portion of the trace structure 3 located in the pad region 200 includes a plurality of signal lines 28 disposed in parallel. The pad region 200 may include a first region 201 and a second region 202 in the extending direction of the signal line 28. The extending direction of the signal line 28 may be perpendicular to the thickness direction of the substrate 1. The first region 201 is located between the second region 202 and the display region 400. The boundary between the first region 201 and the second region 202 may be perpendicular to the extending direction of the signal line 28. The signal line 28 is disposed in each of the first region 201 and the second region 202. The width of the portion of the signal line 28 located in the first region 201 is greater than the width of the portion of the signal line 28 located in the second region 202, and the portion of the signal line 28 located in the first region 201 can be bonded to the external circuit board 600. The second insulating layer 4 may be provided with a window 5, and a portion of the signal line 28 located in the second region 202 may be exposed through the window 5, so as to facilitate the binding connection of the signal line 28 with the external circuit board 600.

As shown in fig. 2 and 3, the second region 202 may be provided with one or more grooves 6. In the depth direction of the bar-shaped groove 6, the bar-shaped groove 6 penetrates the wiring structure 3, i.e. the bar-shaped groove 6 penetrates the signal line 28. The depth direction of the stripe grooves 6 may be the same as the thickness direction of the substrate 1. Taking the mother board to be cut as an example, the mother board to be cut comprises a first insulating layer 2 and a second insulating layer 4, and in the depth direction of the strip-shaped groove 6, the strip-shaped groove 6 sequentially penetrates through the second insulating layer 4, the wiring structure 3 and the first insulating layer 2. Further, in the depth direction of the stripe groove 6, the stripe groove 6 extends into the substrate 1. For example, the distance between the surface of the first insulating layer 2 facing away from the second insulating layer 4 and the surface of the second insulating layer 4 facing away from the first insulating layer 2 is 2 μm-3 μm, such as 2 μm, 2.4 μm, 2.5 μm, 2.8 μm, 3 μm, etc., and the depth of the stripe grooves 6 may be 3 μm-6 μm, such as 3 μm, 4 μm, 5 μm, 6 μm, etc. The width of the strip-shaped groove 6 may be 10 μm to 40 μm, for example, 10 μm, 14 μm, 25 μm, 40 μm, etc. The extending direction of the stripe grooves 6 may be perpendicular to the thickness direction of the substrate 1. The extending direction of the strip-shaped groove 6 may be different from the extending direction of the signal line 28, and the strip-shaped groove 6 may be disposed to cross the signal line 28, so that the signal line 28 is divided into a plurality of line segments disposed at intervals, and the signal line 28 is further divided into a plurality of line segments disposed in an insulating manner. For example, the extending direction of the bar-shaped groove 6 may be perpendicular to the extending direction of the signal line 28. In other embodiments of the present disclosure, at least a portion of the area of the bar-shaped groove 6 may be curved, such as an S-shaped curve.

As shown in fig. 9 and 10, the number of the pad areas 200 may be plural. The plurality of pad regions 200 are spaced apart in a direction perpendicular to the extending direction of the signal lines 28. In one embodiment of the present disclosure, one stripe groove 6 is disposed to cross the signal line 28 in at least two pad areas 200. Further, one stripe groove 6 is disposed to intersect the signal lines 28 in all the pad areas 200, that is, one stripe groove 6 passes through all the pad areas 200 in sequence. Taking the number of the plurality of bar grooves 6 as an example, each of the plurality of bar grooves 6 is disposed to intersect the signal lines 28 in all the pad areas 200, and at least two of the plurality of bar grooves 6 are disposed at intervals in the extending direction of the signal lines 28. Wherein the spaced apart strip-shaped grooves 6 may be arranged in parallel.

In another embodiment of the present disclosure, as shown in fig. 11 and 12, one bar-shaped groove 6 is disposed to cross only the signal line 28 in one pad region 200, and the signal line 28 in each pad region 200 may be disposed to cross one or more bar-shaped grooves 6. Taking the example that the signal line 28 in the pad region 200 crosses the plurality of stripe grooves 6, at least two stripe grooves 6 among the plurality of stripe grooves 6 are arranged at intervals in the extending direction of the signal line 28. Wherein the spaced apart strip-shaped grooves 6 may be arranged in parallel.

As shown in fig. 4, the motherboard to be cut of the present disclosure may further include an insulating paste 7. The insulating glue 7 may fill the bar-shaped groove 6. The insulating glue 7 may be a photosensitive glue, such as taffy (Tuffy) glue, etc. Of course, the insulating paste 7 may be a heat sensitive paste or the like. The insulating adhesive 7 has low viscosity and good permeability, and can be quickly permeated and diffused after being coated so as to fill the strip-shaped groove 6. As shown in fig. 5, taking an example that the bottom of the bar groove 6 extends into the substrate 1 and the substrate 1 includes an organic matter, when the bar groove 6 is formed by a laser cutting process, the substrate 1 is burned by laser to form a carbide 29 capable of conducting electricity, the insulating glue 7 can wrap the carbide 29 to play a role of electrically isolating, and meanwhile, the formation and the extension of cracks can be blocked.

As shown in fig. 6, the cutting area 300 is located on a side of the second area 202 away from the first area 201, and the cutting area 300 is adjacent to the second area 202. The distance L1 between the parting line between the first region 201 and the second region 202 and the bar groove 6 is greater than the distance L2 between the bar groove 6 and the cutting region 300, so that the influence of the insulating paste 7 filled in the bar groove 6 on the binding of the external circuit board 600 can be reduced. Wherein the distance L1 of the parting line between the first region 201 and the second region 202 from the bar-shaped groove 6 may be larger than 145 μm, e.g. 150 μm, 160 μm, 170 μm, 180 μm, 2000 μm, etc. The distance L2 of the strip-shaped groove 6 from the cutting zone 300 may be 45 μm-105 μm, for example 45 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 105 μm. The distance L2 between the bar groove 6 and the cutting area 300 may be a distance between the dividing line of the cutting area 300 and the second area 202 and the bar groove 6. After the mother board to be cut is cut along the boundary between the cutting area 300 and the second area 202, the signal line 28 may form a cut section at an end of the portion of the second area 202 away from the first area 201. The distance between the strip-shaped groove 6 and the cutting section is the distance L2 between the strip-shaped groove 6 and the cutting area 300.

It should be noted that, the distance between the bar-shaped groove 6 and other objects in the disclosure may be the distance between the center line of the bar-shaped groove 6 and other objects, the center line of the bar-shaped groove 6 is located between two groove walls of the bar-shaped groove 6, and the center line of the bar-shaped groove 6 extends in the extending direction of the bar-shaped groove 6. When the number of the bar grooves 6 is plural, the "distance of the bar groove 6 from other objects" described in the present disclosure may be "distance of the bar groove 6 closest to the first region 201 from other objects" among the plurality of bar grooves 6.

As shown in fig. 8, a thin film transistor may be provided over the substrate 1. The thin film transistor may be a top gate thin film transistor, and of course, the thin film transistor may also be a bottom gate thin film transistor. Taking a thin film transistor as an example, the thin film transistor may include an active layer 14, a first gate insulating layer 15, a first gate electrode layer 16, a second gate insulating layer 17, a second gate electrode layer 18, an interlayer insulating layer 19, a first source drain electrode layer 20, a first planarization layer 21, and a second source drain electrode layer 22. The active layer 14 may be provided on the substrate 1. The first gate insulating layer 15 may be provided on the substrate 1 and cover the active layer 14. The first gate electrode layer 16 may be provided on a side of the first gate insulating layer 15 remote from the substrate 1. The second gate insulating layer 17 may be provided on the first gate insulating layer 15 and cover the first gate electrode layer 16. The second gate electrode layer 18 may be provided on a side of the second gate insulating layer 17 remote from the substrate 1. The interlayer insulating layer 19 may be provided on the second gate insulating layer 17 and cover the second gate electrode layer 18. The first source-drain electrode layer 20 may be disposed on the interlayer insulating layer 19 and connected to the active layer 14 via a via hole passing through the interlayer insulating layer 19, the first gate insulating layer 15, and the second gate insulating layer 17. The first planarization layer 21 may cover the first source-drain electrode layer 20 and the interlayer insulating layer 19. The second source-drain electrode layer 22 may be provided on the first planarization layer 21 and electrically connected to the first source-drain electrode layer 20 of the thin film transistor via a via hole penetrating the first planarization layer 21. The motherboard to be cut of the present disclosure may further include a second planarization layer 23. The second planarization layer 23 may cover the second source-drain electrode layer 22.

As shown in fig. 8, the signal line 28 may include a first pad 281. The first source-drain electrode layer 20 may be disposed on the same layer as the first pad 281. The second insulating layer 4 described above may be provided in the same layer as the first planarizing layer 21. The signal line 28 may further include a second pad 282 and a third pad 283. The second pad 282 may be disposed in the same layer as the second gate electrode layer 18. The third pad 283 may be disposed on the same layer as the first gate electrode layer 16. The first pad 281 may be connected to the second pad 282, and the second pad 282 may be connected to the third pad 283. The first insulating layer 2 may be composed of the first gate insulating layer 15, and the second insulating layer 4 may be composed of the second gate insulating layer 17, the interlayer insulating layer 19, and the first planarization layer 21, but the disclosure is not limited thereto.

As shown in fig. 8, the motherboard to be cut of the embodiment of the present disclosure may further include a light emitting structure. The light emitting structure may be provided at a side of the drive transistor facing away from the substrate 1. The light emitting structure may include first and second electrodes 24 and 26 disposed opposite to each other, and a light emitting layer 25 between the first and second electrodes 24 and 26. The light-emitting layer 25 may be an organic electroluminescent layer, or may be a quantum dot light-emitting layer, which is not particularly limited in the embodiment of the present disclosure. The first electrode 24 may be an anode and the second electrode 26 may be a cathode, but the disclosure is not limited thereto. The first electrode 24 may be disposed on a side of the second planarization layer 23 facing away from the substrate 1, and electrically connected to the second source-drain electrode layer 22 via a via hole penetrating the second planarization layer 23. The motherboard to be cut of the present disclosure may also include a pixel defining layer 27. The pixel defining layer 27 covers the second planarization layer 23 and the first electrode 24. The pixel defining layer 27 is provided with a pixel opening exposing the first electrode 24. The light emitting layer 25 of the light emitting structure may be provided on a side of the first electrode 24 facing away from the substrate 1. The second electrode 26 of the light emitting structure is arranged on the side of the light emitting layer 25 facing away from the substrate 1. The display panel of the present disclosure may further include an encapsulation layer. The encapsulation layer may cover the light emitting structure. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The first inorganic packaging layer and the second inorganic packaging layer are oppositely arranged, and the organic packaging layer is coated between the first inorganic packaging layer and the second inorganic packaging layer.

The embodiment of the disclosure also provides a preparation method of the display panel. The manufacturing method of the display panel can comprise the steps of providing the mother board to be cut according to any embodiment, and cutting the mother board to be cut along the cutting area 300 to form the display panel. The dicing line may be a boundary between the dicing area 300 and the first area 201, but the embodiment of the disclosure is not limited thereto.

The embodiment of the disclosure also provides a display panel. The display panel can be prepared by the preparation method of the display panel.

The embodiment of the disclosure also provides a display module. As shown in fig. 9, 10, 13 and 14, the display module may include an external circuit board 600 and the display panel described above. The external circuit board 600 may be in bonded connection with the portion of the signal line 28 located in the first region 201. The external circuit board 600 may include a substrate 10 and pins 9. The substrate 10 may be a flexible substrate, such as a PI substrate or the like. The material of the pins 9 may be copper or the like. The pins 9 may be bonded to the signal lines 28 by conductive adhesive 8 (ACF adhesive). In addition, the side of the pin 9 facing away from the substrate 10 may also be provided with a protective glue 12 (SR). Wherein, the partial area of the pin 9 is not covered by the protective adhesive 12, so as to be convenient for binding. Taking the number of pad areas 200 as a plurality of examples, the signal lines 28 of each pad area 200 may be bonded to one external circuit board 600, and a plurality of external circuit boards 600 may be connected through the connection circuit board 700. In addition, the display module assembly may further include a positive photoresist 13 and a back photoresist 11. The positive glue 13 is adhered to one end of the external circuit board 600 near the display area 400, and covers the conductive glue 8, the pins 9 and the second insulating layer 4. The protective paste 12, the positive paste 13 and the negative paste 11 may be insulating materials. The display module can be a mobile phone display module or a computer display module, and of course, the display module can also be a television display module and the like.

The mother board to be cut, the preparation method of the display panel, the display panel and the display module provided by the embodiment of the disclosure belong to the same inventive concept, and descriptions of related details and beneficial effects can be referred to each other, and are not repeated.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure in any way, although the present disclosure has been described in terms of the preferred embodiment, it is not intended to limit the present disclosure, and any person skilled in the art will recognize that the present disclosure is not limited thereto, while the above-described technical disclosure may be utilized to make a few changes or modifications to equivalent embodiments, any simple modification, equivalent changes and modification made to the above embodiments according to the technical disclosure without departing from the disclosure of the technical disclosure still fall within the scope of the technical disclosure.

Claims (14)

1. A motherboard to be cut, the motherboard to be cut including a display area and a peripheral area, the peripheral area surrounding the display area, the peripheral area including a pad area and a cutting area, the pad area being located between the cutting area and the display area, the motherboard to be cut comprising:

A substrate;

The wiring structure is arranged on one side of the substrate, and the part of the wiring structure, which is positioned in the pad area, comprises a plurality of signal lines which are arranged in parallel, wherein the pad area comprises a first area and a second area in the extending direction of the signal lines, the first area is positioned between the second area and the display area, the part of the signal line, which is positioned in the first area, can be in binding connection with an external circuit board, and the part of the signal line, which is positioned in the second area, is divided into a plurality of line segments which are arranged in an insulating way by a strip-shaped groove which is intersected with the extending direction of the signal line in the extending direction of the signal line;

the insulating glue fills the strip-shaped groove, wherein,

The distance between the boundary between the first area and the second area and the strip-shaped groove is larger than the distance between the strip-shaped groove and the boundary between the second area and the cutting area, the cutting area is adjacent to the second area, and the width of the part of the signal line located in the first area is larger than the width of the part of the signal line located in the second area.

2. The motherboard to be cut according to claim 1, wherein the second area is provided with one or more of the bar-shaped grooves penetrating the routing structure in a depth direction of the bar-shaped groove.

3. The motherboard to be cut according to claim 1, wherein the insulating glue is a photosensitive glue or a heat-sensitive glue.

4. The motherboard to be cut according to claim 2, wherein the stripe-shaped groove extends into the substrate in a depth direction of the stripe-shaped groove.

5. The motherboard to be cut according to claim 4, wherein a distance between a boundary line between the first region and the second region and the stripe-shaped groove is greater than 145 μm, and a distance between the stripe-shaped groove and a boundary line between the second region and the cutting region is 45 μm to 105 μm.

6. The motherboard to be cut according to claim 2, wherein the extending direction of the bar-shaped groove is perpendicular to the extending direction of the signal line.

7. The motherboard to be cut according to claim 2, wherein the number of the pad areas is plural, and the plural pad areas are distributed among the pad areas in a direction perpendicular to the extending direction of the signal line;

One of the stripe grooves is disposed to cross the signal lines in at least two of the pad regions, or one of the stripe grooves is disposed to cross the signal lines in only one of the pad regions.

8. The motherboard to be cut according to claim 2, wherein the number of the strip-shaped grooves is plural, and at least two of the strip-shaped grooves are arranged at intervals in the extending direction of the signal line.

9. The motherboard to be cut according to claim 1, wherein the motherboard to be cut comprises:

the first insulating layer is arranged on the substrate, and the wiring structure is arranged on one side, far away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, far away from the substrate, of the wiring structure, a window is formed in the second insulating layer, and the part, located in the second area, of the signal wire is exposed through the window.

10. The motherboard to be cut according to claim 1, further comprising a thin film transistor comprising:

an active layer disposed on the substrate;

the first gate insulating layer is arranged on the substrate and covers the active layer;

the first gate electrode layer is arranged on one side of the first gate insulating layer, which is far away from the substrate;

a second gate insulating layer covering the first gate electrode layer and the first gate insulating layer;

the second gate electrode layer is arranged on one side of the second gate insulating layer, which is far away from the substrate;

an interlayer insulating layer covering the second gate electrode layer and the second gate insulating layer;

the first source-drain electrode layer is arranged on one side of the interlayer insulating layer away from the substrate and is connected with the active layer;

a first planarization layer covering the first source-drain electrode layer and the interlayer insulating layer;

the signal line comprises a first welding pad, and the first source-drain electrode layer and the first welding pad are arranged on the same layer.

11. The motherboard to be diced according to claim 10, wherein said signal line further comprises a second pad and a third pad, said second pad being arranged in a same layer as said second gate electrode layer, said third pad being arranged in a same layer as said first gate electrode layer, said first pad being connected to said second pad, said second pad being connected to said third pad.

12. A method for manufacturing a display panel, comprising:

providing a motherboard to be cut as claimed in any one of claims 1 to 11;

And cutting the mother board to be cut along the cutting area to form the display panel.

13. A display panel prepared by the method of preparing a display panel of claim 12.

14. A display module, comprising:

the display panel of claim 13;

and the external circuit board is in binding connection with the part of the signal line, which is positioned in the first area.