CN114709222A

CN114709222A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN114709222A
Application number: CN202210167253.2A
Authority: CN
Inventors: 李永亮; 赵飞; 罗军; 王文武
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2022-02-23
Filing date: 2022-02-23
Publication date: 2022-07-05

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for inhibiting electric leakage of a parasitic channel in a gate-all-around transistor and improving the working performance of the semiconductor device comprising the gate-all-around transistor. The semiconductor device includes: the semiconductor device comprises a substrate, a gate all around transistor and an isolation layer. The gate-all-around transistor is formed on the substrate. The isolation layer is at least filled between the substrate and the gate stack structure of the gate-all-around transistor, and the isolation layer is at least positioned below the channel of the gate-all-around transistor. The area of the isolation layer covering the substrate is smaller than or equal to the area of the gate stack structure covering the substrate. The manufacturing method of the semiconductor device provided by the invention is used for manufacturing the semiconductor device.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background

Compared with a fin field effect transistor, the gate stack structure of the gate-all-around transistor is formed on the top and the side wall of the channel and the bottom of the channel, so that the short channel effect can be inhibited, and the gate control capability of the gate-all-around transistor is enhanced.

However, in the case where the gate-all-around transistor has a channel including at least one layer of nanosheets, it is difficult to suppress leakage of a parasitic channel in the gate-all-around transistor using the existing punchthrough-preventing implantation process, thereby reducing the operating performance of the gate-all-around transistor.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for inhibiting the leakage of a parasitic channel in a gate-all-around transistor and improving the working performance of the semiconductor device comprising the gate-all-around transistor.

In order to achieve the above object, the present invention provides a semiconductor device comprising: the semiconductor device comprises a substrate, a gate all around transistor and an isolation layer.

The gate-all-around transistor is formed on the substrate. The isolation layer is at least filled between the substrate and the gate stack structure of the gate-all-around transistor, and the isolation layer is at least positioned below the channel of the gate-all-around transistor. The area of the isolation layer covering the substrate is smaller than or equal to the area of the gate stack structure covering the substrate.

Compared with the prior art, the semiconductor device provided by the invention has the advantages that the isolation layer is at least filled between the substrate and the gate stack structure of the gate-all-around transistor, and the isolation layer is at least positioned below the channel of the gate-all-around transistor. That is, the isolation layer isolates a portion of the gate stack structure located under the channel that the gate-all-around transistor has from the substrate. In this case, since the isolation layer has an isolation characteristic, even if a voltage of a corresponding magnitude is applied to the gate stack structure in the working process of the semiconductor device provided by the present invention, the semiconductor structure located below the channel is not turned on, thereby suppressing parasitic channel leakage and improving the working performance of the semiconductor device.

The present invention also provides a method of manufacturing a semiconductor device, the method of manufacturing the semiconductor device including:

a substrate is provided.

A gate-all-around transistor and an isolation layer are formed on a substrate. The isolation layer is at least filled between the substrate and the gate stack structure of the gate-all-around transistor, and the isolation layer is at least positioned below the channel of the gate-all-around transistor. The area of the isolation layer covering the substrate is smaller than or equal to the area of the gate stack structure covering the substrate.

Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as the semiconductor device provided by the invention, and the details are not repeated herein.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

figure 1 is a schematic diagram of a structure after forming a first fin structure and a barrier layer on a substrate;

FIG. 2 is a cross-sectional view of a structure after a FinFET is formed on a substrate;

figure 3 is a cross-sectional view of the second fin structure after being processed using a punch-through implant process;

fig. 4 is a cross-sectional view of the structure after a gate-all-around transistor is formed based on the second fin structure;

FIG. 5 is a schematic structural diagram of a pre-formed layer and at least one stacked material layer formed on a substrate according to an embodiment of the present invention;

figure 6 is a schematic diagram illustrating a fin structure formed on a substrate in accordance with an embodiment of the present invention;

FIG. 7 is a schematic diagram of a structure after shallow trench isolation is formed on a substrate in an embodiment of the present invention;

FIG. 8 is a cross-sectional view of the first structure taken along line A-A' of the structure of FIG. 7;

FIG. 9 is a cross-sectional view of the second construction taken along line A-A' of the construction of FIG. 7;

FIG. 10 is a cross-sectional view of a third construction taken along line A-A' of the construction of FIG. 7;

fig. 11 is a schematic structural diagram after forming a sacrificial gate and a sidewall spacer in the embodiment of the present invention;

FIG. 12 is a schematic view of a first structure after forming source and drain regions in an embodiment of the invention;

FIG. 13 is a cross-sectional view of a first structure taken along A-A' after source and drain regions are formed in accordance with an embodiment of the present invention;

FIG. 14 is a cross-sectional view taken along A-A' of a second structure after forming source and drain regions in accordance with an embodiment of the present invention;

FIG. 15 is a cross-sectional view taken along A-A' of a third structure after source and drain regions have been formed in accordance with an embodiment of the present invention;

FIG. 16 is a schematic diagram of a fourth structure after forming source and drain regions in an embodiment of the invention;

FIG. 17 is a cross-sectional view of a fourth structure taken along line A-A' after source and drain regions have been formed in accordance with an embodiment of the present invention;

FIG. 18 is a schematic structural diagram illustrating a structure after a dielectric layer is formed and a sacrificial gate is removed in an embodiment of the present invention;

FIG. 19 is a cross-sectional view of the structure taken along the direction A-A' after a dielectric layer is formed and a sacrificial gate is removed in an embodiment of the present invention;

FIG. 20 is a cross-sectional view of the structure taken along line B-B' after a dielectric layer is formed and a sacrificial gate is removed in an embodiment of the present invention;

FIG. 21 is a cross-sectional view taken along A-A' of a preformed structure after removal of portions of the structure underlying at least one of the stacked layers in an embodiment of the present invention;

FIG. 22 is a cross-sectional view taken along A-A' of the structure after removal of the sacrificial layer and the portion of the preformed structure underlying the at least one stack layer in an embodiment of the present invention;

FIG. 23 is a cross-sectional view taken along A-A' of the first structure after forming a layer of spacer material in accordance with an embodiment of the present invention;

FIG. 24 is a cross-sectional view taken along line B-B' of the first structure after forming a layer of spacer material in accordance with an embodiment of the present invention;

FIG. 25 is a cross-sectional view taken along A-A' of a second structure after a layer of spacer material has been formed in accordance with an embodiment of the present invention;

FIG. 26 is a cross-sectional view taken along line B-B' of the second structure after a layer of spacer material has been formed in accordance with an embodiment of the present invention;

FIG. 27 is a schematic view of a first structure after forming an isolation layer in an embodiment of the invention;

FIG. 28 is a cross-sectional view of a first structure taken along line A-A' after forming a spacer layer in accordance with an embodiment of the present invention;

FIG. 29 is a cross-sectional view of a first structure taken along line B-B' after forming a spacer layer in accordance with an embodiment of the present invention;

FIG. 30 is a cross-sectional view taken along line B-B' of a second structure after forming a spacer layer in accordance with an embodiment of the present invention;

FIG. 31 is a schematic view of a third structure after forming an isolation layer in an embodiment of the invention;

FIG. 32 is a cross-sectional view of a third structure taken along line B-B' after forming a spacer layer in accordance with an embodiment of the present invention;

FIG. 33 is a cross-sectional view taken along A-A' of the first structure after forming a gate-all-around transistor in an embodiment of the present invention;

FIG. 34 is a cross-sectional view taken along line B-B' of the first structure after forming a gate-all-around transistor in accordance with an embodiment of the present invention;

FIG. 35 is a cross-sectional view taken along line B-B' of the second structure after a gate-all-around transistor is formed in accordance with an embodiment of the present invention;

FIG. 36 is a cross-sectional view taken along line B-B' of a third structure after a gate-all-around transistor has been formed in accordance with an embodiment of the present invention;

fig. 37 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Reference numerals: 11 is a substrate, 12 is a preformed layer, 121 is a preformed structure, 13 is a laminated material layer, 131 is a sacrificial material layer, 1311 is a sacrificial layer, 132 is a channel material layer, 1321 is a channel layer, 133 is a laminated layer, 14 is a fin structure, 141 is a fin portion, 1411 is a source region forming region, 1412 is a drain region forming region, 1413 is a transition region, 15 is shallow trench isolation, 16 is a sacrificial gate, 17 is a sidewall, 18 is a source region, 19 is a drain region, 20 is a dielectric layer, 21 is a gate forming region, 22 is an isolation material layer, 221 is an isolation layer, 2211 is a middle region, 2212 is an outer region, 23 is a channel, 231 is a nanosheet, 24 is a gate stack structure, 241 is a gate dielectric layer, 242 is a gate, 25 is a ring gate transistor, 26 is a first fin structure, 27 is a barrier layer, 28 is a second fin structure, and 29 is a central region.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions, layers and their relative sizes, positional relationships are shown in the drawings as examples only, and in practice deviations due to manufacturing tolerances or technical limitations are possible, and a person skilled in the art may additionally design regions/layers with different shapes, sizes, relative positions according to the actual needs.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The fin field effect transistor has a first fin structure and a shallow trench isolation formed on a substrate. The part of the first fin-shaped structure exposed outside the shallow trench isolation is a fin part. The portion of the fin surrounded by the gate stack corresponds to a channel of the finfet. In this case, when the fin field effect is in an operating state, the channel is controlled by the gate stack structure, thereby enabling conduction between the source region and the drain region. And the part of the first fin-shaped structure surrounded by the shallow trench isolation is separated from the gate stack structure by the shallow trench isolation, so that the part is far away from the control of the gate stack structure, and channel punch-through effect is easy to occur, and a parasitic channel is caused.

As shown in fig. 1 and 2, in order to solve the problem of parasitic channel leakage in the finfet, after forming the first fin structure 26 and the shallow trench isolation 15 on the substrate 11 in the process of manufacturing the finfet, impurity ions of a conductivity type opposite to that of impurities doped in source and drain regions are implanted at least into the first fin structure 26 through a punch-through implantation process to form a barrier layer 27 at a middle lower portion of the first fin structure 26, so that a parasitic channel is suppressed by the highly doped barrier layer 27.

With the development of semiconductor technology, gate-all-around transistors are produced in time. Compared with a fin field effect transistor, the gate stack structure of the gate-all-around transistor is formed on the top and the side wall of the channel and the bottom of the channel, so that the gate control capability of the gate-all-around transistor can be enhanced, the short channel effect is inhibited, and the gate-all-around transistor has higher working performance. However, in the case where the pass-through prevention implantation process is performed, it is difficult to solve the problem of parasitic channel leakage in the pass-through prevention transistor in the case where the pass-through prevention transistor has a wide channel width. Specifically, as shown in fig. 3 and 4, in the process of manufacturing the gate-all-around transistor, since the gate-all-around transistor has a wider width of the channel 23, the second fin structure 28 formed on the substrate 11 also has a wider width. Based on this, when the ion impurities are implanted into the second fin structure 28 by the punch-through prevention implantation process, the ion impurities are difficult to enter the central region 29 of the second fin structure 28 in the width direction thereof, that is, the central region 29 of the second fin structure 28 in the width direction thereof does not completely form the barrier layer 27. In this case, after a proper voltage is applied to the gate stack structure 24 of the gate-all-around transistor, the source region and the drain region can be conducted through the channel, and the central region 29 has a parasitic channel leakage problem, thereby reducing the operating performance of the gate-all-around transistor.

In order to solve the above technical problem, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiment of the invention, at least the isolation layer is filled between the substrate and the gate stack structure of the gate-all-around transistor, and the isolation layer is positioned between the source region and the drain region of the gate-all-around transistor, so that the part of the gate stack structure positioned below the channel of the gate-all-around transistor can be isolated from the substrate through the isolation layer, the semiconductor structure positioned below the channel can not be conducted, the parasitic channel leakage can be inhibited, and the working performance of the semiconductor device can be improved.

As shown in fig. 33 to 36, an embodiment of the present invention provides a semiconductor device including: substrate 11, gate-all-around transistor 25, and isolation layer 221. The gate-all-around transistor 25 described above is formed on the substrate 11. The isolation layer 221 is at least filled between the substrate 11 and the gate stack structure 24 of the gate-all-around transistor 25, and the isolation layer 221 is at least located below the channel of the gate-all-around transistor 25. The area of the isolation layer 221 covering the substrate 11 is less than or equal to the area of the gate stack structure 24 covering the substrate 11.

As for the above substrate, the substrate may beThe substrate is any semiconductor substrate such as a silicon substrate, a silicon-on-insulator substrate, or a silicon germanium substrate. In some cases, a shallow trench isolation is formed on the substrate to define an active region. As for the material contained in the shallow trench isolation, SiN and Si can be used₃N₄、SiO₂Or an insulating material such as SiCO.

As shown in fig. 33 to 36, the gate-all-around transistor 25 may include a source region 18, a drain region 19, a channel 23, and a gate stack structure 24. As shown in fig. 8 to 15, the source region 18 and the drain region 19 are formed at different specific positions according to the formation range of the source region 18 and the drain region 19 during the manufacturing process. As shown in fig. 13, when the formation range of the source region 18 and the drain region 19 is large, the source region 18 and the drain region 19 may be formed on the substrate 11 at an interval. Alternatively, as shown in fig. 14 and fig. 15, when the formation range of the source region 18 and the drain region 19 is small, the source region 18 and the drain region 19 may be formed at an interval on the surface of the preformed structure 121 (the preformed structure 121 is a structure formed in advance for forming the isolation layer 221, and the manufacturing method will be described in detail below, and will not be described herein) or at an interval above the preformed structure 121. As shown in fig. 12 to 15, the source region 18 and the drain region 19 may be formed on the substrate 11 by etching, epitaxial growth, and the like after forming the sacrificial gate 16 and the sidewall 17. Alternatively, as shown in fig. 16 and 17, the source region 18 and the drain region 19 may be formed by directly performing ion implantation on the source region formation region and the drain region formation region. The channel 23 is located between the source region 18 and the drain region 19, and the channel 23 is in contact with the source region 18 and the drain region 19. The channel 23 has at least one layer of nanosheets 231 spaced apart along the thickness of the substrate 11. The nanosheet 231 located lowermost is spaced from the substrate 11. The number of the layers of the nanosheets 231, the interval between adjacent nanosheets 231, and the number of the nanosheets 231 may be set according to actual requirements, and is not specifically limited herein. And the spacing of the nanosheet 231 located lowermost from the substrate 11 may be set according to the specifications of the gate stack structure 24 and the layer thickness of the isolation layer 221. The gate stack 24 surrounds the channel 23. Specifically, the gate stack structure 24 includes a gate dielectric layer 241 surrounding the channel 23, and a gate electrode 242 formed on the gate dielectric layer 241. The thickness of the gate dielectric layer 241 and the specification of the gate electrode 242 may be set according to actual conditions.

The materials contained in the source region, the drain region and the at least one layer of nano-sheets are semiconductor materials. Specifically, the material contained in the source region and the drain region may be set according to practical circumstances, and is not particularly limited herein. The source region and the drain region may be made of the same or different materials. The material contained in the at least one layer of nanoplatelets may be Si_1-xGe_x. Wherein x is more than or equal to 0 and less than or equal to 1. For example: the material contained in at least one layer of nano-sheet can be Si or Si_0.5Ge_0.5Or Ge, etc.

The gate dielectric layer may contain HfO₂、ZrO₂、TiO₂Or Al₂O₃And materials with higher dielectric constants. The material contained in the grid can be TiN, TaN or TiSiN and other conductive materials.

In some cases, as shown in fig. 33 to fig. 36, the gate-all-around transistor 25 may further include a spacer 17 and a dielectric layer 20. The dielectric layer 20 covers at least the surface of the source region 18 facing away from the substrate 11 and covers at least the surface of the drain region 19 facing away from the substrate 11. The top of dielectric layer 20 may be flush with the top of gate stack structure 24. It is to be understood that in the process of manufacturing the semiconductor device provided by the embodiment of the present invention, as shown in fig. 18 to 32, the presence of the dielectric layer 20 may protect the source region 18 and the drain region 19 from etching, cleaning, and the like when etching the sacrificial gate and the sacrificial layer 1311. Specifically, the material contained in the dielectric layer 20 may be SiO₂Or an insulating material such as SiN.

For the side wall, the side wall can be formed between the dielectric layer and the gate stack structure so as to form the gate stack structure surrounding the periphery of the channel and isolate the gate stack structure from a subsequently formed conductive structure, and the yield of the semiconductor device is improved. The side wall is made of insulating materials. Specifically, the material contained in the side wall and the thickness of the side wall may be designed according to an actual application scenario, and are not specifically limited herein.

As shown in fig. 36, along the length extension direction of the isolation layer 221, the isolation layer 221 may be filled only between the substrate 11 and the gate stack structure 24, i.e., the isolation layer 221 is located only under the channel. At this time, the area of the isolation layer 221 covering the substrate 11 is smaller than the area of the gate stack structure 24 covering the substrate 11. Alternatively, as shown in fig. 33 to 35, the isolation layer 221 may be filled between the gate stack structure 24 and the substrate 11 and between the gate stack structure 24 and the shallow trench isolation 15 along the length extension direction of the isolation layer 221. At this time, the area of the isolation layer 221 covering the substrate 11 is equal to the area of the gate stack structure 24 covering the substrate 11. As for the height of the bottom surface of the isolation layer 221, it may be set according to practical application scenarios as long as it can be applied to the semiconductor device provided in the embodiment of the present invention. Illustratively, the bottom surface of the isolation layer 221 may be flush with the bottom surfaces of the source region 18 and the drain region 19 of the gate-all-around transistor 25.

Illustratively, as shown in fig. 33 to 35, in the case where the area of the isolation layer 221 covering the substrate 11 is equal to the area of the gate stack structure covering the substrate 11, the isolation layer 221 has a middle region 2211 and an outer region 2212 along the length extension direction of the isolation layer 221. The middle region 2211 is a region where the isolation layer 221 is located below the channel 23. Outer regions 2212 are located on either side of middle region 2211. The top height of the middle region 2211 is greater than or equal to the top height of the outer regions 2212.

In practical applications, as shown in fig. 21 to 32, the isolation layer 221 is obtained by performing an etching back process on the isolation material layer 22 formed in at least a portion of the gate formation region and the hollow region between the at least one stack 133 and the substrate 11. During the etching back process, under the mask action of the channel layer 1321 at the topmost layer, a portion of the isolation material layer 22 under the at least one stack layer 133 is retained, so that the portion corresponds to a portion of the isolation layer 221 in the middle region 2211. Along the length extension direction of the gate formation region, the portions of the isolation material layer 22 on both sides of the middle region 2211 are not protected by the topmost channel layer 1321, so after the isolation material layer 22 is etched back to obtain the isolation layer 221, the height of the top of the isolation layer 221 in the outer region 2212 is less than or equal to the height of the top of the isolation layer 221 in the middle region 2211. Specifically, when the heights of the tops of the two areas are different, the height difference between the two areas can be determined according to actual conditions. Therefore, the thickness of the portion of the isolation layer 221 located in the outer region 2212 may have many possible situations as long as the top height of the middle region 2211 is greater than or equal to the top height of the outer region 2212, so that it is not necessary to strictly control the etching conditions in the etching back process of the isolation material layer 22 in order to obtain the isolation layer 221 only formed in the hollow region, or obtain the isolation layer 221 with the middle region 2211 equal to the top height of the outer region 2212, thereby reducing the etching difficulty of the etching back process.

In addition, as described above, the specific formation positions of the source region and the drain region are different according to the formation range of the source region and the drain region in the manufacturing process. Correspondingly, the relative position relationship between the source region, the drain region and the isolation layer is different. Specifically, at least part of the isolation layer is positioned between the source region and the drain region of the gate-all-around transistor. Alternatively, the isolation layer is located below a region between the source region and the drain region of the gate-all-around transistor.

And when the forming range of the source region and the drain region is large, the source region and the drain region are positioned on the substrate. And the isolation layer is positioned between the source region and the drain region and is respectively contacted with the source region and the drain region. And when the partial forming range of the source region and the drain region is positioned in the etched part of the preformed layer, the source region and the drain region are positioned on the surface of the preformed structure. And, a portion of the isolation layer is located between and in contact with the source region and the drain region. When the forming range of the source region and the drain region is small, the source region and the drain region are located above the preformed structure. And, the isolation layer is located under a region between the source region and the drain region.

The material contained in the isolation layer can be set according to actual requirements. Illustratively, the isolation layer comprises a dielectric material including silicon oxide, silicon nitride, silicon oxycarbide, and the like. The thickness of the isolation layer may be 3nm to 50 nm. Of course, the layer thickness of the isolating layer can also be set to other suitable thickness values. Preferably, the layer thickness of the isolation layer is 10nm to 15 nm.

As can be seen from the above, as shown in fig. 33 to 36, the isolation layer 221 of the semiconductor device according to the embodiment of the present invention can isolate the portion of the gate stack structure 24 located under the channel 23 of the gate-all-around transistor 25 from the substrate 11. In this case, since the isolation layer 221 has an isolation characteristic, even if a voltage of a corresponding magnitude is applied to the gate stack structure 24 during operation of the semiconductor device provided in the embodiment of the present invention, the semiconductor structures such as the substrate 11 located below the channel 23 will not be turned on, so that parasitic channel leakage can be suppressed, and the operating performance of the semiconductor device can be improved.

As shown in fig. 37, the embodiment of the invention also provides a method for manufacturing a semiconductor device. The manufacturing process will be described below based on the perspective and cross-sectional views of the operation shown in fig. 5 to 36. Specifically, the manufacturing method of the semiconductor device includes:

first, a substrate is provided. For details of the substrate, reference may be made to the foregoing description, and details are not repeated here.

As shown in fig. 5 to 36, a gate-all-around transistor 25 and an isolation layer 221 are formed on a substrate 11. The isolation layer 221 is at least filled between the substrate 11 and the gate stack structure 24 of the gate-all-around transistor 25, and the isolation layer 221 is at least located under the channel of the gate-all-around transistor 25. The area of the isolation layer 221 covering the substrate 11 is less than or equal to the area of the gate stack structure 24 covering the substrate 11.

Specifically, the structure of the gate all around transistor, the material contained in the isolation layer, and the specification of the isolation layer may refer to the foregoing, and are not described herein again.

In one example, as shown in fig. 5 to 32, forming the isolation layer 221 on the substrate 11 may include the steps of:

as shown in fig. 5 to 17, a pre-formed structure 121 and a stacked structure (not shown) are formed on the substrate 11. The stack structure includes at least one stack layer 133, and a gate-all-around transistor having a source region 18 and a drain region 19. At least one layer of the stack 133 is positioned on the preform structure 121. At least one stack 133 is located between the source region 18 and the drain region 19, and at least one stack 133 is in contact with the source region 18 and the drain region 19. Each stack 133 includes a sacrificial layer 1311, and a channel layer 1321 on the sacrificial layer 1311.

Specifically, the structures of the source region and the drain region, and the materials contained in the source region and the drain region, etc. can be referred to above, and are not described herein again. As shown in fig. 12 to 17, as for the relative positional relationship between the source region 18 and the drain region 19 and the preform structure 121, the formation range of the source region 18 and the drain region 19 is concerned. Specifically, the positional relationship between the source region 18 and the drain region 19 and the preform structure 121 is classified into the following three types:

the first method comprises the following steps: as shown in fig. 12 and 13, and fig. 16 and 17, the source region 18 and the drain region 19 may both be located on the substrate 11. The preformed structure 121 is located between the source region 18 and the drain region 19 and the preformed structure 121 is in contact with the source region 18 and the drain region 19.

And the second method comprises the following steps: as shown in fig. 14, the source region 18 and the drain region 19 may both be located on the preformed structure 121 with the bottom surface of the stacked structure in contact with the top surface of the preformed structure 121.

And the third is that: as shown in fig. 15, the source region 18 and the drain region 19 may both be located above the pre-formed structure 121.

As can be seen from the above, the forming range of the source region and the drain region has a plurality of possible implementation schemes, so that the manufacturing method of the semiconductor device provided by the embodiment of the present invention has the characteristic of diversified forming manners, thereby reducing the manufacturing difficulty.

The channel layer is a film layer in which the at least one nanosheet is formed, and therefore the number of stacked layers on the preformed structure can be set according to the number of layers of the nanosheets in the channel. For example: when the channel has two layers of nanosheets, a two-layer stack needs to be formed on the preformed structure. The material contained in the channel layer may be provided according to the material contained in the nanosheet. Illustratively, the channel layer may comprise a material that is Si_1-xGe_x. Wherein x is more than or equal to 0 and less than or equal to 1. The material contained in the sacrificial layer may be Si_1-yGe_y. Wherein y is more than or equal to 0 and less than or equal to 1, and | x-y | is more than or equal to 0.2. Based on this, the sacrificial layer and the channel layer containThe materials have a certain etching selection ratio, so that when the sacrificial layer is removed to form corresponding nano-sheets on each channel layer, the channel layer is not influenced by operations such as etching and the like, and the yield of the semiconductor device is improved.

For the above preformed structure, the area of the preformed structure under the at least one stacked layer (hereinafter, the hollow area) is the area where at least a part of the isolation layer is located. The area is subsequently released by removing the part of the preformed structure below the at least one layer stack, whereby the thickness of the part of the preformed structure below the at least one layer stack is equal to the layer thickness of the isolation layer. For example: the thickness of the portion of the preformed structure underlying the at least one stack of layers may be in the range 3nm to 50 nm. Further, the material contained in the above preformed structure may be Si_1-zGe_z(ii) a Wherein z is more than or equal to 0 and less than or equal to 1, and | x-z | > or equal to 0.25, so as to form at least one laminated layer on the preformed structure by means of epitaxial growth. Meanwhile, a certain etching selection ratio exists between the preformed structure and the materials contained in the channel layer, so that the channel layer is not influenced by operations such as etching when the part of the preformed structure below at least one laminated layer is removed, and the yield of the semiconductor device is improved. In addition, the material contained in the preformed structure needs to have a certain etching selection ratio with the material contained in the substrate. Based on this, as shown in fig. 21 and fig. 22, in the process of removing the portion of the preformed structure located below the at least one stacked layer 133 to obtain the hollowed-out region, the etchant for etching the preformed structure does not affect the substrate, and the yield of the semiconductor device is improved.

Specifically, the material contained in the sacrificial layer may be the same as or different from the material contained in the preform structure. In addition, in the case where the channel layer, the sacrificial layer, and the preformed structure all contain germanium, the difference in the germanium content among the three may be set according to practical circumstances as long as it can be applied to the method for manufacturing a semiconductor device provided by the embodiment of the present invention. For example: the material included in the channel layer may be Si. The sacrificial layer may contain Si_0.7Ge_0.3. The above preformed structureThe material contained may be Si_0.5Ge_0.5、Si_0.7Ge_0.3Or Ge.

Illustratively, as shown in fig. 5 to 17, the above-mentioned forming of the preformed structure 121 and the stacked structure on the substrate 11 may include the following steps:

as shown in fig. 5, a pre-formed layer 12 and at least one laminated material layer 13 are sequentially formed on a substrate 11 along a thickness direction of the substrate 11.

Specifically, as shown in fig. 5 to 17, the preformed layer 12 is a film layer for forming the preformed structure 121, so the thickness of the preformed layer 12 is equal to the thickness of the portion of the preformed structure 121 located below the at least one stacked layer. As shown in fig. 5 to 17, the at least one laminated material layer 13 is at least a film layer for forming the at least one laminated layer 133, so that the number of laminated material layers 13 is equal to the number of laminated layers 133. The sacrificial material layer 131 included in the stacked material layer 13 is the same as the sacrificial layer 1311 included in the stacked material layer 133. The channel material layer 132 included in the stacked material layer 13 is the same as the channel layer 1321 included in the stacked layer 133.

In practical application, the above preformed layer and at least one stacked material layer may be sequentially formed on the substrate by using processes such as epitaxial growth.

As shown in fig. 6, a fin structure 14 extending along a first direction is formed by etching a portion of the substrate 11 from the top of at least one stacked material layer. The first direction may be any direction parallel to the surface of the substrate 11.

In the actual application process, etching can be performed according to the etching condition through photoetching and etching processes. Specifically, a photoresist layer may be formed on the topmost stacked material layer. And developing and exposing the photoresist layer to form a photoresist mask on the topmost laminated material layer. The photoresist mask covers the area where the fin structure is to be formed. And etching the top of the at least one laminated material layer to a part of the substrate by an etching process under the mask action of the photoresist mask to obtain the fin-shaped structure. As shown in fig. 6 and 7, the substrate 11 is etched to a depth equal to or greater than the thickness of the shallow trench isolation 15.

As shown in fig. 7 to 10, shallow trench isolations 15 are formed on portions of the substrate 11 exposed outside the fin structures. The portion of the fin structure exposed outside the shallow trench isolation 15 is a fin 141. The fin 141 has a source region formation region 1411 for forming at least a part of a source region, a drain region formation region 1412 for forming at least a part of a drain region, and a transition region for forming a channel and an isolation layer. The portion of the at least one laminated material layer within the transition zone 1413 is the at least one laminated layer 133.

In practical applications, a physical vapor deposition process or a chemical vapor deposition process may be used to form a dielectric material covering the substrate and the fin structure, and the dielectric material may be planarized to expose the top of the fin structure. And then, etching back the dielectric material to obtain the shallow trench isolation.

As shown in fig. 11, a sacrificial gate 16 and a sidewall 17 extending in the second direction are formed at the outer periphery of the transition region. The side walls 17 are at least located on two sides of the sacrificial gate 16 along the width direction. The second direction is different from the first direction.

Specifically, the second direction may be any direction parallel to the surface of the substrate and different from the first direction. Preferably, the second direction is orthogonal to the first direction.

In practical application, a gate material for forming a sacrificial gate may be deposited on the fin and the shallow trench isolation by using a chemical vapor deposition process. And then, etching the gate material by adopting a dry etching mode, and only keeping the part of the gate material, which is positioned at the periphery of the transition region, to obtain the sacrificial gate extending along the second direction. The gate material may be amorphous silicon, polysilicon, or other materials that are easily removed. As shown in fig. 11, after the sacrificial gate 16 is formed, the sidewall spacers 17 may be formed on the sidewalls of the sacrificial gate 16 in the above manner. The side walls 17 may be distributed on only two sides of the sacrificial gate 16 along the width direction of the sacrificial gate 16. Alternatively, the sidewall spacer may surround the sidewall of the sacrificial gate. The material contained in the side wall can be insulating material such as silicon nitride.

As shown in fig. 12 to 17, at least the source region formation region is processed to form a source region 18, and at least the drain region formation region is processed to form a drain region 19, resulting in a stacked structure; and so that the remaining part of the pre-formed layer forms the pre-formed structure 121.

In an actual application process, a dry etching process or a wet etching process may be used to remove the portions of the fin portion located in the source region formation region and the drain region formation region. As shown in fig. 12 and 15, a source region 18 is epitaxially formed in the source region formation region and a drain region 19 is epitaxially formed in the drain region formation region by epitaxial growth or the like, thereby obtaining a stacked structure. Alternatively, as shown in fig. 16 and 17, ion implantation may be directly performed on the fin portion in the source region formation region and the drain region formation region, so that the source region formation region corresponds to the source region 18, and the drain region formation region corresponds to the drain region 19. Specifically, the forming range of the source region and the drain region may refer to the foregoing, and details are not repeated here. While the remaining part of the preformed layer forms the preformed structure 121.

In addition, after the source region and the drain region are formed and the preformed structure is obtained, and before subsequent operations are performed, a physical vapor deposition process or a chemical vapor deposition process may be used to form a dielectric material covering the formed structure, and a chemical mechanical polishing process may be used to planarize the dielectric material to expose the top of the sacrificial gate. Wherein the dielectric material remains on the source region and the drain region to form a dielectric layer. Specifically, the materials contained in the dielectric layer may refer to the foregoing, and are not described herein again.

As shown in fig. 18 to 20, after forming the pre-formed structure 121 and the stacked structure on the substrate 11, before removing a portion of the pre-formed structure 121 located below the at least one stacked layer 133, the method for manufacturing a semiconductor device further includes: the sacrificial gate is removed so that the at least one stack 133 covered by the sacrificial gate and the portion of the preformed structure 121 located under the at least one stack 133 are exposed, facilitating the subsequent removal of the portion of the preformed structure 121 located under the at least one stack 133.

As shown in fig. 21 and 22, a portion of the preformed structure under the at least one stacked layer 133 is removed to form a hollow area (not shown) under the at least one stacked layer 133.

In practical applications, the material of the sacrificial layer comprised by the preformed structure and the at least one layer stack may be the same or different. As shown in fig. 21, when the two materials are different, only the portion of the preformed structure under the at least one stacked layer 133 may be removed. At this time, a hollowed-out region may be formed between the at least one stacked layer 133 and the substrate 11. As shown in fig. 22, when the preformed structure and the sacrificial layer contain the same material, the steps are: and removing the sacrificial layer and the part of the preformed structure below the at least one laminated layer to form a hollow-out area below the at least one laminated layer, and enabling the channel layer included in the at least one laminated layer to form a channel 23. That is, after the above-mentioned processing, not only the hollow region can be obtained, but also the channel layer can be released.

Specifically, the structure to be removed (the structure to be removed is a portion of the preformed structure located below the at least one stacked layer, or a portion of the preformed structure located below the at least one stacked layer and the sacrificial layer) may be directly removed by using a dry etching process or a wet etching process. Alternatively, the structure to be removed may be oxidized first. And then the structure to be removed after the oxidation treatment is corroded and removed by a wet etching process. The etchant and the etching conditions used in the dry etching process and the wet etching process, and the processing conditions of the oxidation treatment may be set according to actual situations, and are not specifically limited herein.

For example: the channel layer contains Si as a material. The sacrificial layer contains Si_0.7Ge_0.3. The preformed structure contains Si as the material_0.5Ge_0.5. In this case, the portion of the preformed structure under the at least one laminated layer may be subjected to an oxidation treatment at an oxidation temperature of 650 ℃ to 850 ℃ under the protection of nitrogen. The portion of the oxidized preformed structure underlying the at least one stack is then removed by a solution such as HF.

As shown in fig. 23 to 32, an isolation layer 221 is formed at least in the hollow region.

Specifically, as described above, referring to fig. 31 and 32, if the isolation layer 221 is only filled between the gate stack structure 24 and the substrate 11, the isolation layer 221 only needs to be formed in the hollow area. Referring to fig. 27 to 30, if the isolation layer 221 is formed between the gate stack structure 24 and the shallow trench isolation 15, and between the gate stack structure 24 and the substrate 11, the isolation layer 221 needs to be formed in the hollow area and the partial area released by removing the sacrificial gate.

For example, as shown in fig. 23 to 32, the forming of the isolation layer 221 at least in the hollow area may include the following steps:

as shown in fig. 23 to 26, the isolation material layer 22 is formed at least in the hollow area and a portion of the gate forming region 21. The gate forming region 21 is a region where a gate stack structure is formed.

It is to be understood that the region where the sacrifice layer is present belongs to a part of the gate forming region. Based on this, as shown in fig. 23 and 24, if the sacrificial layer 1311 is not removed while removing the portion of the preformed structure below the at least one stacked layer 133, the isolation material layer 22 needs to be formed in the hollow area and the portion of the gate formation region outside the area where the sacrificial layer 1311 is located. As shown in fig. 25 and 26, if the sacrificial layer is removed at the same time as the removal of the portion of the preformed structure located under the at least one stacked layer, the isolation material layer 22 needs to be formed in the hollow area and the gate formation area. Specifically, the isolation material filled in the above-mentioned region and covering the dielectric layer may be formed by using a chemical vapor deposition or physical vapor deposition process. And the isolation material is subjected to planarization treatment to obtain the isolation material layer 22, and all areas on the top of the isolation material layer 22 are leveled, so that the etched depths of all areas can be the same when the isolation material layer 22 is etched back subsequently, a sacrificial layer is removed or a gate stack structure is formed, and the yield of the semiconductor device is improved. The material contained in the spacer material layer 22 is a dielectric material, and the dielectric material includes silicon oxide, silicon nitride, silicon oxycarbide, and the like.

It is noted that the spacing between adjacent channel layers, and the spacing between the channel layers and the preformed structure, is small. If the sacrificial layer and the preformed structure comprise the same material, the sacrificial layer is removed at the same time as the removal of the part of the preformed structure located below the at least one layer stack. Therefore, the isolation material layer is also formed between the adjacent channel layers and between the channel layer and the hollow area, and when the isolation material layer is subjected to back etching treatment, the parts of the isolation material layer in the two areas are difficult to remove, so that the manufacturing difficulty of the semiconductor device can be reduced by setting the material contained in the preformed layer to be different from the material contained in the sacrificial layer.

As shown in fig. 27 to 32, the isolation material layer is etched back by using a wet etching process or a dry etching process, so that the remaining isolation material layer forms an isolation layer 221.

In practical applications, as shown in fig. 27 to 29, if the isolation layer 221 has a top height of the middle region 2211 equal to a top height of the outer region 2212, a wet etching process or a dry etching process may be used, and these two processes perform an etching back process on the isolation material layer. As shown in fig. 30 to 32, if the isolation layer 221 has a top height of the middle region 2211 smaller than a top height of the outer region 2212, or the isolation layer 221 is only located between the gate stack structure and the substrate 11, the isolation material layer may be etched back by using a dry etching process under the mask action of the dielectric layer 20 and the channel layer 1321 located at the top.

Specifically, the etchant and the etching conditions used in the dry etching process and the wet etching process may be set according to the material contained in the isolation material layer. For example: in the case where the material contained in the spacer material layer is silicon oxide, the spacer material layer may be subjected to an etching back treatment by an HF solution. Another example is: in the case where the material contained in the spacer material layer is silicon nitride, the spacer material layer may be subjected to the etching back process by hot phosphoric acid (the temperature of the hot phosphoric acid may be set as appropriate). For another example: in the case where the material contained in the spacer material layer is silicon oxide, the spacer material layer may be subjected to an etching back treatment by a fluorine-based gas.

In addition, whether to etch back the isolation material layer to a predetermined thickness may be determined according to the etching time of the dry etching process or the wet etching process and the etching strength of the etchant used by the dry etching process or the wet etching process.

In one example, in a case where the sacrificial layer and the pre-formed structure contain different materials, after forming an isolation layer on the substrate, a gate-all-around transistor is formed on the substrate, including the steps of: the sacrificial layer is removed such that the channel layer comprised by the at least one layer stack forms a channel. As shown in fig. 33 to 36, a gate stack structure 24 is formed around the periphery of the channel 23, obtaining a gate-all-around transistor 25.

Specifically, as described above, in the case that the sacrificial layer and the preformed structure contain different materials, when the part of the release hollow area of the preformed structure located below the at least one stack layer is removed, the sacrificial layer is not removed, and therefore the sacrificial layer needs to be removed before the gate stack structure is formed, so that each channel layer forms a corresponding nanosheet. Wherein, the sacrificial layer can be removed by wet etching and other processes. A gate stack structure surrounding the periphery of the channel may then be formed using a chemical vapor deposition process or the like.

In another example, in a case where the sacrificial layer and the pre-formed structure contain the same material, after forming an isolation layer on the substrate, forming a gate-all-around transistor on the substrate, the method includes: as shown in fig. 33 to 36, a gate stack structure 24 is formed around the periphery of the channel 23, obtaining a gate-all-around transistor 25.

Specifically, as described above, in the case where the sacrificial layer and the preformed structure contain the same material, the sacrificial layer is removed at the same time of removing the partial release via region of the preformed structure located below the at least one stack, so that the gate stack structure surrounding the periphery of the channel can be directly formed after the isolation layer is formed.

The specific structure of the gate stack structure and the materials contained in the gate stack structure can refer to the foregoing, and are not described herein again.

Compared with the prior art, the manufacturing method of the semiconductor device provided by the embodiment of the invention has the same beneficial effects as those of the semiconductor device provided by the embodiment, and the details are not repeated herein.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate, a first electrode and a second electrode,

a gate all around transistor formed on the substrate;

the isolation layer is at least filled between the substrate and the gate stack structure of the gate-all-around transistor and is at least positioned below the channel of the gate-all-around transistor; the area of the isolation layer covering the substrate is smaller than or equal to the area of the gate stack structure covering the substrate.

2. The semiconductor device according to claim 1, wherein the material contained in the spacer layer is a dielectric material, and the dielectric material includes silicon oxide, silicon nitride, and silicon oxycarbide; and/or the presence of a gas in the gas,

the thickness of the isolating layer is 3 nm-50 nm; and/or the presence of a gas in the gas,

at least part of the isolation layer is positioned between the source region and the drain region of the gate-all-around transistor; or the isolation layer is positioned below a region between the source region and the drain region of the gate-all-around transistor.

3. The semiconductor device according to claim 1, wherein in a case where an area of the isolation layer covering the substrate is equal to an area of the gate stack structure covering the substrate, the isolation layer has a middle region and an outer region in a length extending direction of the isolation layer; the middle area is an area of the isolation layer below the channel; the outer regions are positioned on both sides of the middle region; the top height of the middle region is greater than or equal to the top height of the outer region.

4. A semiconductor device according to any one of claims 1 to 3, wherein the channel comprises at least one layer of nanosheets spaced apart along the thickness of the substrate; the material contained in the at least one layer of nano-sheets is Si_1- _xGe_xWherein x is more than or equal to 0 and less than or equal to 1.

5. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a gate-all-around transistor and an isolation layer on the substrate; the isolation layer is at least filled between the substrate and the gate stack structure of the gate-all-around transistor, and the isolation layer is at least positioned below the channel of the gate-all-around transistor; the area of the substrate covered by the isolation layer is smaller than or equal to the area of the substrate covered by the gate stack structure.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the forming of the isolation layer over the substrate comprises:

forming a pre-formed structure and a stacked structure on the substrate; the stacked structure comprises at least one layer of stacked layers, and a source region and a drain region which are arranged on the gate-all-around transistor; the at least one laminated layer is positioned on the preformed structure; the at least one laminated layer is positioned between the source region and the drain region and is in contact with the source region and the drain region; each of the laminated layers comprises a sacrificial layer and a channel layer positioned on the sacrificial layer;

removing a part of the preformed structure below the at least one laminated layer to form a hollowed-out area below the at least one laminated layer;

and forming the isolation layer at least in the hollow area.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the source region and the drain region are both located on the substrate; the preformed structure is positioned between the source region and the drain region and is in contact with the source region and the drain region; or the like, or, alternatively,

the source region and the drain region are both positioned on the preformed structure, and the bottom surface of the stacked structure is in contact with the top surface of the preformed structure; or the like, or, alternatively,

the source region and the drain region are both located above the pre-formed structure.

8. The method according to claim 6, wherein the forming the isolation layer at least in the hollow region comprises:

forming an isolation material layer at least in the hollow area and part of the grid forming area; the grid electrode forming region is a region for forming the grid stack structure;

and carrying out back etching treatment on the isolation material layer by adopting a wet etching process or a dry etching process, so that the rest isolation material layer forms the isolation layer.

9. The method of manufacturing the semiconductor device according to claim 6, wherein the forming a pre-formed structure and a stacked structure on the substrate comprises:

sequentially forming a preformed layer and at least one laminated material layer on the substrate along the thickness direction of the substrate;

etching to a part of the substrate from the top of the at least one laminated material layer to form a fin-shaped structure extending along a first direction;

forming shallow trench isolation on the exposed part of the substrate outside the fin-shaped structure; the part of the fin-shaped structure exposed outside the shallow trench isolation is a fin part; the fin part is provided with a source region forming region for forming at least part of the source region, a drain region forming region for forming at least part of the drain region and a transition region for forming the channel and the isolation layer; the part of the at least one laminated material layer in the transition area is the at least one laminated layer;

forming a sacrificial gate and a side wall extending along a second direction on the periphery of the transition region; the side walls are at least positioned at two sides of the sacrificial gate along the width direction; the second direction is different from the first direction;

processing at least the source region forming region to form the source region, and processing at least the drain region forming region to form the drain region, so as to obtain the stacked structure; and allowing the remaining portion of the pre-formed layer to form the pre-formed structure;

after the pre-forming structure and the stacking structure are formed on the substrate, and before the removing of the part of the pre-forming structure below the at least one laminated layer, the method for manufacturing the semiconductor device further comprises:

and removing the sacrificial gate.

10. The method according to claim 6, wherein in a case where the sacrificial layer and the preformed structure contain different materials, forming the gate-all-around transistor on the substrate after forming the isolation layer on the substrate comprises:

removing the sacrificial layer so that a channel layer included in the at least one stack layer forms the channel;

and forming the gate stack structure around the periphery of the channel to obtain the gate-all-around transistor.

11. The method for manufacturing a semiconductor device according to claim 6, wherein in the case where the sacrificial layer and the pre-formed structure contain the same material,

after the pre-forming structure and the stacking structure are formed on the substrate, and before the isolation layer is formed at least in the hollow area, the manufacturing method of the semiconductor device comprises the following steps: removing the sacrificial layer and a part of the preformed structure below the at least one laminated layer to form a hollow-out area below the at least one laminated layer and enable a channel layer included in the at least one laminated layer to form the channel;

after forming the isolation layer on the substrate, forming the gate-all-around transistor on the substrate, including: and forming the gate stack structure around the periphery of the channel to obtain the gate-all-around transistor.

12. The method for manufacturing a semiconductor device according to any one of claims 6 to 11, wherein the channel layer contains Si as a material_1-xGe_x(ii) a The sacrificial layer contains Si_1-yGe_y(ii) a The preformed structure contains Si as the material_1-zGe_z(ii) a Wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 1, x-y is more than or equal to 0.2, and x-z is more than or equal to 0.25.