CN114706116B - FPGA-based detector reading electronics system - Google Patents
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- CN114706116B CN114706116B CN202210631795.0A CN202210631795A CN114706116B CN 114706116 B CN114706116 B CN 114706116B CN 202210631795 A CN202210631795 A CN 202210631795A CN 114706116 B CN114706116 B CN 114706116B
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Abstract
The invention discloses a detector reading electronic system based on an FPGA (field programmable gate array), which comprises a plurality of QTC (quantitative trait locus) circuits and a plurality of digital parts, wherein each QTC circuit comprises an operational amplifier and an integrating capacitor C f A diode and a resistor R; the digital part comprises a voltage comparator and an FPGA, and the negative input end of the operational amplifier is respectively connected with a resistor R, a diode and an integrating capacitor C f And an external detector, the resistor R is connected with a power supply V dis Said diode and an integrating capacitor C f Connected in parallel and connected to the output terminal of the operational amplifier, the positive terminal of the operational amplifier being connected to a power supply V + The output end of the voltage comparator is connected with the positive end of the voltage comparator, and the negative end of the voltage comparator is connected with a power supply V Th And the voltage comparator is integrated on the FPGA. The method has the advantages that the measuring circuit is directly connected with the output current pulse of the particle detector, and the direct QTC conversion of charge time is realized.
Description
Technical Field
The application belongs to the field of nuclear electronics, and particularly relates to a multichannel and high-density reading electronics system based on an FPGA.
Background
Currently, full waveform digitization is the most widely used signal readout for a variety of different particle detectors. In the technology, firstly, the input nuclear signal is integrated and formed, the weak signal is changed into an observable large-amplitude signal, then the rapid waveform sampling is carried out, and the sampled signal is sent to a programmable device for real-time processing. This technique offers great advantages when the number of channels is small. With the development of particle detectors, multi-channel particle detectors have been developed in order to achieve high-precision positioning performance. For a high density, multi-channel particle detector of hundreds of channels, full waveform digitization techniques will make the detector readout electronics quite bulky. Another solution is to use an ASIC chip design that encapsulates all complex functions in one chip. The ASIC chip has very powerful functions, has excellent qualities of multiple channels, low power, radiation resistance and the like, but the development cycle is very long, and a targeted and practical ASIC chip can be developed within 5 to 10 years, and the cost is very high, and specific research and development are required for each application scene.
Disclosure of Invention
Aiming at the defects in the signal reading scheme of the existing multi-channel particle detector, the invention provides a compact signal reading scheme of the particle detector, which has low noise and simultaneous measurement of charge and time. The technical proposal is that the method comprises the following steps,
a detector reading electronic system based on FPGA comprises multiple QTC circuits and multiple digital parts, wherein each QTC circuit comprises an operational amplifier and an integrating capacitor C f A diode and a resistor R; the digital part comprises a voltage comparator and an FPGA, and the negative input end of the operational amplifier is respectively connected with a resistor R, a diode and an integrating capacitor C f And an external detector, the resistor R is connected with a power supply V dis Said diode and an integrating capacitor C f Connected in parallel and connected to the output terminal of the operational amplifier, the positive terminal of the operational amplifier is connected to the power supply V + The output end of the voltage comparator is connected with the positive end of the voltage comparator, and the negative end of the voltage comparator is connected with a power supply V Th And the voltage comparator is integrated on the FPGA.
Preferably, a time-to-digital converter TDC is integrated on the FPGA, and the digital pulse output by the voltage comparator is digitized by using the time-to-digital converter TDC.
Preferably, SSTL receiver is used as a voltage comparator inside FPGA, and a threshold power supply V is used Th V connected to corresponding Bank REF Pins, in this Bank, all I/O pins share a V Th 。
Preferably, the negative current pulse measurement process is:
anode connection amplifier of diodeThe negative input end of the amplifier is connected with the negative electrode of the amplifier; in the quiescent state, i.e. without input current pulses, i D (t)=I c (t)=0，I diode (t)=I 0 =V dis /R, diode conduction, i D (t) is the output current of the detector, i c (t) is via an integrating capacitor C f Upper current, I diode (t) is the current through the diode, I 0 Is a current passing through the resistor R, at which time the power supply V + Is equal to the turn-on voltage V of the diode on The output baseline of the operational amplifier is V + Minus V on Equal to 0V, the anode voltage of the diode is V on And the cathode voltage is 0V.
Preferably, the negative current pulse measurement process is:
when a current pulse is injected into the QTC circuit, i is in a very short time initially because the current pulse is in the rising part D (t)<I 0 Power supply V dis And resistor R provide a discharge path; when inputting current i D (t) is greater than discharge current I 0 When is i D (t)>I 0 The current of the detector is passed through a power supply V dis And resistor R, and on the other hand, starts in integrating capacitor C f After that, the output voltage of the operational amplifier is greater than 0V, resulting in the voltage difference between the anode and the cathode of the diode being less than V on The diode being off, i diode (t) ≈ 0, the output voltage of the operational amplifier increases until the output current i of the detector D (t) is once again less than the discharge current I 0 After that, the current outputted by the detector will pass through the power supply V dis And a resistor R, no extra charge will be present in the integrating capacitor C f While integrating, integrating the capacitance C f On the already stored charge also starts from V dis And the resistor R discharges until the charges integrated on the capacitor are completely discharged, the baseline voltage output by the operational amplifier becomes 0V again, the diode is conducted, and the whole QTC circuit returns to the condition of static working again.
Preferably, the negative current pulse measurement process is: when the operational amplifier starts to have the output voltage, the diode is cut off, and the current i passing through the diode path diode (t) ≈ 0, and the following equation is obtained by the conservation of electric charge and the sum of the currents at the negative input terminal of the operational amplifier being 0:
wherein i c (t) is through an integrating capacitor C f At an upper current, i.e. i c (t)=C f (dU (t)/dt), assuming an integrating capacitance C f The time when the integrated charge starts to be 0 is the time when the output voltage of the operational amplifier starts to increase from 0V, the pulse width of the output signal of the operational amplifier is T, and at the time T, the feedback capacitor C of the operational amplifier f The accumulated charges are completely discharged, so the output voltage of the operational amplifier returns to 0V again, and in the time period of 0-T, the output voltage of the operational amplifier starts from 0V and increases to the maximum value and then returns to 0V again, and the integral of the above expression is obtained:
Preferably, the positive current pulse measurement process is:
1) the cathode of the diode is connected with the negative input end of the operational amplifier, and the anode of the diode is connected with the output end of the operational amplifier;
2) power supply V + 1.8V, and the output voltage of the operational amplifier is V under the static condition of the circuit, namely when no input current pulse exists + And V on Summing; v connected to a resistor R dis 0V, at which time the discharge current I 0 In the reverse direction, the current value is V + R; in the quiescent state, the voltage of the anode of the diode is V + And V on Sum, voltage of diode cathode is V + At the moment, the diode is normally conducted; when there is a positive current pulse input to the circuit, at i D (t)>I 0 After that time, the user can use the device,
at integrating capacitor C f The upper integration makes the output end of the operational amplifier generate a negative pulse to cause the diode to be cut off until the integrating capacitor C f The situation that the circuit returns to the static state again only when the charges integrated above are all discharged by the resistor R;
3) the QTC circuit obtains a voltage signal with the charge proportional to the pulse width of the signal, and the voltage comparator compares the QTC signal with a specified threshold value V Th The voltage comparator outputs a digital signal having a width proportional to the total charge of the current pulse, the leading edge of the digital signal representing the arrival time of the signal, thereby enabling simultaneous charge and time measurement.
Advantageous effects
1. The scheme is suitable for the design of a miniaturized, low-noise and multi-channel nuclear electronic system, and has the capability of simultaneously measuring the charge and the time.
2. Discrete elements such as an amplifier, an integrating capacitor and a resistor are adopted to realize the conversion of single-path charges to signal width, and meanwhile, the advantages of multiple resources, multiple I/O (input/output) and low power consumption of an FPGA (field programmable gate array) are utilized to realize a multi-channel, high-density and miniaturized particle detector read-out electronic system.
Drawings
Fig. 1 is a schematic diagram of a compact FPGA-based charge readout.
Fig. 2 is a diagram of a direct charge-time converter QTC schematic for negative current pulse measurement.
Fig. 3 is a diagram of a direct charge-time converter QTC schematic for positive current pulse measurement.
Fig. 4 is a miniaturized nuclear electronics system based on an FPGA.
Detailed Description
The following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application.
The technical scheme of the invention is realized by a direct charge-time conversion QTC technology:
a detector reading electronic system based on FPGA comprises multiple QTC circuits and multiple digital parts, wherein each QTC circuit comprises an operational amplifier and an integrating capacitor C f A diode and a resistor R; the digital part comprises a voltage comparator and an FPGA, and the negative input end of the operational amplifier is respectively connected with a resistor R, a diode and an integrating capacitor C f And an external detector, the resistor R is connected with a power supply V dis Said diode and an integrating capacitor C f Connected in parallel and connected to the output terminal of the operational amplifier, the positive terminal of the operational amplifier is connected to the power supply V + The output end of the voltage comparator is connected with the positive end of the voltage comparator, and the negative end of the voltage comparator is connected with a power supply V Th And the voltage comparator is integrated on the FPGA. And a time-to-digital converter (TDC) is integrated on the FPGA, and the digital pulse output by the voltage comparator is digitized by using the TDC. An SSTL receiver is adopted as a voltage comparator in the FPGA, and a threshold power supply V Th V connected to corresponding Bank REF Pins, in this Bank, all I/O pins share a V Th 。
The operational amplifier is used for amplifying weak current pulse signals from the particle detector and passes through an integrating capacitor C in a feedback loop of the operational amplifier f Integrating the weak signal, wherein the voltage amplitude after integration can reach hundreds of millivolts mV or a plurality of volts V;
the integrating capacitor C f The operational amplifier and the charge storage are formed to integrate and store the total charge contained in the input weak current pulse;
the diode provides a direct current loop when the circuit is in a static state, namely under the condition of no input current pulse, a constant voltage drop is generated between the negative input end and the output end of the operational amplifier due to the clamping action of the diode, namely the conduction voltage drop of the diode, under the condition of input current pulse, the voltage of the negative input end of the operational amplifier is unchanged due to the 'virtual short' action of the operational amplifier, and the current pulse is at C f After the upper integration, the voltage output by the operational amplifier is increased or decreased (according to the conditions of the positive current pulse and the negative current pulse), so that the voltage difference between the two ends of the diode is smaller than the conducting voltage, and then the diode is cut off, and all charges are discharged from the resistor R;
the resistor R (for discharging, also called discharge resistor) is used to continuously form the integrating capacitor C f A discharge loop is provided.
The power supply V + Connected to the positive side of the operational amplifier, the voltage value of which is equal to the conduction voltage drop V of the diode in the case of a negative current pulse measurement on ，V + The output of the amplifier is clamped at 0V by a diode, and in the case of a positive current pulse measurement, this voltage value is equal to 1.8V, where V is + Clamping the output base line of the operational amplifier at (V) through the clamping action of a diode + +V on Is the sum of two voltages);
the power supply V dis A constant discharge path is provided together with the resistor R;
the power supply V Th For providing the threshold required for signal comparison, V in the case of a negative current pulse input Th Slightly larger than the output baseline of the operational amplifier, in case of a positive current pulse input, V Th Slightly smaller than the output baseline of the amplifier;
the functions realized by the FPGA inside the FPGA comprise: the functions of a voltage comparator are realized by using an LVDS receiver or a voltage reference type receiver (SSTL and HSTL receivers), the functions of pulse width measurement and leading edge information extraction are realized by using a time digital converter TDC, the functions of data caching and transmission are realized by using an internal FIFO, and the functions of a high-speed data transmission engine are completed.
The invention comprises two parts: an analog part and a digital part.
The analog part comprises an operational amplifier and an integrating capacitor C f Diode, resistor R and power supply V + Power supply V dis These elements constitute a charge-time converter QTC.
The digital part comprises a power supply V Th And the FPGA completes the pulse width and time extraction of the QTC output voltage signal. If a voltage reference type receiver is adopted as a voltage comparator in the FPGA, the threshold value V Th Bank fixed V connected to FPGA REF At this time, any one of the I/O pins in the Bank can be used as a positive input terminal of a voltage comparator, and thus, one path of charge and time measurement can be realized inside the FPGA. Thus, for an FPGA with hundreds of I/O pins, a high density, miniaturized nuclear electronics system of hundreds of channels is easily achieved.
With reference to fig. 2, the charge measurement principle is first expressed as follows:
taking the measurement of negative current pulse as an example, at this time, the anode of the diode is connected with the negative input end of the amplifier, and the cathode is connected with the output end of the amplifier; in the quiescent case, i.e. without input current pulses, i D (t)=I c (t)=0，I diode (t)=I 0 =V dis R, the diode is on, at this time, the power supply V + Is the conduction voltage V of the diode on The output baseline of the amplifier is V + -V on =0V (i.e. the difference between the two power supplies is 0V), it should be noted that the diode anode voltage is V at this time on The cathode voltage is 0V; when a current pulse is injected into the QTC circuit, i is in a very short time since the current pulse is in the rising part D (t)<I 0 ，V dis And resistor R provide a discharge path; when the input current i of the detector D (t) is greater than discharge current I 0 When (I) 0 Is a current through resistor R), i.e. i D (t)>I 0 Current of the detector, on the one hand, through V dis And the branch of the resistor R discharges, and on the other hand starts at the integrating capacitor C f After that, the output voltage of the amplifier is greater than 0V, resulting in the voltage difference between the anode and cathode of the diode being less than V on The diode being off, i diode (t) ≈ 0, after which the output voltage of the amplifier increases until the output current i of the detector D (t) is once again less than the discharge current I 0 After that, the current outputted by the detector will pass through V dis And branch of R, no extra charge is in capacitor C f While integrating, and a capacitor C f On the already stored charge also starts from V dis And the branch of the R is discharged until the charges integrated on the capacitor are completely discharged, the baseline voltage output by the amplifier becomes 0V again, the diode is conducted, and the whole circuit returns to the condition of static operation again.
In summary, we can formulate the operating principle of the circuit, since we are mainly concerned with the period of time during which the amplifier starts to have an output voltage, during which the diode is turned off and the current i through the diode path is diode (t) ≈ 0, and by conservation of charge, the sum of currents flowing into the node a (the junction of the resistor R and the detector is the node a, i.e., the sum of currents at the negative input terminal of the operational amplifier is 0) is 0, and the following equation can be obtained:
wherein i c (t) is via an integrating capacitor C f Upper current, i c (t)=C f (dU (t)/dt), assuming an integrating capacitance C f The time when the integrated charge starts to be present is time 0, at which time the amplifier output voltage starts to increase from 0V, and the pulse width of the amplifier output signal is T, as shown in fig. 2, at time T, the amplifier feedback capacitor C f The accumulated charge has all drained away and so the amplifier output voltage returns to 0V again. In the period of 0-TIn the interim, that is, after the output voltage of the amplifier increases from 0V to the maximum value, the output voltage returns to 0V again, and the above equation is integrated to obtain:
and then
The area of the current pulse is approximately equal to the total charge Q (since i is before time 0 D (t)<I 0 Before the output voltage of the amplifier is greater than 0, a small amount of charge passes through V dis And discharge of resistor R, but since the current pulse leading edge is fast, this part of the charge is lost, negligible), so we get Q = I) 0 Xt, the conversion of charge to pulse width is achieved.
The positive charge is similar in principle to the negative charge measurement, and is briefly described below with the aid of fig. 3:
1) the cathode of the diode is connected with the negative input end of the amplifier, and the anode of the diode is connected with the output end of the amplifier; 2) voltage V + Becomes 1.8V, and in the case of a circuit quiescent state, i.e., when no current pulse is input, the output voltage of the amplifier becomes (V) + +V on The sum of the two power supplies); 3) v connected to a resistor R dis Becomes 0V at which time the discharge current I 0 In the reverse direction, the current value is V + and/R. In the quiescent state, the voltage of the anode of the diode is (V) + +V on Is the sum of two power supplies), the voltage of the cathode of the diode is V + At this time, the diode is normally turned on. When there is a positive current pulse input to the circuit, at i D (t)>I 0 After that time, the user can use the device,
at integrating capacitor C f The upper integration makes the output end of the amplifier generate a negative pulse, which causes the diode to be cut off until the integrating capacitor C f The charge integrated above is fully discharged by the resistor R, and the circuit will return to the condition of the quiescent state again.
The QTC circuit obtains a voltage signal having a charge proportional to the pulse width of the signal. The digital part is mainly composed of an FPGA, as shown in FIG. 1. Within the FPGA, the QTC signal is first compared with a specified threshold V by an equivalent voltage comparator (LVDS receiver or voltage reference type receiver) Th The comparison is made such that the digital signal width output by the voltage comparator, i.e. proportional to the total charge of the current pulse, is proportional to the time of arrival of the signal, thereby enabling simultaneous charge and time measurement.
Inside the FPGA, the digital pulses output by the voltage comparators are digitized using a time-to-digital converter TDC. In order to realize high-density electronics, the utilization rate of FPGA resources is balanced, and the high-density electronics is realized by adopting a coarse time counter; to achieve high accuracy charge and time measurements, a TDC based on time interpolation is used to measure the digital signal pulse width and leading edge.
FIG. 4 provides an example of a design that employs an SSTL receiver as a voltage comparator inside an FPGA, with a threshold V Th V connected to corresponding Bank REF Pins, in this Bank, all I/O pins share a V Th . Each QTC circuit consists of an amplifier and a capacitor C f Resistor R, diode and power supply V + Power supply V dis The structure adopts a commercial chip of a four-way amplifier, and a 4-way QTC circuit can be limited to 10 multiplied by 10 mm 2 Therefore, 100 QTC circuits can be limited to 50 mm by 50 mm 2 Comparable to the size of an ASIC circuit.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. A detector reading electronic system based on FPGA is characterized by comprising a plurality of QTC circuits and a plurality of digital parts, wherein each QTC circuit comprises an operational amplifier and an integrating capacitor C f A diode and a resistor R; number ofThe word part comprises a voltage comparator and an FPGA, and the negative input end of the operational amplifier is respectively connected with a resistor R, a diode and an integrating capacitor C f And an external detector, the resistor R is connected with a power supply V dis Said diode and an integrating capacitor C f Connected in parallel and connected to the output terminal of the operational amplifier, the positive terminal of the operational amplifier being connected to a power supply V + The output end of the voltage comparator is connected with the positive end of the voltage comparator, and the negative end of the voltage comparator is connected with a power supply V Th The voltage comparator is integrated on the FPGA;
when measuring the negative current pulse, the anode of the diode is connected with the negative input end of the operational amplifier, and the cathode of the diode is connected with the output end of the operational amplifier;
when measuring the positive current pulse, the cathode of the diode is connected with the negative input end of the operational amplifier, and the anode is connected with the output end of the operational amplifier.
2. An FPGA-based detector readout electronics system according to claim 1 wherein a time to digital converter, TDC, is integrated on said FPGA, and wherein the digital pulses output by the voltage comparators are digitized using the time to digital converter, TDC.
3. FPGA-based detector readout electronics system according to claim 2, characterized in that the FPGA uses an SSTL receiver as voltage comparator inside, a threshold supply V Th V connected to corresponding Bank REF Pins, in this Bank, all I/O pins share a V Th 。
4. An FPGA-based detector readout electronics system according to claim 3, wherein the negative current pulse measurement process comprises:
in the quiescent case, i.e. without input current pulses, i D (t)=I c (t)=0，I diode (t)=I 0 =V dis /R, diode on, i D (t) is the output current of the detector, i c (t) is via an integrating capacitor C f Upper current, I diode (t) is the current through the diode, I 0 Is a current passing through the resistor R, at which time the power supply V + Is equal to the turn-on voltage V of the diode on The output baseline of the operational amplifier is V + Minus V on Equal to 0V, the anode voltage of the diode is V on The cathode voltage was 0V.
5. An FPGA-based detector readout electronics system according to claim 4, wherein the negative current pulse measurement process comprises:
when a current pulse is injected into the QTC circuit, i is initially in a very short time because the current pulse is in the rising portion D (t)<I 0 Power supply V dis And resistor R provide a discharge path; when inputting current i D (t) is greater than discharge current I 0 When is i D (t)>I 0 The current of the detector is passed through a power supply V dis And the resistor R discharges, and on the other hand starts at the integrating capacitor C f After that, the output voltage of the operational amplifier is greater than 0V, resulting in the voltage difference between the anode and the cathode of the diode being less than V on The diode being off, i diode (t) ≈ 0, the output voltage of the operational amplifier increases until the output current i of the detector D (t) is once again less than the discharge current I 0 After that, the current outputted by the detector will pass through the power supply V dis And a resistor R, no extra charge will be left in the integrating capacitor C f While integrating, integrating the capacitance C f On the stored charge also starts from V dis And the resistor R discharges until the charges integrated on the capacitor are completely discharged, the baseline voltage output by the operational amplifier becomes 0V again, the diode is conducted, and the whole QTC circuit returns to the condition of static working again.
6. The FPGA-based detector readout electronics system of claim 4, wherein the negative current pulse measurement process is: fortuneWhen the operational amplifier starts to have the output voltage, the diode is cut off, and the current i passing through the diode path diode (t) ≈ 0, and the following equation is obtained by the conservation of electric charge and the sum of the currents at the negative input terminal of the operational amplifier being 0:
wherein i c (t) is via an integrating capacitor C f Upper current, i c (t)=C f (dU (t)/dt), assuming an integrating capacitance C f The time when the integrated charge starts to be 0 is the time when the output voltage of the operational amplifier starts to increase from 0V, the pulse width of the output signal of the operational amplifier is T, and at the time T, the feedback capacitor C of the operational amplifier f The accumulated charges are all discharged, so the output voltage of the operational amplifier returns to 0V again, and in the time period of 0-T, the output voltage of the operational amplifier starts to increase from 0V to the minimum value and then returns to 0V again, and the integral of the above equation is obtained:
7. An FPGA-based detector readout electronics system according to claim 3 wherein the positive current pulse measurement process is:
1) power supply V + 1.8V, and the output voltage of the operational amplifier is V under the static condition of the circuit, namely when no input current pulse exists + And V on Summing; v connected to a resistor R dis 0V, at which time the discharge current I 0 In the reverse direction, the current value is V + R; in a static state, the voltage of the anode of the diode is V + And V on Sum, the voltage of the cathode of the diode is V + At the moment, the diode is normally conducted; when there is a positive current pulse input to the circuit, at i D (t)>I 0 After that time, the user can use the device,
at integrating capacitor C f The upper integration makes the output end of the operational amplifier generate a negative pulse, which causes the diode to be cut off until the integrating capacitor C f The situation that the circuit returns to the static state again only when the charges integrated above are all discharged by the resistor R;
2) the QTC circuit obtains a voltage signal with the charge proportional to the pulse width of the signal, and the voltage comparator compares the QTC signal with a specified threshold value V Th The voltage comparator outputs a digital signal having a width proportional to the total charge of the current pulse, the leading edge of the digital signal representing the arrival time of the signal, thereby enabling simultaneous charge and time measurement.
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