CN114696969A - Serial UART (universal asynchronous receiver/transmitter) coding and decoding structure and method based on interleaving XOR (exclusive OR) algorithm - Google Patents
Serial UART (universal asynchronous receiver/transmitter) coding and decoding structure and method based on interleaving XOR (exclusive OR) algorithm Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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Abstract
The invention relates to a serial UART coding and decoding structure and a method based on an interleaving exclusive-or algorithm.A hardware structure uses two channels for data transmission, the two channels are a first channel and a redundant channel respectively, and each channel consists of a signal transmitter and a signal receiver; the first channel transmits a signal to be transmitted after being coded by a serial UART protocol, and the redundant channel transmits redundant data after being coded by the serial UART protocol; the decoding module decodes the dual-channel data received by the receiving end through a serial UART protocol, when the interference of a transmission channel is small, the first channel data can be directly used for reducing power consumption, when the interference of the transmission channel is large, the algorithm processing is carried out on the received data through a sampling game algorithm to deal with the channel data transmission in a high-interference environment, and when the received data is abnormal, the error correction of the abnormal data is realized through an interleaving XOR algorithm which is the same as that of the encoding module in the data recovery module.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a serial UART coding and decoding method based on an interleaving exclusive-or algorithm.
Background
The serial UART refers to a Universal Asynchronous Receiver/Transmitter (generally referred to as UART), which is an Asynchronous serial transceiver protocol and is composed of a signal Transmitter and a signal Receiver, and data transmission and reception can be performed by connecting a transmitting data terminal of the signal Transmitter and a receiving data terminal of the signal Receiver, so that data interaction can be completed only by two transmission lines.
The serial UART communication is widely applied in the fields of electric power and automatic control, when the serial UART transceiving is applied to an FPGA (Field Programmable Gate Array), the transmission speed is generally high, often greater than 4Mbps, since the sending data end and the receiving data end of the serial transceiving are single-ended transmission, when a transmission channel is affected by factors such as electromagnetic interference or noise, a signal transmitted by the transmission channel may cause data sampling errors due to the generation of burrs, thereby causing received data anomalies and error codes to easily occur. Usually, serial transceiving sets a parity bit (the last bit of a data bit) to check received data to determine whether a transmitted signal is correct, but the parity bit can only determine the correctness of the transmitted signal, but cannot help a user to correct the abnormality, which is not allowed in some occasions with high requirements on data reliability.
Disclosure of Invention
In order to solve the technical problems, the invention provides a high-reliability serial UART coding and decoding method based on a Field Programmable Gate Array (FPGA), which is mainly applied to channel data transmission in a high-interference environment and realizes error correction when the channel data transmission is abnormal; the method comprises the steps that a link signal to be transmitted at a sending end is processed through an interleaving XOR algorithm and then is recoded by using a serial UART protocol, the link signal is used as redundant data and sent through a redundant channel sending end, the channel data transmission under a high-interference environment is responded through a sampling game algorithm at a receiving end, and when the environment interference is large, error correction is carried out on channel transmission abnormal signals in the serial UART communication process through the same interleaving XOR algorithm as that of the sending end.
The serial UART coding and decoding structure based on the interleaving XOR algorithm comprises a first FPGA and a second FPGA, wherein the first FPGA comprises a coding module, a first channel signal transmitter and a redundant channel signal transmitter, and the second FPGA comprises a decoding module, a first channel signal receiver and a redundant channel signal receiver;
the encoding module comprises a first UART encoding module and an algorithm encoding module, the first UART encoding module encodes a link signal to be transmitted, and transmits the encoded link signal to be transmitted to a first channel signal receiver through a first channel signal transmitter; the algorithm coding module processes a link signal to be transmitted to obtain a group of redundant data, codes the redundant data, and sends the coded redundant data to a redundant channel signal receiver through a redundant channel signal transmitter;
the decoding module comprises a first UART decoding module, a second UART decoding module, a first sampling game algorithm module, a second sampling game algorithm module and a data recovery module, wherein the first UART decoding module and the second UART decoding module respectively decode received encoded link signals to be transmitted and encoded redundant data, then process the decoded data through the first sampling game algorithm module and the second sampling game algorithm module, and correct errors of the received data through the data recovery module when the received data are abnormal.
Further, the algorithm coding module comprises an interleaving exclusive-or algorithm coding module and a second UART coding module, the interleaving exclusive-or algorithm coding module performs algorithm processing on the link signal to be transmitted, and then the second UART coding module is used for coding the processed data.
The serial UART coding and decoding method based on the interleaving XOR algorithm adopts the serial UART coding and decoding structure based on the interleaving XOR algorithm to carry out coding and decoding, and comprises the following steps:
step 3, the algorithm coding module performs interleaving XOR algorithm operation on the link signals to be transmitted simultaneously, low-order to high-order of the signals to be transmitted are defined as (p (0), p (1), p (2) · and p (n-1)), an information sequence is formed, and the information sequence is recoded through the interleaving XOR algorithm to obtain redundant data;
step 4, encoding the redundant data through a second UART encoding module, and transmitting the encoded redundant data through a data transmitting end of a redundant channel signal transmitter;
step 5, receiving data sent by a first channel signal transmitter through a first channel signal receiver; receiving data transmitted by a redundant channel signal transmitter through a redundant channel signal receiver;
and 6, decoding the received encoded link signal to be transmitted and the encoded redundant data by the first UART decoding module and the second UART decoding module respectively, processing the decoded data by the first sampling game algorithm module and the second sampling game algorithm module simultaneously, and correcting errors of the received data by the data recovery module when the received data is abnormal.
Further, in step 2, the link signal to be transmitted is encoded by the UART protocol, and then the data is transmitted by the data transmitting end of the first channel signal transmitter, where the encoding protocol does not use parity bits to detect errors in the transmission signal.
Further, in step 3, the algorithm encoding module discretizes successive bits of the link signal to be transmitted by an interleaving xor algorithm, and then re-encodes the discretized data, where the interleaving xor algorithm formula for re-encoding the information sequence is specifically:
when in use
Then, a polynomial is defined
When in use
Then, a polynomial is defined
，
X: current transmission bit, r: coefficient of dispersion, n: the number of signal bits is transmitted.
Further, after the first channel signal receiver receives the link signal to be transmitted, sampling each bit of the decoded link signal to be transmitted through the first sampling game algorithm module, wherein the sampling times are CYCLE = CLK _ FRE/BAUD _ RATE, CLK _ FRE is the system clock frequency of the decoding module, and BAUD _ RATE is the serial transmission BAUD RATE; setting a high level counter and a low level counter in the first sampling game algorithm module, wherein when the sampling signal is at a high level, the high level counter is increased by one, and when the sampling signal is at a low level, the low level counter is increased by one; after each pair of one-bit sampling CYCLE times, the counting values of the high-level counter and the low-level counter are played, and the high level and the low level of the bit are selected according to the principle that a small number of bits obey most in a game algorithm; after bit receiving is finished, register zero clearing operation is carried out on the two counters, and game is continued on the next bit; when the count values of the high level counter and the low level counter become equal, the position is set as a warning bit.
Further, after the redundant channel signal receiver receives the redundant data, each bit of the redundant data is sampled through a second sampling game algorithm module, the sampling times are CYCLE = CLK _ FRE/BAUD _ RATE, CLK _ FRE is the system clock frequency of the decoding module, and BAUD _ RATE is the serial transmission BAUD RATE; a high level counter and a low level counter are arranged in the second sampling game algorithm module, when the sampling signal is at a high level, the high level counter is increased by one, and when the sampling signal is at a low level, the low level counter is increased by one; after each pair of the first digit samples CYCLE times, the counting values of the high level counter and the low level counter are played, the high level and the low level of the digit are selected according to the principle that a small number of digits obey most in a game algorithm, after the digit is received, the two counters are subjected to register zero clearing operation, and the next digit is played continuously; when the count values of the high level counter and the low level counter become equal, the position is set as a warning bit.
Furthermore, when the data of the redundant channel is abnormal, the data is decoded by using the same interleaving XOR algorithm as that used in encoding, so that the effect of recovering the abnormality is achieved; when more than two coefficients in the interleaving XOR algorithm are warning bits, only the warning bits are subjected to receiving operation without other operation, and data continues to be received until more than two coefficients in the algorithm are not warning bits; and recovering all the warning bits of the first channel received data and the redundant channel received data before the bit, recovering the warning bit of the bit through an algorithm, wherein the recovered data is a received correct value, replacing the warning bit data value of the current bit by using the correct value, and simultaneously continuing to perform algorithm operation by using the replaced correct value until all the warning bits before the bit are recovered to be correct values, thereby realizing the function of correcting errors when the serial reception is abnormal.
The invention has the beneficial effects that: in the prior art, because serial UART protocol communication is single-ended transmission, abnormal transmission data occurs at a high possibility during transmission in a high interference environment, and if an error checking code is added to the transmission data to judge whether the data transmission is abnormal or not, the transmission rate is reduced; therefore, the invention designs an implementation method of a dual-channel structure aiming at the situation, wherein a first channel transmits a link signal to be transmitted, a redundant channel transmits redundant data, the data transmitted by the first channel is encoded by a serial UART protocol and then transmitted, the data transmitted by the redundant channel is subjected to data processing by using an interleaving XOR algorithm to obtain a group of redundant data, and the redundant data is encoded by the serial UART protocol and then transmitted; under the environment with larger interference, the decoding module uses a sampling game algorithm to deal with the transmission abnormality under the high-interference environment, and the encoding module and the data recovery module use an interleaving exclusive OR algorithm to realize error checking and correction when the transmission abnormality occurs.
Drawings
In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
Fig. 1 is a schematic structural diagram of a serial encoding and decoding method based on an interleaving exclusive or algorithm according to an embodiment of the present invention;
FIG. 2 is a block diagram according to an embodiment of the present invention;
FIG. 3 is a flow chart of a transmission encoding method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an interleaved XOR algorithm encoding according to an embodiment of the present invention;
FIG. 5 is a flow chart of a receiving and decoding method according to an embodiment of the present invention;
fig. 6 is a flow diagram of a sample gaming method according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a schematic diagram of a serial UART codec structure based on an interleaving exclusive-or algorithm according to an embodiment of the present invention, where the serial UART codec structure includes a first FPGA and a second FPGA, the first FPGA includes a coding module, a first channel signal transmitter, and a redundant channel signal transmitter, and the second FPGA includes a decoding module, a first channel signal receiver, and a redundant channel signal receiver.
As shown in fig. 2, the encoding module includes a first UART encoding module and an algorithm encoding module, the first UART encoding module encodes a link signal to be transmitted, and transmits the encoded link signal to be transmitted to the first channel signal receiver through the first channel signal transmitter; the algorithm coding module comprises an interleaving XOR algorithm coding module and a second UART coding module, the interleaving XOR algorithm coding module performs algorithm processing on a link signal to be transmitted to obtain a group of redundant data, then the second UART coding module is used for coding the redundant data, and the coded redundant data is sent to a redundant channel signal receiver through a redundant channel signal transmitter;
the decoding module comprises a first UART decoding module, a second UART decoding module, a first sampling game algorithm module, a second sampling game algorithm module and a data recovery module, wherein the first UART decoding module and the second UART decoding module respectively decode received encoded link signals to be transmitted and encoded redundant data, then process the decoded data through the first sampling game algorithm module and the second sampling game algorithm module, and correct errors of the received data through the data recovery module when the received data are abnormal.
As shown in fig. 3, the serial UART encoding and decoding method based on the interleaving xor algorithm of the present invention firstly proposes an encoding operation performed by the interleaving xor algorithm, and the algorithm is suitable for a multi-bit serial transmission signal, and includes the following steps:
when in use
Then, a polynomial is defined
When in use
Then, a polynomial is defined
，
Step 3, the algorithm coding module performs interleaving exclusive-or algorithm operation on the link signals to be transmitted simultaneously, as shown in fig. 4, the low order to the high order of the signals to be transmitted are defined as (p (0), p (1), p (2) ·.. so, p (n-1)), so as to generate coefficients from low order terms to high order terms of an algorithm polynomial, and the sequence length n is the number of bits of the data to be transmitted; the polynomial of the algorithm is as
Then, a polynomial is defined
When is coming into contact with
Then, a polynomial is defined
The discretization degree of the signal can be adjusted according to the size of r, when r is the maximum value of the range, the discretization degree is the highest at the moment but the algorithm operation consumes the longest at the moment, when r is the minimum value of the range, the discretization degree is the lowest at the moment but the algorithm operation consumes the least at the moment, and in practical engineering application, the discretization variables of the algorithm need to be balanced. The data coded in the step is coded by a UART protocol, and the coded redundant data is transmitted by a data transmitting end of a redundant channel signal transmitter.
Step 4, encoding the redundant data through a second UART encoding module, and transmitting the encoded redundant data through a data transmitting end of a redundant channel signal transmitter;
step 5, receiving data sent by a first channel signal transmitter through a first channel signal receiver; receiving data transmitted by the redundant channel signal transmitter through the redundant channel signal receiver, as shown in fig. 5;
and 6, decoding the received encoded link signal to be transmitted and the encoded redundant data by the first UART decoding module and the second UART decoding module respectively, processing the decoded data by the first sampling game algorithm module and the second sampling game algorithm module simultaneously, and correcting errors of the received data by the data recovery module when the received data is abnormal.
As shown in fig. 6, when receiving the signal of the first channel, because of the serial UART protocol, the signal is received in a serial manner of receiving one bit, the receiving period of each bit is calculated by the BAUD RATE agreed by the serial protocol, the receiving period is 1/BAUD _ RATE (BAUD _ RATE is transmission BAUD RATE), the bit register needs to be sampled at each positive transition edge of the system clock in the receiving period, samples are required to be sampled for CYCLEs = CLK _ FRE/BAUD _ RATE (CLK _ FRE is system clock frequency of the decoding module), two counters are defined in the first sample game algorithm module, one is a high level counter, and the other is a low level counter, the counter is operated once when the receiving bit data is sampled for each time, the sampling signal value is logic high level when sampling, the sampling signal value of the high level counter is incremented by one, the sampling signal value is logic low level when sampling, at the moment, the value of the low level counter is increased by one, after the digit is sampled for CYCLE times, the counting values of the high level counter and the low level counter are subjected to game operation, and the high level value and the low level value of the digit are selected according to a few obedient majority principles in a game algorithm. The sampling game algorithm module of the first channel is executed in parallel with the receiving decoding module, so that the receiving decoding rate is not influenced, and when the sampling values of the high-low counter are equal due to the fact that a transmission channel has more burrs caused by electromagnetic interference or noise and the like, the position needs to be a warning bit, which means that the signal received by the bit is abnormal.
The receiving and decoding of the redundant channel also need to call a sampling game module, because the transmission environment of the redundant channel is the same as that of the first channel, the transmission channel may have more burrs due to electromagnetic interference or noise, etc., which results in the sample values of the high-low counters being equal, at this time, the position is also a warning bit, the receiving and decoding module of the redundant channel is executed in parallel with the decoding module of the first channel, and the decoding rate of the redundant channel is the same as that of the first channel, therefore, when the reception of a certain position of the first channel is completed, the position corresponding to the redundant channel is also completely received, when the signal received by the first channel passes through the sampling game algorithm module, which is set as the warning bit, at this time, the data recovery module tries to recover the warning bit abnormality by using the interleaving xor algorithm, when the data recovery module detects that the other two coefficients of the interleaving xor algorithm are normal values, and recovering the abnormal warning bit, when detecting that the abnormal values of the other two coefficients exist, not operating the warning bit, continuously judging the next group of data until detecting that the two coefficients in the interleaving exclusive-or algorithm are the normal values, recovering the warning bit by the data recovery module through the algorithm, replacing the abnormal values of the warning bit with the recovered normal values, simultaneously detecting forwards by using the normal values of the warning bit, and recovering all the abnormal values of the warning bit received before through the same algorithm operation.
Example 1:
and if the signal received by the first channel has no warning bit after passing through the sampling game algorithm, outputting the signal received by the first channel without performing other operations.
Example 2: (coefficient of dispersion R =1 time)
Assuming that the transmission channel signal is from high to low: 10010101
At this time, the link signal 10010101 to be transmitted is transmitted serially from the signal transmitter of the first channel by the UART protocol encoding.
At this time, the link signal to be transmitted is calculated by an interleaving exclusive-or algorithm, and since the discrete coefficient is 1, the obtained calculated data from the high bit to the low bit is: 01000001, the data is re-encoded by UART protocol and then transmitted through the signal transmitter of the redundant channel.
The first channel of the receiving end receives the serial data sent by the first channel of the sending end, the data is received by using a corresponding serial decoding mode, and meanwhile, the first sampling game algorithm module processes the received data in parallel, at the moment, the transmission channel generates burrs due to interference, and the received data is as follows: 10111001, compared with the link signal to be transmitted, the 3 rd, 5 th and 6 th bits of the received data are abnormal values, and the three bits are judged as warning bits through the sampling game algorithm module.
The redundant channel of the receiving end receives the serial data sent by the redundant channel of the sending end, and the received data is processed in parallel through the second sampling game algorithm module, and at the moment, the transmission channel is also burred due to interference, so that the received data is as follows: 00101101, compared with the link signal to be transmitted, the 2 nd, 3 rd and 6 th bits of the received data are alarm bits, and the three bits are judged as alarm bits by the sample game algorithm module.
When the 3 rd position of the first channel is the warning bit, the data recovery module is entered, the data recovery module detects that the 2 nd bit of the first channel is a normal value, the 2 nd bit of the redundant channel is an abnormal value, only one coefficient in the interleaving exclusive-or algorithm is a normal value, the forward detection is carried out, detecting the 2 nd bit of the redundant channel, detecting that the 1 st bit of the first channel and the 1 st bit of the redundant channel are both normal values, recovering the data of the 2 nd bit of the redundant channel by an interleaving exclusive-or algorithm, when the data recovery is finished, the recovered value replaces the 2 nd bit abnormal value received by the redundant channel, the 2 nd bit value of the redundant channel is recovered to be 1, the second bit of the redundant channel is recovered to be a normal value, the operation is continued after the bit is the normal value, thus restoring the 3 rd bit of the first channel to a normal value and so on to restore all subsequent received outliers.
Example 3: (coefficient of dispersion R =3 time)
Assuming that the transmission channel signal is from high to low: 10010101
At this time, the link signal 10010101 to be transmitted is transmitted serially from the signal transmitter of the first channel by the UART protocol encoding.
At this time, the link signal to be transmitted is calculated by an interleaving exclusive-or algorithm, and since the discrete coefficient is 3, the obtained calculated data from the high bit to the low bit is: 11000110, the data is sent by the signal transmitter of the redundant channel after being recoded by UART protocol.
The first channel of the receiving end receives the serial data sent by the first channel of the sending end, the data is received by using a corresponding serial decoding mode, and meanwhile, the sampling game algorithm module processes the received data in parallel, at the moment, the transmission channel generates burrs due to interference, and the received data is as follows: 00010101, compared with the link signal to be transmitted, the 1 st bit of the received data is an abnormal value, and the bit is judged as a warning bit through the sampling game algorithm module.
The redundant channel of the receiving end receives the serial data sent by the redundant channel of the sending end, and the received data is processed in parallel through the sampling game algorithm module, and at the moment, the transmission channel is also burred due to interference, so that the received data is as follows: 01000110, compared with the link signal to be transmitted, the 1 st bit of the received data is an alarm bit, and this bit is determined as an alarm bit by the sample game algorithm module.
When the 1 st position of the first channel is a warning bit, the data enters a data recovery module, at this time, because the discrete value of the interleaving algorithm is 3, at this time, the data recovery module can start data recovery only by detecting the 4 th bit of the first channel, so that the running time of the algorithm is increased, and the power consumption of the FPGA is increased. The data recovery module detects that the 4 th bit of the first channel is a normal value, but the 1 st bit of the redundant channel is an abnormal value, only one coefficient in the interleaving exclusive-or algorithm is a normal value, at this time, because the data received by the 1 st bit is data, the data cannot be detected forward, at this time, the data recovery module waits for the first channel to start detection when the 6 th bit of the first channel is received, at this time, the 6 th bit of the first channel and the 6 th bit of the redundant channel are both normal values, the data recovery module recovers the 1 st bit of the abnormal values of the first channel and the redundant channel through the interleaving exclusive-or algorithm, and so on, all the received abnormal values can be recovered.
The invention relates to a serial UART coding and decoding structure and a method based on an interleaving exclusive-OR algorithm, wherein a hardware structure uses two channels for data transmission, the two channels are a first channel and a redundant channel respectively, and each channel consists of a signal transmitter and a signal receiver; the first channel transmits a signal to be transmitted after being coded by a serial UART protocol, and the redundant channel transmits redundant data after being coded by the serial UART protocol; the decoding module decodes the dual-channel data received by the receiving end through a serial UART protocol, when the interference of a transmission channel is small, the first channel data can be directly used for reducing power consumption, when the interference of the transmission channel is large, the algorithm processing is carried out on the received data through a sampling game algorithm to deal with the channel data transmission in a high-interference environment, and when the received data is abnormal, the error correction of the abnormal data is realized through an interleaving XOR algorithm which is the same as that of the encoding module in the data recovery module.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations made by using the contents of the present specification and the drawings are within the protection scope of the present invention.
Claims (8)
1. The serial UART coding and decoding structure based on the interleaving XOR algorithm comprises a first FPGA and a second FPGA, and is characterized in that the first FPGA comprises a coding module, a first channel signal transmitter and a redundant channel signal transmitter, and the second FPGA comprises a decoding module, a first channel signal receiver and a redundant channel signal receiver;
the encoding module comprises a first UART encoding module and an algorithm encoding module, the first UART encoding module encodes a link signal to be transmitted, and transmits the encoded link signal to be transmitted to a first channel signal receiver through a first channel signal transmitter; the algorithm coding module processes a link signal to be transmitted to obtain a group of redundant data, codes the redundant data, and sends the coded redundant data to a redundant channel signal receiver through a redundant channel signal transmitter;
the decoding module comprises a first UART decoding module, a second UART decoding module, a first sampling game algorithm module, a second sampling game algorithm module and a data recovery module, wherein the first UART decoding module and the second UART decoding module respectively decode received encoded link signals to be transmitted and encoded redundant data, then process the decoded data through the first sampling game algorithm module and the second sampling game algorithm module, and correct errors of the received data through the data recovery module when the received data are abnormal.
2. The serial UART codec structure according to claim 1, wherein the algorithm encoding module includes an interleaving xor algorithm encoding module and a second UART encoding module, the interleaving xor algorithm encoding module performs algorithm processing on the link signal to be transmitted, and then encodes the processed data using the second UART encoding module.
3. The serial UART coding and decoding method based on the interleaving XOR algorithm is characterized in that the serial UART coding and decoding structure based on the interleaving XOR algorithm of any one of claims 1 or 2 is adopted for coding and decoding, and the method comprises the following steps:
step 1, determining a link signal to be transmitted;
step 2, the first UART coding module carries out coding processing on a link signal to be transmitted in a serial UART coding mode; transmitting the encoded link signal to be transmitted through a data transmitting end of a first channel signal transmitter;
step 3, the algorithm coding module performs interleaving XOR algorithm operation on the link signals to be transmitted simultaneously, low-order to high-order of the signals to be transmitted are defined as (p (0), p (1), p (2) · and p (n-1)), an information sequence is formed, and the information sequence is recoded through the interleaving XOR algorithm to obtain redundant data;
step 4, encoding the redundant data through a second UART encoding module, and transmitting the encoded redundant data through a data transmitting end of a redundant channel signal transmitter;
step 5, receiving data sent by a first channel signal transmitter through a first channel signal receiver; receiving data transmitted by a redundant channel signal transmitter through a redundant channel signal receiver;
and 6, decoding the received encoded link signal to be transmitted and the encoded redundant data by the first UART decoding module and the second UART decoding module respectively, processing the decoded data by the first sampling game algorithm module and the second sampling game algorithm module simultaneously, and correcting errors of the received data by the data recovery module when the received data is abnormal.
4. The serial UART coding and decoding method according to claim 3 and based on the interleaving exclusive-OR algorithm, wherein in step 2, the link signal to be transmitted is encoded by UART protocol, and then the data is transmitted through the data transmitting end of the first channel signal transmitter, and the encoding protocol does not use parity bits to detect errors of the transmission signal.
5. The serial UART coding and decoding method based on interleaving XOR algorithm as claimed in claim 3, characterized in that in step 3, the algorithm coding module discretizes the successive bits of the link signal to be transmitted by the interleaving XOR algorithm, and then re-encodes the discretized data, and the interleaving XOR algorithm formula for re-encoding the information sequence specifically is as follows:
when in use
Then, a polynomial is defined
When in use
Then, a polynomial is defined
，
X: current transmission bit, r: coefficient of dispersion, n: the number of signal bits is transmitted.
6. The serial UART coding and decoding method based on the interleaving exclusive-or algorithm as claimed in claim 3, characterized in that when the first channel signal receiver receives the link signal to be transmitted, each bit of the decoded link signal to be transmitted is sampled by the first sampling game algorithm module, the sampling times are CYCLE = CLK _ FRE/BAUD _ RATE, CLK _ FRE is the system clock frequency of the decoding module, BAUD _ RATE is the serial transmission BAUD RATE; setting a high level counter and a low level counter in the first sampling game algorithm module, wherein when the sampling signal is at a high level, the high level counter is increased by one, and when the sampling signal is at a low level, the low level counter is increased by one; after each pair of one-bit sampling CYCLE times, the counting values of the high-level counter and the low-level counter are played, and the high level and the low level of the bit are selected according to the principle that a small number of bits obey most in a game algorithm; after bit receiving is finished, register zero clearing operation is carried out on the two counters, and the game continues to be played on the next bit; when the count values of the high level counter and the low level counter become equal, the position is set as a warning bit.
7. The serial UART coding and decoding method based on the interleaving XOR algorithm as claimed in claim 3, characterized in that when the redundant channel signal receiver receives the redundant data, each bit of the redundant data is sampled by the second sampling game algorithm module, the sampling times are CYCLE = CLK _ FRE/BAUD _ RATE, CLK _ FRE is the system clock frequency of the decoding module, BAUD _ RATE is the serial transmission BAUD RATE; a high level counter and a low level counter are arranged in the second sampling game algorithm module, when the sampling signal is at a high level, the high level counter is increased by one, and when the sampling signal is at a low level, the low level counter is increased by one; after each pair of the first digit samples CYCLE times, the counting values of the high level counter and the low level counter are played, the high level and the low level of the digit are selected according to the principle that a small number of digits obey most in a game algorithm, after the digit is received, the two counters are subjected to register zero clearing operation, and the next digit is played continuously; when the count values of the high level counter and the low level counter become equal, the position is set as a warning bit.
8. The serial UART coding and decoding method based on the interleaving XOR algorithm of claim 7 is characterized in that when the data of the redundant channel is abnormal, the data is decoded by using the same interleaving XOR algorithm as that used for coding so as to achieve the effect of recovering the abnormality; when more than two coefficients in the interleaving XOR algorithm are warning bits, only the warning bits are subjected to receiving operation but not other operations, and data continues to be received until more than two coefficients in the algorithm are not warning bits; and recovering all the warning bits of the first channel received data and the redundant channel received data before the bit, recovering the warning bit of the bit through an algorithm, wherein the recovered data is a received correct value, replacing the warning bit data value of the current bit by using the correct value, and simultaneously continuing to perform algorithm operation by using the replaced correct value until all the warning bits before the bit are recovered to be correct values, thereby realizing the function of correcting errors when the serial reception is abnormal.
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