CN114695525A - Semiconductor device and method for manufacturing semiconductor device - Google Patents
Semiconductor device and method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN114695525A CN114695525A CN202011643648.2A CN202011643648A CN114695525A CN 114695525 A CN114695525 A CN 114695525A CN 202011643648 A CN202011643648 A CN 202011643648A CN 114695525 A CN114695525 A CN 114695525A
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- substrate
- semiconductor device
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 193
- 239000002184 metal Substances 0.000 claims abstract description 193
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 238000002955 isolation Methods 0.000 claims abstract description 56
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000001465 metallisation Methods 0.000 claims description 11
- 239000003989 dielectric material Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 9
- 238000002360 preparation method Methods 0.000 abstract description 9
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 description 16
- 239000000463 material Substances 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 11
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 229910002704 AlGaN Inorganic materials 0.000 description 8
- 230000005669 field effect Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000001451 molecular beam epitaxy Methods 0.000 description 6
- 230000006911 nucleation Effects 0.000 description 5
- 238000010899 nucleation Methods 0.000 description 5
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 238000003877 atomic layer epitaxy Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000004549 pulsed laser deposition Methods 0.000 description 4
- 238000000927 vapour-phase epitaxy Methods 0.000 description 4
- 241001391944 Commicarpus scandens Species 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- -1 InAlN Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000002178 crystalline material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the invention provides a semiconductor device and a preparation method of the semiconductor device, and relates to the technical field of microelectronics, the semiconductor device comprises a substrate, a semiconductor layer, a metal electrode and a metal connecting layer, the semiconductor layer is positioned on one side of the substrate, the metal electrode is positioned on one side of the semiconductor layer away from the substrate, the metal electrode comprises a source electrode, the metal connecting layer is positioned on one side of the source electrode away from the substrate and is connected with the source electrode, the metal connecting layer is divided into at least two metal connecting blocks by an isolation structure, so that in the process of depositing and forming the metal connecting layer, redundant metal positioned on one side of the metal connecting layer can be connected with corresponding metal deposits at the isolation structure, the area of the metal deposits to be stripped is larger, the stripping of the redundant metal is easier, the stripping process of a field plate is safer, the structure and the metal connecting layer can not be damaged, the manufacturing process difficulty of the metal connecting layer and the field plate structure is reduced, and the manufacturing efficiency is improved.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a semiconductor device and a preparation method of the semiconductor device.
Background
The semiconductor material gallium nitride has become a research hotspot at present due to the characteristics of large forbidden bandwidth, high electron saturation drift velocity, high breakdown field strength, good heat-conducting property and the like. In the aspect of electronic devices, gallium nitride materials are more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power devices than silicon and gallium arsenide, so that the gallium nitride-based electronic devices have good application prospects.
Generally, in a semiconductor device, a conductive interconnection metal layer is usually disposed on a source metal electrode for connecting other external structures, such as a field plate structure, which is often used to adjust an electric field, and how to design and layout the conductive metal layer, the field plate, and surrounding structures during process manufacturing may greatly affect reliability and stability of the device, and may also affect difficulty of the process manufacturing.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method of the semiconductor device, which can match a field plate structure, reduce the process difficulty and improve the manufacturing efficiency.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a semiconductor device comprising:
a substrate;
a semiconductor layer on one side of the substrate;
the metal electrode is positioned on one side of the semiconductor layer, which is far away from the substrate, and comprises a source electrode;
the metal connecting layer is positioned on one side of the source electrode, which is far away from the substrate, and is connected with the source electrode;
the metal connecting layer is provided with an isolation structure, and the isolation structure divides the metal connecting layer into at least two metal connecting blocks.
In an alternative embodiment, the isolation structure is hollowed out or filled with a dielectric material.
In an alternative embodiment, the isolation structure comprises at least two dividing line portions, at least two of which intersect and separate the metal connection layer into at least two metal connection blocks.
In an alternative embodiment, each of the dividing line portions extends to an edge of the metal connection layer.
In an alternative embodiment, the width of each of the line segments is greater than or equal to 2 microns.
In an optional embodiment, the semiconductor device further includes a dielectric layer, the dielectric layer is located on a side of the semiconductor layer away from the substrate, and at least two of the metal connection blocks are connected to the dielectric layer.
In an alternative embodiment, the projected area S1 of the metal connection layer on the substrate is 0.4-1.6 times the projected area S2 of the source electrode on the substrate.
In a second aspect, the present invention provides a method for manufacturing a semiconductor device, comprising:
manufacturing a semiconductor layer on one side of a substrate;
manufacturing a source electrode, a grid electrode and a drain electrode on one side of the semiconductor layer far away from the substrate;
manufacturing a metal connecting layer on one side of the source electrode, which is far away from the substrate;
the metal connecting layer is connected with the source electrode, an isolating structure is arranged on the metal connecting layer, and the isolating structure divides the metal connecting layer into at least two metal connecting blocks.
In an alternative embodiment, before the step of forming the metal connection layer on the side of the source electrode away from the substrate, the method further comprises:
and manufacturing a dielectric layer on one side of the semiconductor layer far away from the substrate.
In an alternative embodiment, the step of forming a metal connection layer on a side of the source electrode away from the substrate includes:
coating a first photoresist layer on one side of the dielectric layer, which is far away from the substrate, and developing the shape of the source electrode;
etching and removing the dielectric layer on the side of the source electrode far away from the substrate;
coating a second photoresist layer on one side of the source electrode, which is far away from the substrate, and developing the shape of the metal connecting layer;
performing metal deposition on one side of the second photoresist layer far away from the substrate;
and stripping the metal deposit corresponding to the isolation structure and forming the metal connecting layer.
The beneficial effects of the embodiment of the invention include, for example:
according to the semiconductor device and the preparation method thereof provided by the invention, the metal connecting layer is arranged on the source electrode to realize the connection with the field plate structure, meanwhile, the isolation structure is arranged on the metal connecting layer and divides the metal connecting layer into at least two metal connecting blocks, so that in the process of depositing and forming the metal connecting layer, redundant metal on one side of the metal connecting layer can be connected with the metal deposit corresponding to the isolation structure, and the area of the metal deposit to be stripped is increased, so that the stripping is easier, the stripped metal is not easy to break, the stripping process is safer, the field plate structure and the metal connecting layer cannot be damaged, the difficulty of the manufacturing process of the metal connecting layer and the field plate structure is reduced, and the manufacturing efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention from a first viewing angle;
fig. 2 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention from a second viewing angle;
fig. 3 is a schematic view of a connection structure of a semiconductor device and a field plate structure according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention;
fig. 5 is a schematic view of a connection structure of a semiconductor device and a field plate structure according to a second embodiment of the present invention;
fig. 6 is a block diagram illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
Icon: 100-a semiconductor device; 110-a substrate; 130-a semiconductor layer; 131-a nucleation layer; 133-a buffer layer; 135-a channel layer; 137-barrier layer; 150-a metal electrode; 151-source; 153-gate; 155-drain electrode; 170-metal connection layer; 171-an isolation structure; 173-metal connecting block; 175-parting line portions; 190-a dielectric layer; 200-field plate structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background art, in the conventional semiconductor device, such as the hemt, the connection to the source field plate is realized by a conductive interconnection metal layer disposed on the source electrode, and the conductive interconnection metal layer is a bulk deposition structure, which mainly plays a role of connecting the source field plate and the source electrode. In the preparation process, the conductive metal interconnection layer and the source field plate need to be formed through a metal deposition process, stripping is needed after metal deposition, redundant metal connected with an external passive region around the source field plate and redundant metal between the conductive interconnection metal layer and the source field plate need to be stripped, the stripping process is very troublesome, the structure of the source field plate is easily damaged, the difficulty of the preparation process of the device is steep, and the manufacturing efficiency is reduced.
In order to solve the above problems, the present invention provides a semiconductor device, and it is to be noted that features in embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1 to fig. 3, the present embodiment provides a semiconductor device 100, which can match with a field plate structure 200, so that the metal stripping process is simpler, safer and more reliable, the process difficulty is reduced, and the manufacturing efficiency is improved.
The semiconductor device 100 provided by the embodiment includes a substrate 110, a semiconductor layer 130, a metal electrode 150 and a metal connection layer 170, wherein the semiconductor layer 130 is located on one side of the substrate 110, the metal electrode 150 is located on one side of the semiconductor layer 130 away from the substrate 110, the metal electrode 150 includes a source 151, the metal connection layer 170 is located on one side of the source 151 away from the substrate 110 and is connected to the source 151, an isolation structure 171 is disposed on the metal connection layer 170, and the isolation structure 171 separates the metal connection layer 170 into at least two metal connection blocks 173.
In the present embodiment, the isolation structure 171 is used to separate the metal connection layer 170 into at least two metal connection blocks 173, the metal connection layer 170 can be used to connect electrical components such as the field plate structure 200, the metal connection layer 170 is used to connect the field plate structure 200 in the present embodiment as an example, and in other preferred embodiments, the metal connection layer 170 can also be connected to other electrical components. By arranging the isolation structure 171, in the process of depositing the metal connection layer 170, the redundant metal adjacent to the field plate structure 200 and connected with the external passive region can be connected with the metal deposit corresponding to the isolation structure 171, so that in the process of depositing the metal connection layer, the redundant metal on one side of the metal connection layer 170 can be connected with the metal deposit corresponding to the isolation structure 171, the area of the metal deposit to be stripped is increased, stripping is easier, stripping metal is not easy to break, the stripping process is safer, the field plate structure 200 and the metal connection layer 170 cannot be damaged, the difficulty of the manufacturing process of the metal connection layer 170 and the field plate structure 200 is reduced, and the manufacturing efficiency is improved.
In the present embodiment, the substrate 110 functions to support the semiconductor layer 130, and the substrate 110 may be one or a combination of more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides. The Deposition method of the substrate 110 may employ CVD (Chemical Vapor Deposition), VPE (Vapor Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), atomic layer Epitaxy, MBE (Molecular Beam Epitaxy), sputtering, evaporation, and the like.
In the present embodiment, the semiconductor layer 130 is formed on the substrate 110, and the semiconductor layer 130 may be fabricated by MOCVD, MBE, atomic layer epitaxy, or the like. The semiconductor layer 130 may include a nucleation layer 131, a buffer layer 133, a channel layer 135, and a barrier layer 137, which are sequentially stacked, wherein the nucleation layer 131 is located at a side of the substrate 110, the buffer layer 133 is located at a side of the nucleation layer 131 away from the substrate 110, the channel layer 135 is located at a side of the buffer layer 133 away from the substrate 110, the barrier layer 137 is located at a side of the channel layer 135 away from the substrate 110, and the barrier layer 137 and the channel layer 135 constitute a heterojunction. The buffer layer 133 serves to bond other semiconductor layers 130 that are grown next, specifically, the substrate 110 and the channel layer 135, and also can protect the substrate 110 from being invaded by some metal ions, and the buffer layer 133 is AlGaN with a controllable aluminum content. A channel layer 135 is deposited and grown on the buffer layer 133, and the channel layer 135 serves as a channel for providing movement of Two Dimensional Electron Gas (2 DEG). Wherein the channel layer 135 may be one or more of undoped, n-doped or n-type partially doped GaN, AlGaN, InAlN, or AlN. The barrier layer 137 is deposited on the buffer layer 133 and may be any semiconductor material capable of forming a heterojunction structure with the channel layer 135, including a gallium-based compound semiconductor material or a group III nitride semiconductor material, such as InAlGaN. Specifically, AlGaN is used in the embodiment, and the Al content is controllable, i.e. 0 < Al% < 1. The AlGaN barrier layer 137 forms a heterojunction structure together with the underlying channel layer 135, and forms a two-dimensional electron gas (2DEG) near the channel layer 135 at a heterojunction interface.
It should be noted that the semiconductor device 100 mentioned in the present embodiment includes, but is not limited to: a High power gallium nitride High Electron Mobility Transistor (HEMT) operating in a High voltage and High current environment, a Silicon-On-Insulator (SOI) structure Transistor On the insulating substrate 110, a gallium arsenide (GaAs) based Transistor, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), a Metal-Insulator-Semiconductor Field Effect Transistor (Metal-Semiconductor Field-Effect Transistor, MISFET), a Double Heterojunction Field Effect Transistor (dhjunction), a Junction-Field-Effect Transistor (JFET), a Metal-Semiconductor Field Effect Transistor (Metal-Semiconductor Field-Effect Transistor, JFET), MISHFET for short) or other field effect transistors.
In this embodiment, the metal electrode 150 may further include a drain electrode 155 and a gate electrode 153, wherein the source electrode 151 and the drain electrode 155 are both located on the barrier layer 137, the gate electrode 153 is located between the source electrode 151 and the drain electrode 155 and located on the barrier layer 137, and the gate electrode 153 may be a T-shaped gate and is configured to correspond to the field plate structure 200, so as to implement the function of adjusting the electric field through the field plate structure 200. Specifically, there is also a dielectric space between the gate 153 and the field plate structure 200, which may be filled with a dielectric layer 190, and the isolation structure 171 extends into the dielectric space. The source and drain electrodes 151 and 155 are electrically connected to the 2DEG in the semiconductor layer 130.
In this embodiment, the isolation structure 171 may be filled with a dielectric material, air, or a combination thereof, and when the isolation structure 171 is filled with air, the isolation structure 171 is hollowed out. When the isolation structure 171 is filled with a dielectric material, it is referred to as being filled with an insulating material, such as SiN or resin. By filling the insulating material, the structure of the metal connection layer 170 can be more stable, and the device performance is more reliable.
In the present embodiment, the isolation structure 171 includes at least two dividing line portions 175, and the at least two dividing line portions 175 intersect and separate the metal connection layer 170 into at least two metal connection blocks 173. Specifically, the dividing line portion 175 in the present embodiment is linear, and in other preferred embodiments, the dividing line portion 175 may be partially or entirely curved. When applied to a single device, the plurality of dividing line portions 175 may be spliced to form a T-shaped structure or an L-shaped structure, and when applied to at least two devices, the plurality of dividing line portions 175 may be spliced to form a cross-shaped structure or a m-shaped structure. Preferably, the isolation structure 171 in this embodiment includes two dividing line portions 175, and the two dividing line portions 175 intersect in the middle and form a cross-shaped structure, which partitions the metal connection layer 170 into four metal connection blocks 173, each metal connection block 173 being used for connection with the field plate structure 200.
It should be noted that in this embodiment, the metal connection layer 170 is formed on the source 151 by metal deposition, specifically, after the surface of the source 151 is coated with photoresist, the isolation structure 171 is used as a mask to develop the shape of the metal connection layer 170, then metal deposition is performed, and finally the excess metal is stripped off, in the stripping process, due to the existence of the isolation structure 171, the surrounding excess metal deposit can be connected with the metal deposit corresponding to the isolation structure 171, the area of the metal to be stripped is increased, so that the excess metal is stripped off more easily, and the stripping process is safer, and the metal connection layer 170 is not damaged. Of course, the field plate structure 200 can be formed simultaneously here, and the field plate structure 200 can be integrally formed with the metal connection layer 170, and the stripping process of the field plate structure 200 is made easier and safer by the isolation structure 171.
In the present embodiment, each of the division line portions 175 extends to an edge of the metal connection layer 170, and at least one of the division line portions 175 extends to an edge of the dielectric space and communicates with the dielectric space, so that the isolation structure 171 communicates with the dielectric space and is connected with the inactive area, i.e., so that the dielectric space between the source electrode 151 and the gate electrode 153 is connected with the inactive area through the isolation structure 171.
In the present embodiment, the width of each of the dividing line portions 175 is greater than or equal to 2 micrometers, and the width of the dividing line portion 175 is less than the width of the metal connection layer 170. Preferably, the width of each of the dividing line portions 175 is the same, so that the stability of the device can be improved. In this embodiment, the width of the dividing line 175 refers to the distance between two adjacent metal connecting blocks 173.
In this embodiment, the edge of each metal connecting block 173 is further provided with a connecting bridge structure (not shown), through which a connection with a field plate can be achieved, and at least one dividing line portion 175 exists between two adjacent connecting bridge structures, so that each connecting bridge structure can be connected with each independent metal connecting block 173. The number of the connecting bridge structures is less than or equal to the number of the metal connecting blocks 173.
In the present embodiment, the projected area S1 of the metal connection layer 170 on the substrate 110 is 0.4-1.6 times the projected area S2 of the source 151 on the substrate 110. Specifically, in the present embodiment, the metal connection layer 170 covers the source 151, and in the present embodiment, the surface of the substrate 110 is used as a projection plane, and the difference between the projection area S1 of the metal connection layer 170 and the projection plane S2 of the source 151 is not large, so that the manufacturing process is simpler, and the structure is more stable, and the area difference between S1 and S2 is less than or equal to 3/5 of S2. Of course, the projected area of the metal connection layer 170 here includes the projected area of the metal connection block 173 and the projected area of the isolation structure 171. When the projected area of the metal connection layer 170 above the source 151 is larger than the projected area of the source 151, the metal connection layer 170 above the source 151 is stripped of the excess metal, and after the isolation structure 171 is formed, the projected areas of the remaining metal connection blocks 173 may be larger or smaller than the projected area of the source 151, which is not limited in this embodiment.
In summary, the present embodiment provides a semiconductor device 100, wherein the metal connection layer 170 is disposed on the source electrode 151, so as to achieve connection with the field plate structure 200, meanwhile, the isolation structure 171 is disposed on the metal connection layer 170, and the isolation structure 171 partitions the metal connection layer 170 into at least two metal connection blocks 173, so that in the process of forming the metal connection layer 170 by deposition, the excess metal to be stripped can be connected with the metal deposit corresponding to the isolation structure 171, and the area of the metal to be stripped is increased, so that the excess metal is easier to strip, the stripped metal is not easy to break, the stripping process is safer, the field plate structure 200 and the metal connection layer 170 are not damaged, the difficulty in the manufacturing process of the metal connection layer 170 and the field plate structure 200 is reduced, and the manufacturing efficiency is improved.
Second embodiment
Referring to fig. 4 and 5, the present embodiment provides another semiconductor device 100, the basic structure and principle thereof and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, corresponding contents in the first embodiment may be referred to where this embodiment is not mentioned.
The semiconductor device 100 provided by this embodiment includes a substrate 110, a semiconductor layer 130, a metal electrode 150, a metal connection layer 170 and a dielectric layer 190, wherein the semiconductor layer 130 is located on one side of the substrate 110, the metal electrode 150 is located on one side of the semiconductor layer 130 away from the substrate 110, the metal electrode 150 includes a source 151, a drain 155 and a gate 153, the metal connection layer 170 is located on one side of the source 151 away from the substrate 110 and is connected to the source 151, an isolation structure 171 is disposed on the metal connection layer 170, and the isolation structure 171 separates the metal connection layer 170 into at least two metal connection blocks 173. A dielectric layer 190 is located on a side of the semiconductor layer 130 away from the substrate 110, and at least two metal connection pads 173 are connected to the dielectric layer 190.
In this embodiment, the gate 153 is located between the source 151 and drain 155, and a dielectric layer 190 covers at least the gate 153 and is used to fill the dielectric space between the gate 153 and the field plate. Preferably, dielectric layer 190 covers drain 155 and gate 153 and is formed with a trench for field plate structure 200 to extend into, and field plate structure 200 is adapted to be disposed on a surface of dielectric layer 190 away from substrate 110 and extend into the trench on dielectric layer 190. By providing the dielectric layer 190, the field plate structure 200 can be better supported, and the dielectric space can be filled, so that the field plate structure 200 can realize the function of adjusting the electric field. Dielectric layer 190 may be a crystalline material, such as GaN or AlN, deposited during growth or processing, or may be an amorphous material, such as SiN, deposited during growth or processing.
In other preferred embodiments of the present invention, the dielectric layer 190 may also cover only the gate 153 and be self-aligned with the gate 153, and the remaining dielectric space is an air dielectric, which can also ensure the function of the field plate structure 200.
In the present embodiment, isolation structure 171 includes at least two dividing line portions 175, where at least two dividing line portions 175 intersect and separate metal connection layer 170 into at least three metal connection blocks 173, and at least one dividing line portion 175 is connected to dielectric layer 190. Thereby allowing isolation structure 171 to be connected to dielectric layer 190 and to the inactive region, i.e., allowing dielectric layer 190 between source 151 and gate 153 to be connected to the inactive region through isolation structure 171.
In the semiconductor device 100 provided by this embodiment, the dielectric layer 190 is additionally disposed, so that the field plate structure 200 can be better supported, and the dielectric space can be filled, so that the field plate structure 200 can realize the function of adjusting the electric field.
Third embodiment
Referring to fig. 6, the present embodiment provides a method for manufacturing a semiconductor device 100 for manufacturing the semiconductor device 100 as provided in the first embodiment or the second embodiment, the method for manufacturing the semiconductor device 100 including the steps of:
s1: a semiconductor layer 130 is fabricated on one side of the substrate 110.
Specifically, a substrate 110 is provided, a semiconductor layer 130 is formed on the substrate 110, and specifically, a nucleation layer 131, a buffer layer 133, a channel layer 135 and a barrier layer 137 are sequentially prepared on an upper surface of the substrate 110. The substrate 110 may be one or a combination of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides. The buffer layer 133 serves to bond other semiconductor layers 130 that are grown next, specifically, the substrate 110 and the channel layer 135, and also can protect the substrate 110 from being invaded by some metal ions, and the buffer layer 133 is AlGaN with a controllable aluminum content. A channel layer 135 is deposited and grown on the buffer layer 133, and the channel layer 135 serves as a channel for providing movement of Two Dimensional Electron Gas (2 DEG). Wherein the channel layer 135 may be one or more of undoped, n-doped or n-type partially doped GaN, AlGaN, InAlN, or AlN. Barrier layer 137 is deposited on buffer layer 133 and its deposited material may be any semiconductor material capable of forming a heterojunction structure with channel layer 135, including gallium-based compound semiconductor materials or group III nitride semiconductor materials, such as InAlGaN. Specifically, AlGaN is used in the embodiment, and the Al content is controllable, i.e. 0 < Al% < 1. The AlGaN barrier layer 137 forms a heterojunction structure together with the underlying channel layer 135, and forms a two-dimensional electron gas (2DEG) near the channel layer 135 at a heterojunction interface.
The Deposition method of the substrate 110 may employ CVD (Chemical Vapor Deposition), VPE (Vapor Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), atomic layer Epitaxy, MBE (Molecular Beam Epitaxy), sputtering, evaporation, and the like. The method of fabricating the semiconductor layer 130 may be MOCVD, MBE, atomic layer epitaxy, etc.
S2: a metal electrode 150 is formed on the side of the semiconductor layer 130 remote from the substrate 110.
Specifically, the metal electrode 150 includes a source electrode 151, and may further include a drain electrode 155 and a gate electrode 153, and the source electrode 151 and the drain electrode 155 are electrically connected to the two-dimensional electron gas (2DEG) in the semiconductor layer 130 by, but not limited to, high temperature annealing, ion implantation, and heavy doping. After the source and drain electrodes 151 and 155 are formed, a gate groove is formed on the surface of the semiconductor layer 130 through an etching process, and then metal is deposited on an exposed region of the gate electrode 153, thereby forming the gate electrode 153, and the gate electrode 153 may be a T-shaped gate.
S3: a metal connection layer 170 is formed on the side of the source 151 remote from the substrate 110.
Specifically, in the preparation of the semiconductor device 100 as provided in the first embodiment, a photoresist layer may be directly coated on the side of the source 151 away from the substrate 110, the shape of the metal connection layer 170 is developed by using the isolation structure 171 as a mask, and metal deposition is performed on the side of the photoresist layer away from the substrate 110 to strip off the metal deposit corresponding to the isolation structure 171 and other excess metal deposits, thereby forming the metal connection layer 170. The metal connection layer 170 is connected to the source 151, an isolation structure 171 is disposed on the metal connection layer 170, and the isolation structure 171 separates the metal connection layer 170 into at least two metal connection blocks 173.
It should be noted that after the isolation structure 171 is molded, it may be filled with a dielectric material, air, or a combination thereof. The boundary of the isolation structure 171 is to penetrate the metal connection layer 170 above the source electrode 151, and an opening is formed such that each of the dividing line portions 175 extends to the edge of the metal connection layer 170.
It is to be noted that, in the preparation of the semiconductor device 100 as provided in the second embodiment, before performing step S3, the method further includes the steps of:
and manufacturing a dielectric layer 190 on the side of the semiconductor layer 130 far away from the substrate 110, wherein the dielectric layer 190 covers the drain electrode 155 and the gate electrode 153. Specifically, a crystalline material (e.g., GaN, AlN, or the like) or an amorphous material (e.g., SiN, or the like) is deposited on the semiconductor layer 130 to form a dielectric layer 190 covering the source 151, the drain 155, and the gate 153, a photoresist is coated on an upper surface of the dielectric layer 190, the source 151 region is exposed, the shape of the source 151 is developed, and then the dielectric layer 190 located above the source 151 is removed by an etching process to facilitate the subsequent fabrication of the metal connection layer 170 above the source 151. Here, the dielectric layer 190 above the source 151 may be completely removed, or the dielectric layer 190 above the source 151 may be partially removed, for example, the dielectric layer 190 may be removed in an area of 65% of the source 151. Here, it is only necessary to expose the source electrode 151 and enable the formation of the subsequent metal connection layer 170.
In the fabrication of the semiconductor device 100 according to the second embodiment, a dielectric layer 190 is grown on the barrier layer 137, a photoresist is coated on the dielectric layer, the source 151 is etched, the dielectric layer 190 on the source 151 is completely etched, a photoresist is coated, the shape of the metal connection layer 170 is developed on the photoresist by using the isolation structure 171 as a mask, then metal deposition is performed, and finally the excess metal deposition is stripped. The stripped portion above source 151 is isolation structure 171.
In the present embodiment, the metal connection layer 170 is used to connect the field plate structure 200, wherein the field plate structure 200 can be integrally formed with the metal connection layer 170, and the excess metal adjacent to the field plate structure 200 and connected to the external passive region can be connected to the corresponding metal deposit at the isolation structure 171, so as to reduce the stripping difficulty and make the stripping process simpler and safer. Specifically, after the dielectric layer 190 above the source electrode 151 is completely etched away, a layer of photoresist is coated on the upper surface of the source electrode 151 and the upper surface of the dielectric layer 190, shapes of the metal connection layer 170 and the field plate structure 200 are developed on the photoresist, then metal deposition is performed, and after the metal connection layer 170 and the field plate structure 200 are integrally formed, an excessive metal deposition is stripped.
According to the preparation method of the semiconductor device 100 provided by the invention, the metal connecting layer 170 is arranged on the source electrode 151 to realize the connection with the field plate structure 200, meanwhile, the isolation structure 171 is arranged on the metal connecting layer 170, and the isolation structure 171 divides the metal connecting layer 170 into at least two metal connecting blocks 173, so that in the process of depositing and forming the metal connecting layer 170, redundant metal can be connected with the corresponding metal deposit at the position of the isolation structure 171, and the area of the metal deposit to be stripped is larger, so that the stripping of the redundant metal is easier, the difficulty of the manufacturing process of the metal connecting layer 170 and the field plate structure 200 is reduced, and the manufacturing efficiency is improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A semiconductor device, comprising:
a substrate;
a semiconductor layer on one side of the substrate;
the metal electrode is positioned on one side of the semiconductor layer, which is far away from the substrate, and comprises a source electrode;
the metal connecting layer is positioned on one side of the source electrode, which is far away from the substrate, and is connected with the source electrode;
the metal connecting layer is provided with an isolation structure, and the isolation structure divides the metal connecting layer into at least two metal connecting blocks.
2. The semiconductor device of claim 1, wherein the isolation structure is hollowed out or filled with a dielectric material.
3. The semiconductor device according to claim 1, wherein the isolation structure comprises at least two dividing line portions, at least two of the dividing line portions intersecting and dividing the metal connection layer into at least two of the metal connection blocks.
4. The semiconductor device of claim 3, wherein each of the dividing line portions extends to an edge of the metal connection layer.
5. The semiconductor device according to claim 3, wherein a width of each of the dividing line portions is greater than or equal to 2 μm.
6. The semiconductor device according to claim 1, further comprising a dielectric layer on a side of the semiconductor layer away from the substrate, wherein at least two of the metal connection blocks are connected to the dielectric layer.
7. The semiconductor device according to any one of claims 1 to 6, wherein a projected area S1 of the metal connection layer on the substrate is 0.4 to 1.6 times a projected area S2 of the source electrode on the substrate.
8. A method of manufacturing a semiconductor device, comprising:
manufacturing a semiconductor layer on one side of a substrate;
manufacturing a metal electrode on one side of the semiconductor layer far away from the substrate, wherein the metal electrode comprises a source electrode;
manufacturing a metal connecting layer on one side of the source electrode, which is far away from the substrate;
the metal connecting layer is connected with the source electrode, an isolating structure is arranged on the metal connecting layer, and the isolating structure divides the metal connecting layer into at least two metal connecting blocks.
9. The method for manufacturing a semiconductor device according to claim 8, wherein before the step of forming a metal connection layer on a side of the source electrode away from the substrate, the method further comprises:
and manufacturing a dielectric layer on one side of the semiconductor layer far away from the substrate.
10. A method for manufacturing a semiconductor device according to claim 8 or 9, wherein the step of forming a metal connection layer on the side of the source electrode away from the substrate comprises:
coating a photoresist layer on one side of the source electrode, which is far away from the substrate, and developing the shape of the metal connecting layer;
performing metal deposition on one side of the photoresist layer far away from the substrate;
and stripping the metal deposit corresponding to the isolation structure and forming the metal connecting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011643648.2A CN114695525A (en) | 2020-12-30 | 2020-12-30 | Semiconductor device and method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011643648.2A CN114695525A (en) | 2020-12-30 | 2020-12-30 | Semiconductor device and method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114695525A true CN114695525A (en) | 2022-07-01 |
Family
ID=82135498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011643648.2A Pending CN114695525A (en) | 2020-12-30 | 2020-12-30 | Semiconductor device and method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114695525A (en) |
-
2020
- 2020-12-30 CN CN202011643648.2A patent/CN114695525A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103311244B (en) | Semiconductor device and the method being used for producing the semiconductor devices | |
| US9871107B2 (en) | Device with a conductive feature formed over a cavity and method therefor | |
| US20150349124A1 (en) | Transistor structure having buried island regions | |
| EP2955755B1 (en) | Nitride high-voltage component and manufacturing method therefor | |
| CN106298882A (en) | HEMT devices and manufacture method thereof | |
| US10608102B2 (en) | Semiconductor device having a drain electrode contacting an epi material inside a through-hole and method of manufacturing the same | |
| CN114127955B (en) | Semiconductor device and method for manufacturing the same | |
| CN112420850A (en) | Semiconductor device and preparation method thereof | |
| CN112736136B (en) | Semiconductor device and preparation method thereof | |
| CN103208419A (en) | Semiconductor transistor having trench contacts and method for forming same | |
| CN114127954B (en) | Semiconductor device and method for manufacturing the same | |
| US11695052B2 (en) | III-Nitride transistor with a cap layer for RF operation | |
| US20230352575A1 (en) | A vertical hemt and a method to produce a vertical hemt | |
| CN114695525A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN118020159A (en) | Nitride-based semiconductor device and method of manufacturing the same | |
| US11152364B1 (en) | Semiconductor structure and methods for manufacturing the same | |
| CN111627988B (en) | Semiconductor device and preparation method thereof | |
| TW201737354A (en) | Semiconductor device, electronic part, electronic apparatus, and method for fabricating semiconductor device | |
| CN114695523A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| KR102248808B1 (en) | Semiconductor device and a method for manufacturing the same | |
| CN112117328A (en) | Semiconductor device and method for manufacturing the same | |
| CN114141737B (en) | Semiconductor device and method for manufacturing semiconductor device | |
| KR20140146849A (en) | nitride-based transistor with vertical channel and method of fabricating the same | |
| US11916140B2 (en) | Compound semiconductor device | |
| CN114709256B (en) | Semiconductor device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |