KR102248808B1 - Semiconductor device and a method for manufacturing the same - Google Patents

Abstract

A substrate in which an insulating layer is buried between the first semiconductor layer and the second semiconductor layer, a through hole penetrating through the commercial substrate, the through hole is a first hole penetrating the first semiconductor layer, and a bottom surface of the first hole An epi layer including a second hole penetrating the insulating layer and the second semiconductor layer, the epi layer disposed in the through hole, a drain electrode disposed in the second hole and contacting one surface of the epi layer, and the epi layer. It provides a semiconductor device including a source electrode and a gate electrode disposed on the other side.

Description

A semiconductor device and its manufacturing method TECHNICAL FIELD

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a vertical semiconductor device and a method of manufacturing the same.

Due to the development of information and communication technology, requests for high withstand voltage transistors operating in a high-speed switching environment or a high voltage environment are increasing. Thus, the recently appeared gallium nitride (GaN) transistor using a group III?-V semiconductor material is capable of high-speed switching operation compared to conventional silicon transistors, making it suitable for ultra-high signal processing and high breakdown voltage characteristics of the material itself. It is attracting attention from the industry because it has the advantage that it can be applied to a high voltage environment.

The gallium nitride-based transistor may be manufactured in a horizontal structure or a vertical structure. The horizontal structure has a structure in which charge conduction of the nitride-based transistor is performed in a horizontal direction, and a source electrode, a gate electrode, and a drain electrode are disposed on the same surface on the substrate. The vertical structure has a structure in which charge conduction is conducted in a vertical direction. The source electrode and the drain electrode of the vertical structure are arranged to face each other in the vertical direction, and the current is the aperture of the p-type gallium nitride (p-GaN) layer provided as a current barrier layer between the source electrode and the drain electrode. ) Flows in the vertical direction from the source electrode to the drain electrode.

The problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device with a simplified process.

Another problem to be solved by the present invention is to provide a semiconductor device having a simplified structure.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

In the semiconductor device according to embodiments of the present invention for solving the above-described technical problems, a substrate in which an insulating layer is buried between a first semiconductor layer and a second semiconductor layer, a through hole penetrating the commercial substrate, and the through hole are the An epi layer disposed in the through hole, the second hole including a first hole penetrating the first semiconductor layer and a second hole penetrating the insulating layer and the second semiconductor layer from a bottom surface of the first hole A drain electrode disposed in the hole and in contact with one surface of the epi layer, and a source electrode and a gate electrode disposed on the other surface of the epi layer may be included.

According to an embodiment, a lower surface of the epi layer may be disposed at a lower level than the insulating layer. The upper surface of the epi layer may be disposed at a higher level than the insulating layer.

According to an embodiment, the epitaxial layer may include an ohmic contact layer, a drift layer, a channel layer, and a barrier layer sequentially stacked from the drain electrode.

According to an embodiment, the drift layer may be disposed on a boundary between the first hole and the second hole. The upper surface of the drift layer may be located at a higher level than the insulating layer. A lower surface of the drift layer may be located at a lower level than the insulating layer.

According to an embodiment, the channel layer may be disposed on a boundary between the first hole and the second hole. The upper surface of the channel layer may be positioned at a higher level than the insulating layer. The lower surface of the channel layer may be located at a lower level than the insulating layer.

According to an embodiment, the barrier layer may include AlGaN, AlN, InN, InAlN, or AlGaInN. The channel layer may include GaN.

According to an embodiment, a spacer layer disposed between the epi layer and the inner wall of the through hole may be further included.

According to an embodiment, a width of the first hole may be greater than a width of the second hole.

A method of manufacturing a semiconductor device according to embodiments of the present invention for solving the above-described technical problems is to provide a substrate in which an insulating layer is buried between a first semiconductor layer and a second semiconductor layer, and the second semiconductor layer is Forming a first hole exposing the insulating layer by etching, forming a second hole extending into the first semiconductor layer by etching the exposed insulating layer, an epi layer on the bottom surface of the second hole Growing, forming a source electrode and a gate electrode on an upper surface of the epi layer, forming a third hole connected to the second hole by etching the first semiconductor layer, and the first semiconductor It may include forming a drain electrode extending from one surface of the layer into the third hole and in contact with the epi layer.

According to an embodiment, before forming the epi layer, it may further include forming a spacer layer covering the inner wall and the bottom surface of the first hole and the inner wall of the second hole.

According to an embodiment, the epi layer may include a buffer layer, an ohmic contact layer, a drift layer, a channel layer, and a barrier layer sequentially stacked from the bottom surface of the second hole.

According to an embodiment, during the etching process of the first semiconductor layer for forming the third hole, the buffer layer may be removed together.

According to an embodiment, the interface between the channel layer and the barrier layer may be disposed at a higher level than the insulating layer.

According to an embodiment, it may further include polishing the first semiconductor layer before forming the third hole.

According to an embodiment, a width of the first hole may be greater than a width of the second hole.

A separate current blocking layer for vertically flowing current between the semiconductor source electrodes and the drain electrodes according to embodiments of the present invention may not be required. That is, the structure of the semiconductor device can be simplified. When the epi layer of the substrate, the first semiconductor layer and the second semiconductor layer contain different semiconductor materials, the epi layer, the first and second semiconductor layers are formed on one surface of each of the different types of semiconductor devices or integrated circuits. Integration becomes possible. According to embodiments of the present invention, the epitaxial layer may be formed only in the active device region. In such a case, when a plurality of semiconductor devices are formed on the epi layer of the substrate, a device separation process for electrically separating the semiconductor devices may not be required. That is, the manufacturing process of the semiconductor device can be simplified.

A method of manufacturing a semiconductor device according to embodiments of the present invention may not require a separate process for forming a current blocking layer. In addition, when a plurality of semiconductor devices are formed on a substrate, a device separation process for electrically separating the semiconductor devices may not be required. That is, the manufacturing process of the semiconductor device can be simplified.

1 is a cross-sectional view illustrating a semiconductor device according to example embodiments.
2 is a cross-sectional view illustrating a semiconductor device according to example embodiments.
3 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.
12 and 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms and various modifications may be made. However, it is provided to complete the disclosure of the present invention through the description of the present embodiments, and to completely inform the scope of the present invention to those of ordinary skill in the art to which the present invention pertains. Those of ordinary skill in the art will understand that the inventive concept may be practiced in any suitable environment.

The terms used in the present specification are for describing exemplary embodiments and are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification,'comprises' and/or'comprising' refers to the presence of one or more other elements, steps, actions and/or elements in the referenced elements, steps, actions and/or elements. Or does not preclude additions.

When a film (or layer) is referred to herein as being on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate, or a third film ( Or a layer) may be interposed.

In various embodiments of the present specification, terms such as first, second, and third are used to describe various regions, films (or layers), and the like, but these regions and films should not be limited by these terms. do. These terms are only used to distinguish one region or film (or layer) from another region or film (or layer). Accordingly, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Parts indicated by the same reference numerals throughout the specification represent the same elements.

Terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those of ordinary skill in the art, unless otherwise defined.

Hereinafter, a semiconductor device according to the concept of the present invention and a method of manufacturing the same will be described with reference to the drawings.

1 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

Referring to FIG. 1, a substrate 10 may be provided. The substrate 10 may be a silicon on insulator (SOI) substrate. For example, the substrate 10 may include a first semiconductor layer 11, an insulating layer 12, and a second semiconductor layer 13 that are sequentially stacked. The insulating layer 12 may be buried between the first semiconductor layer 11 and the second semiconductor layer 13. The first semiconductor layer 11 may include silicon (Si), aluminum nitride (AlN), silicon carbide (SiC), and sapphire. The insulating layer 12 may include silicon oxide (SiO ₂ ) or rare earth oxide. The second semiconductor layer 13 may include silicon (Si), gallium nitride (GaN), or silicon carbide (SiC). The first semiconductor layer 11 and the second semiconductor layer 13 may include the same material. Unlike this, the first semiconductor layer 11 and the second semiconductor layer 13 may include different materials, or may have the same material but have different crystal directions. In addition, the substrate 10 may include various SOI substrates.

The substrate 10 may have a through hole H. The through hole H may vertically penetrate the first semiconductor layer 11, the insulating layer 12 and the second semiconductor layer 13. The through hole H may include a first hole H1 penetrating the second semiconductor layer 13 and a second hole H2 penetrating the insulating layer 12 and the first semiconductor layer 11. have. The width of the second hole H2 may be smaller than the width of the first hole H1. The first hole H1 and the second hole H2 may vertically overlap. The second hole H2 extends from the bottom surface of the first hole H1 to the bottom surface of the first semiconductor layer 11, and the first hole H1 and the second hole H2 may be connected to each other. That is, the through hole H may have a bolt shape having a wide upper portion and a narrow lower portion.

The spacer layer 20 may be disposed in the through hole H. The spacer layer 20 may conformally cover the inner wall and the bottom surface of the first hole H1 and the inner wall of the second hole H2. In this case, a part of the inner wall of the second hole H2 may be exposed. The spacer layer 20 may extend on the upper surface of the second semiconductor layer 13. The spacer layer 20 may include silicon nitride (SiN _x ). The spacer layer 20 may be omitted if necessary.

The epitaxial layer 30 may be disposed in the through hole H. The epitaxial layer 30 may fill the first hole H1 and may fill a part of the second hole H2. In this case, the upper surface of the epi layer 30 may be located at a higher level than the insulating layer 12, and the lower surface of the epi layer 30 may be located at a lower level than the insulating layer 12. The epitaxial layer 30 may be spaced apart from the substrate 10 by the spacer layer 20. The epitaxial layer 30 may include an ohmic contact layer 32, a drift layer 33, a channel layer 34, and a barrier layer 35.

The ohmic contact layer 32, the drift layer 33, the channel layer 34, and the barrier layer 35 may be sequentially stacked in a direction from the first semiconductor layer 11 to the second semiconductor layer 13 . The ohmic contact layer 32 may be disposed in the second hole H2, and the channel layer 34 and the barrier layer 35 may be disposed in the first hole H1. The drift layer 33 is disposed on the boundary between the first hole H1 and the second hole H2, and its upper surface is at a higher level than the insulating layer 12, and its lower surface is at a lower level than the insulating layer 12. Can be located in Alternatively, as shown in FIG. 2, the drift layer 33 may be positioned at a lower level than the insulating layer 12 on its upper surface. The channel layer 34 is disposed on the boundary between the first hole H1 and the second hole H2, and its upper surface is at a higher level than the insulating layer 12 and its lower surface is at a lower level than the insulating layer 12. Can be located in Hereinafter, description will be continued based on the embodiment of FIG. 1.

The ohmic contact layer 32 may be formed of n ⁺ type gallium nitride (n ⁺ -GaN). The ohmic contact layer 32 may make ohmic contact between the drift layer 33 and the drain electrode 60 to be described later, respectively. The drift layer 33 may be made of n-type gallium nitride (n-GaN). The n-type dopant of the ohmic contact layer 32 and the drift layer 33 may include silicon (Si). The channel layer 34 may be made of gallium nitride (GaN). The barrier layer 35 may be made of aluminum gallium nitride (AlGaN). By heterojunction between the channel layer 34 and the barrier layer 35, a 2-dimensional electron gas (2-DEG) type channel may be provided on the boundary between the channel layer 34 and the barrier layer 35. Here, the interface between the channel layer 34 and the barrier layer 35, that is, the channel may be disposed at a higher level than the insulating layer 12. Although the heterojunction between the channel layer 34 including gallium nitride (GaN) and the barrier layer 35 including aluminum gallium nitride (AlGaN) has been described, the present invention is not limited thereto. The channel layer 34 and the barrier layer 35 may include various materials having a heterojunction for a channel. For example, when the channel layer 34 includes gallium nitride (GaN), the barrier layer 35 is aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium nitride (InN), indium It may include aluminum nitride (InAlN) or aluminum gallium indium nitride (AlGaInN). Alternatively, when the channel layer 34 includes gallium arsenide (GaAs), the barrier layer 35 may include aluminum gallium arsenide (AlGaAs) or indium gallium arsenide (InGaAs).

Although not shown, a capping layer may be disposed on the epi layer 30. The capping layer may include gallium nitride (GaN). The capping layer may not be provided as needed.

A drain electrode 60 may be disposed on the lower surface of the epi layer 30. For example, the drain electrode 60 may extend from the lower surface of the first semiconductor layer 11 to the second hole H2 to contact the ohmic contact layer 32. The lower surface of the substrate 10 and the lower surface of the ohmic contact layer 32 may be conformally covered. The drain electrode 60 may make ohmic contact with the ohmic contact layer 32. The drain electrode 60 may include a metal.

A gate electrode 41 and source electrodes 42 may be disposed on the epi layer 30. The gate electrode 41 may be positioned between the source electrodes 42. The gate electrode 41 and the source electrodes 42 may make ohmic contact with the barrier layer 35. As an example, when the channel layer 34 includes gallium nitride (GaN), the gate electrode 41 and the source electrodes 42 are titanium (Ti), platinum (Pt), aluminum (Al), nickel ( It may be made of a metal multilayer containing Ni) or gold (Au). Alternatively, when the channel layer 34 includes gallium arsenide (GaAs), the gate electrode 41 and the source electrodes 42 include gold germanium (AuGe), nickel (Ni), or gold (Au). It may be made of a metal multilayer. The gate electrode 41 may control an amount of current flowing from the source electrodes 42 toward the drain electrode 60.

In the semiconductor device according to the embodiments of the present invention, the epi layer 30 is formed to penetrate the insulating layer 12 of the substrate 10, and accordingly, the current between the source electrodes 42 and the drain electrode 60 A separate current blocking layer for vertically flowing may not be required. In addition, when the first semiconductor layer 11 and the second semiconductor layer 13 of the substrate 10 contain different semiconductor materials, on one surface of each of the first and second semiconductor layers 11 and 13 Different types of semiconductor devices can be integrated.

3 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. For convenience of description, a description of a configuration overlapping with that described with reference to FIG. 1 may be omitted.

Referring to FIG. 3, a substrate 10 may be provided. The substrate 10 may be a silicon on insulator (SOI) substrate. For example, the substrate 10 may include an insulating layer 12 buried between the first semiconductor layer 11 and the second semiconductor layer 13.

Referring to FIG. 4, a first hole H1 may be formed in the substrate 10. For example, after forming the first mask pattern M1 exposing the second semiconductor layer 13 on the substrate 10, the first hole H1 is formed by etching the second semiconductor layer 13 Can be. The etching process of the second semiconductor layer 13 is a reactive ion etching (RIE) process, a magnetically enhanced reactive ion etching (MERIE) process, or an inductive coupled plasma (ICP) etching process. It may be performed through dry etching including a process. The first hole H1 may expose the upper surface 12a of the insulating layer 12.

Referring to FIG. 5, after the first mask pattern M1 is removed, a second hole H2 may be formed in the substrate 10. For example, after forming the second mask pattern M2 exposing the upper surface 12a of the insulating layer 12 on the second semiconductor layer 13, the insulating layer 12 and the first semiconductor layer 11 ) May be etched to form the second hole H2. The etching process of the insulating layer 12 and the etching process of the first semiconductor layer 11 include a reactive ion etching (RIE) process, a self-enhancing reactive ion etching (MERIE) process, or an induced defect plasma (ICP) etching process. It can be performed through etching. Different etching gases may be used in the etching process of the insulating layer 12 and the etching process of the first semiconductor layer 11. In this case, the second mask pattern M2 may cover a part of the top surface 12a of the exposed insulating layer 12. Accordingly, the width W2 of the second hole H2 may be smaller than the width W1 of the first hole H1. The second hole H2 may penetrate the insulating layer 12 and extend into the first semiconductor layer 11 to expose one surface 11a of the first semiconductor layer 11.

Referring to FIG. 6, after the second mask pattern M2 is removed, a spacer layer 20 may be formed on the substrate 10. For example, the upper surface of the second semiconductor layer 13, the inner wall and the bottom surface of the first hole H1 (here, the bottom surface of the first hole H1 is the upper surface 12a of the insulating layer 12) Hereinafter, the same reference numerals will be used) and the inner wall and the bottom surface of the second hole H2 (here, the bottom surface of the second hole H2 is one surface of the first semiconductor layer 11 ). The spacer layer 20 may be formed by applying _{silicon nitride (SiN x} ) to cover (11a). Hereinafter, the same reference numerals will be used). The spacer layer 20 conforms to the top surface of the second semiconductor layer 13, the inner wall and bottom surface 12a of the first hole H1, and the inner wall and bottom surface 11a of the second hole H2. It can be covered in (conformal). The spacer layer 20 includes a first portion 20a positioned on the bottom surface 12a of the first hole H1 and a second portion positioned on the bottom surface 11a of the second hole H2 ( 20b).

Referring to FIG. 7, a part of the spacer layer 20 may be etched. For example, after forming the third mask pattern M3 exposing the second portion 20b on the spacer layer 20, the second portion 20b may be etched. Accordingly, the spacer layer 20 may expose one surface 11a of the first semiconductor layer 11.

Referring to FIG. 8, after the third mask pattern M3 is removed, the epi layer 30 may be formed in the first hole H1 and the second hole H2. The epitaxial layer 30 may include a buffer layer 31, an ohmic contact layer 32, a drift layer 33, a channel layer 34, and a barrier layer 35. For example, the buffer layer 31 may be formed on the one surface 11a of the first semiconductor layer 11 exposed by the spacer layer 20. The buffer layer 31 may be formed using, for example, a selective epitaxial growth (SEG) process using the first semiconductor layer 11 as a seed. At this time, since only one surface 11a of the first semiconductor layer 11 is exposed by the spacer layer 20, the growth direction during the selective epitaxial growth (SEG) process is one surface of the first semiconductor layer 11 It may be a direction perpendicular to (11a). Alternatively, if necessary, after forming a seed layer on one surface 11a of the first semiconductor layer 11 exposed by the spacer layer 20, selective epitaxial growth (SEG) using the seed layer as a seed The buffer layer 31 may be formed using a process. Thereafter, the ohmic contact layer 32, the drift layer 33, the channel layer 34, and the barrier layer 35 are sequentially formed on the buffer layer 31 using a selective epitaxial growth (SEG) process. I can. That is, the epitaxial layer 30 may be grown from the bottom surface 11a of the second hole H2 so that the upper surface of the epi layer 30 may be formed to be positioned at a higher level than the insulating layer 12. At this time, the ohmic contact layer 32 may be formed so that its upper surface has a lower level than the insulating layer 12, and the drift layer 33 is grown from the upper surface of the ohmic contact layer 32 so that the upper surface thereof is an insulating layer ( It can be formed to have a higher level than 12). The buffer layer 31 may relieve stress due to the first semiconductor layer 11 and the ohmic contact layer 32 having different lattice constants. The buffer layer 31 may include gallium nitride (GaN). The ohmic contact layer 32 may include n ⁺ type gallium nitride (n ⁺ -GaN). The drift layer 33 may include n-type gallium nitride (n-GaN). The channel layer 34 may include gallium nitride (GaN). The barrier layer 35 may include aluminum gallium nitride (AlGaN).

Alternatively, the epi layer 30 may be formed through various methods such as chemical vapor deposition (CVD), and in this case, the spacer layer 20 may be omitted.

Referring to FIG. 9, gate electrodes 41 and source electrodes 42 may be formed on the upper surface of the barrier layer 35. For example, after forming a metal multilayer on the upper surface of the barrier layer 35, the gate electrode 41 and the source electrodes 42 may be formed by patterning the metal multilayer. The metal multilayer may include titanium (Ti), platinum (Pt), aluminum (Al), nickel (Ni), or gold (Au).

Referring to FIG. 10, a carrier substrate 50 may be provided on the substrate 10. The carrier substrate 50 may cover the barrier layer 35, the gate electrode 41, and the source electrodes 42 on the second semiconductor layer 13. Although not shown, the carrier substrate 50 may be adhered to the substrate 10 by an adhesive layer. The carrier substrate 50 may protect the gate electrode 41 and the source electrodes 42 during a post process and may support the substrate 10.

Although not shown, a thinning process may be performed on the substrate 10 if necessary. For example, the first semiconductor layer 11 may be polished to reduce its thickness.

Referring to FIG. 11, a third hole H3 may be formed in the substrate 10. For example, after forming a fourth mask pattern M4 exposing the first semiconductor layer 11 on the lower surface of the substrate 10, the first semiconductor layer 11 is etched to form a third hole H3. Can be formed. The etching process of the first semiconductor layer 11 may be performed through dry etching including a reactive ion etching (RIE) process, a self-enhancing reactive ion etching (MERIE) process, or an induced defect plasma (ICP) etching process. The third hole H3 may be formed at the same position as the second hole H2 in plan view. The third hole H3 may pass through the first semiconductor layer 11 and be connected to the second hole H2. During the etching process of the first semiconductor layer 11, the buffer layer 31 may be etched together. Accordingly, the third hole H3 may expose the lower surface of the ohmic contact layer 32.

Referring to FIG. 1 again, after removing the fourth mask pattern M4, the drain electrode 60 may be formed. The drain electrode 60 may be deposited under the substrate 10. For example, the drain electrode 60 has a metal film on the lower surface of the first semiconductor layer 11, the inner surfaces and the bottom surface of the third hole H3 (here, the bottom surface of the third hole H3 is in ohmic contact). It may be formed by applying to cover the lower surface of the layer 32 in a conformal manner. The drain electrode 60 may be deposited by a sputtering method.

Thereafter, the carrier substrate 50 is removed, so that the semiconductor device described with reference to FIG. 1 may be manufactured.

In the method of manufacturing a semiconductor device according to embodiments of the present invention, the epitaxial layer 30 is formed to penetrate the insulating layer of the substrate 10, and accordingly, a separate process for forming a current blocking layer This may not be necessary. In addition, by forming the epi layer 30 in the through hole H formed in the substrate 10 using a selective growth process, the epi layer 30 of the substrate 10, the first semiconductor layer 11 and the second When the semiconductor layer 13 contains different semiconductor materials, the epi layer 30 and the first and second semiconductor layers 11 and 13 are mutually integrated between different types of semiconductor devices or integrated circuits on one surface of each This becomes possible. According to embodiments of the present invention, the epitaxial layer 30 may be formed only in the active device region. Accordingly, when a plurality of semiconductor devices are formed on the epi layer 30 of the substrate 10, a device separation process for electrically separating the semiconductor devices may not be required. That is, the manufacturing process of the semiconductor device can be simplified.

12 and 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 12, after the third mask pattern M3 is removed on the result of FIG. 7, the epi layer 30 may be formed in the first hole H1 and the second hole H2. The epitaxial layer 30 may include a buffer layer 31, an ohmic contact layer 32, a drift layer 33, a channel layer 34, and a barrier layer 35. For example, the buffer layer 31 may be formed using a selective epitaxial growth (SEG) process using one surface 11a of the first semiconductor layer 11 exposed by the spacer layer 20 as a seed. . The ohmic contact layer 32, the drift layer 33, the channel layer 34, and the barrier layer 35 may be sequentially formed on the buffer layer 31 using a selective epitaxial growth (SEG) process. . At this time, the drift layer 33 may be formed so that its upper surface has a lower level than the upper surface of the insulating layer 12, and the channel layer 34 is grown from the upper surface of the drift layer 33 so that the upper surface thereof is an insulating layer ( It can be formed to have a higher level than 12).

Referring to FIG. 13, gate electrodes 41 and source electrodes 42 may be formed on the upper surface of the barrier layer 35. For example, after patterning for fabrication of the gate electrode 41 and the source electrode 42 is formed on the upper surface of the barrier layer 35, a metal multilayer is deposited and a lift-off process is performed. The electrode 41 and source electrodes 42 may be formed.

Thereafter, a carrier substrate 50 may be provided on the substrate 10. The carrier substrate 50 may cover the barrier layer 35, the gate electrode 41, and the source electrodes 42 on the second semiconductor layer 13.

Referring again to FIG. 2, a third hole H3 may be formed in the substrate 10. The third hole H3 may pass through the first semiconductor layer 11 and be connected to the second hole H2. During the etching process of the first semiconductor layer 11, the buffer layer 31 may be etched together.

A drain electrode 60 may be formed under the substrate 10. For example, the drain electrode 60 may be formed by applying a metal film to conformally cover the lower surface of the first semiconductor layer 11 and the inner surfaces and the bottom surface of the third hole H3. .

Thereafter, the carrier substrate 50 is removed, so that the semiconductor device described with reference to FIG. 2 may be manufactured.

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features. You can understand that there is. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting.

10: substrate 11: first semiconductor layer
12: insulating layer 13: second semiconductor layer
20: spacer film 30: epi layer
31: buffer layer 32: ohmic contact layer
33: drift layer 34: channel layer
35: barrier layer 41: gate electrode
42: source electrode 50: carrier substrate
60: drain electrode

Claims (15)

A substrate in which an insulating layer is buried between the first semiconductor layer and the second semiconductor layer;
A through hole penetrating the substrate, the through hole includes a first hole penetrating the first semiconductor layer, and a second hole penetrating the insulating layer and the second semiconductor layer from a bottom surface of the first hole, ;
An epi layer disposed in the through hole, a lower surface of the epi layer is disposed at a lower level than the insulating layer, and an upper surface of the epi layer is disposed at a higher level than the insulating layer;
A drain electrode disposed in the second hole and in contact with one surface of the epi layer; And
A semiconductor device including a source electrode and a gate electrode disposed on the other surface of the epi layer.
delete A substrate in which an insulating layer is buried between the first semiconductor layer and the second semiconductor layer;
A through hole penetrating the substrate, the through hole includes a first hole penetrating the first semiconductor layer, and a second hole penetrating the insulating layer and the second semiconductor layer from a bottom surface of the first hole, ;
An epi layer disposed in the through hole;
A drain electrode disposed in the second hole and in contact with one surface of the epi layer; And
Including a source electrode and a gate electrode disposed on the other side of the epi layer,
The epi layer includes an ohmic contact layer, a drift layer, a channel layer, and a barrier layer sequentially stacked from the drain electrode. The method of claim 3,
The drift layer is disposed on the boundary between the first hole and the second hole,
The upper surface of the drift layer is located at a higher level than the insulating layer,
A semiconductor device in which a lower surface of the drift layer is positioned at a lower level than that of the insulating layer. The method of claim 3,
The channel layer is disposed on a boundary between the first hole and the second hole,
The upper surface of the channel layer is located at a higher level than the insulating layer,
A semiconductor device having a lower surface of the channel layer positioned at a lower level than the insulating layer. The method of claim 3,
The barrier layer includes AlGaN, AlN, InN, InAlN or AlGaInN,
The channel layer is a semiconductor device containing GaN. The method of claim 1,
A semiconductor device further comprising a spacer layer disposed between the epi layer and the inner wall of the through hole. The method of claim 1,
A semiconductor device in which a width of the first hole is greater than a width of the second hole. Providing a substrate in which an insulating layer is buried between the first semiconductor layer and the second semiconductor layer;
Etching the second semiconductor layer to form a first hole exposing the insulating layer;
Etching the exposed insulating layer to form a second hole extending into the first semiconductor layer;
Growing an epitaxial layer on the bottom surface of the second hole;
Forming a source electrode and a gate electrode on the upper surface of the epi layer;
Etching the first semiconductor layer to form a third hole connected to the second hole; And
And forming a drain electrode extending from one surface of the first semiconductor layer into the third hole to contact the epi layer. The method of claim 9,
Before forming the epi layer,
The method of manufacturing a semiconductor device further comprising forming a spacer layer covering the inner wall and the bottom surface of the first hole and the inner wall of the second hole. The method of claim 9,
The epi layer is a method of manufacturing a semiconductor device including a buffer layer, an ohmic contact layer, a drift layer, a channel layer, and a barrier layer sequentially stacked from a bottom surface of the second hole. The method of claim 11,
A method of manufacturing a semiconductor device in which the buffer layer is removed together during an etching process of the first semiconductor layer to form the third hole. The method of claim 11,
A method of manufacturing a semiconductor device, wherein an interface between the channel layer and the barrier layer is disposed at a level higher than that of the insulating layer. The method of claim 9,
A method of manufacturing a semiconductor device further comprising polishing the first semiconductor layer before forming the third hole. The method of claim 9,
A method of manufacturing a semiconductor device in which a width of the first hole is larger than a width of the second hole.

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