CN114695296A - Front-end metal structure of semiconductor device and manufacturing method thereof - Google Patents

Front-end metal structure of semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN114695296A
CN114695296A CN202011577547.XA CN202011577547A CN114695296A CN 114695296 A CN114695296 A CN 114695296A CN 202011577547 A CN202011577547 A CN 202011577547A CN 114695296 A CN114695296 A CN 114695296A
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layer
end metal
semiconductor device
metal structure
metal layer
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刘坚
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a front-end metal structure of a semiconductor device, wherein the semiconductor device comprises a topmost front metal layer, and a front metal electrode is formed after the topmost front metal layer is patterned; the front-end metal structure is formed by patterning a front-end metal layer formed on the surface of the topmost front-side metal layer, and the front-end metal layer is made of a weldable metal material so as to form a bonding area for packaging on the surface of the front-end metal structure; the front-end metal structure is positioned on the surface of a partial area of the front-side metal electrode, and the patterning of the front-end metal layer is positioned before the patterning of the topmost front-side metal layer; the semiconductor device further includes a front passivation layer that opens the bonding region. The invention also discloses a manufacturing method of the front-end metal structure of the semiconductor device. The invention can provide a front-end metal structure with solderability and reduce defects caused by a front-end metal structure forming process, thereby forming a bonding area for packaging and enabling the packaging of the copper sheet PDFN.

Description

Front-end metal structure of semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a front-end metal structure of a semiconductor device; the invention also relates to a manufacturing method of the front-end metal structure of the semiconductor device.
Background
With the development of new power devices, new packaging technologies have also been developed rapidly. One of the most important is a copper power dual-edge flat-no-lead (PDFN) package, which can provide very low on-resistance, parasitic resistance, and good thermal conductivity, and has better device reliability and yield compared with the conventional wire bonding package.
Therefore, it is very important how to form a front-end metal structure of a semiconductor device suitable for PDFN packaging, otherwise PDFN packaging cannot be performed well, and device performance after packaging and packaging yield cannot be improved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a front-end metal structure of a semiconductor device, which can provide the front-end metal structure with solderability and reduce the defects caused by the forming process of the front-end metal structure, thereby forming a bonding area for packaging, enabling the packaging of a copper sheet PDFN and developing a new research direction for a new packaging form of a new generation of integrated circuits in the future; meanwhile, the overall reliability and the packaging yield of the device can be improved. Therefore, the invention also provides a manufacturing method of the front-end metal structure of the semiconductor device.
In order to solve the technical problem, the semiconductor device corresponding to the front-end metal structure of the semiconductor device provided by the invention comprises a topmost front metal layer, and a front metal electrode of the semiconductor device is formed after the topmost front metal layer is patterned.
The front-end metal structure is formed by patterning a front-end metal layer formed on the surface of the topmost front-side metal layer, and the front-end metal layer is made of a weldable metal material so as to form a bonding area for packaging on the surface of the front-end metal structure;
the front-end metal structure is positioned on the surface of a partial area of the front-side metal electrode, and the patterning of the front-end metal layer is positioned before the patterning of the topmost front-side metal layer, so that the defects generated by the patterning of the front-end metal layer are reduced.
The semiconductor device further includes a front passivation layer (passivation) that opens the bonding region to expose a surface of the front metal structure of the bonding region, the front passivation layer covering an outside of the bonding region.
In a further refinement, the semiconductor device comprises a power device having a vertical channel, and the front-side metal electrode comprises a source or a gate.
In a further improvement, the material of the topmost front metal layer comprises AlCu or Al.
The further improvement is that the front-end metal layer is a superposed layer of a Ti layer, a Ni layer and an Ag layer or a superposed layer of a Ni layer, a Pd layer and an Au layer.
The further improvement is that when the front-end metal layer is a superposed layer of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100nm, the thickness of the Ni layer is 200nm, and the thickness of the Ag layer is 600 nm.
When the front-end metal layer is an overlapped layer of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100nm, the thickness of the Pd layer is 200nm, and the thickness of the Au layer is 600 nm.
In a further improvement, the material of the front passivation layer comprises: epoxy resins (epoxy), polyimides (polyimide) or nitroxides (oxynitrides).
In a further improvement, the bonding area is used for bonding with the copper sheet during packaging.
In order to solve the above technical problem, the method for manufacturing a front-end metal structure of a semiconductor device provided by the present invention comprises the following steps:
step one, forming a topmost front metal layer of the semiconductor device.
And step two, forming a front-end metal layer on the surface of the topmost front-side metal layer.
And step three, patterning the front-end metal layer to form a front-end metal structure.
The front end metal layer is composed of a solderable metal material to form a bonding area for packaging at a surface of the front end metal structure.
Fourthly, forming a front metal electrode of the semiconductor device after patterning the topmost front metal layer; the front-end metal structure is positioned on the surface of a partial area of the front-side metal electrode, and the patterning of the front-end metal layer is positioned before the patterning of the topmost front-side metal layer, so that the defects generated by the patterning of the front-end metal layer are reduced.
And fifthly, forming a front end passivation layer and patterning the front end passivation layer to open the bonding region and expose the surface of the front end metal structure of the bonding region, wherein the front end passivation layer covers the outside of the bonding region.
In a further refinement, the semiconductor device comprises a power device having a vertical channel, and the front-side metal electrode comprises a source or a gate.
The further improvement is that the patterning of the front-end metal layer is realized by adopting a photoetching definition and etching process in the third step.
And after the etching process of the front-end metal layer is finished, cleaning to remove defects generated by the etching process of the front-end metal layer.
The further improvement is that in the fourth step, the patterning of the topmost front metal layer is realized by adopting a photoetching definition and etching process.
In a further improvement, the material of the topmost front metal layer comprises AlCu or Al.
The further improvement is that the front-end metal layer is a superposed layer of a Ti layer, a Ni layer and an Ag layer or a superposed layer of a Ni layer, a Pd layer and an Au layer.
The further improvement is that when the front-end metal layer is a superposed layer of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100nm, the thickness of the Ni layer is 200nm, and the thickness of the Ag layer is 600 nm.
When the front-end metal layer is an overlapped layer of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100nm, the thickness of the Pd layer is 200nm, and the thickness of the Au layer is 600 nm.
In a further improvement, the material of the front passivation layer comprises: epoxy, polyimide, or oxynitride.
In a further improvement, the bonding area is used for bonding with the copper sheet during packaging.
The front-end metal structure of the semiconductor device is made of weldable metal materials and is arranged on the surface of the topmost front metal layer, and the patterning process for forming the front-end metal structure is arranged before the patterning of the topmost front metal layer, so that a bonding area can be formed on the surface of the front-end metal structure, the defects caused by the patterning for forming the front-end metal structure can be eliminated, and the bonding area for packaging can be formed finally, so that the packaging of the copper sheet PDFN becomes possible, and a new research direction is developed for a new packaging form of a new generation of integrated circuits in the future; the invention can also improve the overall reliability and the packaging yield of the device.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a front-end metal structure of a semiconductor device in accordance with an embodiment of the present invention;
fig. 2A to 2D are schematic device structures in steps of a method for manufacturing a front-end metal structure of a semiconductor device according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a schematic diagram of a front-end metal structure of a semiconductor device according to an embodiment of the present invention; the semiconductor device corresponding to the front-end metal structure of the semiconductor device comprises a topmost front metal layer 2, and a front metal electrode of the semiconductor device is formed after the topmost front metal layer 2 is patterned.
The front-end metal structure is formed by patterning a front-end metal layer formed on the surface of the topmost front-side metal layer 2, and the front-end metal layer is composed of a solderable metal material so as to form a bonding area for packaging on the surface of the front-end metal structure.
The front-end metal structure is positioned on the surface of a partial area of the front-side metal electrode, and the patterning of the front-end metal layer is positioned before the patterning of the topmost front-side metal layer 2, so that the defects generated by the patterning of the front-end metal layer are reduced.
The semiconductor device further comprises a front end passivation layer 6, the front end passivation layer 6 opens the bonding region to expose the surface of the front end metal structure of the bonding region, and the front end passivation layer 6 covers the outside of the bonding region.
In the embodiment of the present invention, the semiconductor device is formed on the semiconductor substrate 1. The semiconductor substrate 1 includes a silicon substrate.
The semiconductor device comprises a power device, the semiconductor device is provided with a vertical channel, a source region is formed in the surface region of the front surface of the semiconductor substrate 1, and a gate structure formed by overlapping a gate dielectric layer and a gate conductive material layer is formed on the surface of the front surface of the semiconductor substrate 1. The front metal electrode comprises a source electrode or a grid electrode. The gate dielectric layer comprises a gate oxide layer, and the gate conductive material layer comprises a polysilicon gate.
The source electrode is connected with the source region, and the grid electrode is connected with the grid electrode conducting material layer. The power device is a power MOSFET, a drain region is further formed on the back surface of the semiconductor substrate 1, and the drain electrode is composed of a back metal layer formed on the back surface of the drain region.
The material of the topmost front metal layer 2 comprises AlCu or Al.
In the embodiment of the invention, the front-end metal layer is a superposed layer of a Ti layer 3, a Ni layer 4 and an Ag layer 5; the thickness of the Ti layer 3 is 100nm, the thickness of the Ni layer 4 is 200nm, and the thickness of the Ag layer 5 is 600 nm.
In other embodiments can also be: the front-end metal layer is a superposed layer of a Ni layer, a Pd layer and an Au layer; the thickness of the Ni layer is 100nm, the thickness of the Pd layer is 200nm, and the thickness of the Au layer is 600 nm.
The material of the front passivation layer 6 includes: epoxy, polyimide, or oxynitride.
The bonding area is used for bonding with the copper sheet during packaging. In fig. 1, the exposed area of the front passivation layer 6 is the bonding area, and the size of the bonding area matches the size of the copper sheet to be bonded in a top view, and the bonding area can be bonded by welding such as soldering.
The front-end metal structure of the semiconductor device is made of weldable metal materials and is arranged on the surface of the topmost front metal layer 2, and the patterning process for forming the front-end metal structure is arranged before the patterning of the topmost front metal layer 2, so that a bonding area can be formed on the surface of the front-end metal structure, defects caused by the patterning for forming the front-end metal structure can be eliminated, and a bonding area for packaging can be formed finally, so that the packaging of the copper sheet PDFN becomes possible, and a new research direction is developed for a new packaging form of a new generation of integrated circuits in the future; the embodiment of the invention can also improve the overall reliability and the packaging yield of the device.
Fig. 2A to 2D are schematic diagrams of device structures in steps of a method for manufacturing a front-end metal structure of a semiconductor device according to an embodiment of the present invention; the manufacturing method of the front-end metal structure of the semiconductor device comprises the following steps:
step one, as shown in fig. 2A, a topmost front metal layer 2 of the semiconductor device is formed.
In the embodiment of the present invention, the semiconductor device is formed on the semiconductor substrate 1. The semiconductor substrate 1 includes a silicon substrate.
The semiconductor device comprises a power device, the semiconductor device is provided with a vertical channel, a source region is formed in the surface region of the front surface of the semiconductor substrate 1, and a gate structure formed by overlapping a gate dielectric layer and a gate conductive material layer is formed on the surface of the front surface of the semiconductor substrate 1.
The gate dielectric layer comprises a gate oxide layer, and the gate conductive material layer comprises a polysilicon gate.
The material of the topmost front metal layer 2 comprises AlCu or Al.
Step two, as shown in fig. 2B, a front end metal layer is formed on the surface of the topmost front metal layer 2.
In the method of the embodiment of the invention, the front-end metal layer is a superposed layer of a Ti layer 3, a Ni layer 4 and an Ag layer 5; the thickness of the Ti layer 3 is 100nm, the thickness of the Ni layer 4 is 200nm, and the thickness of the Ag layer 5 is 600 nm.
In other embodiments the method can also be: the front-end metal layer is a superposed layer of a Ni layer, a Pd layer and an Au layer; the thickness of the Ni layer is 100nm, the thickness of the Pd layer is 200nm, and the thickness of the Au layer is 600 nm.
And step three, as shown in fig. 2C, patterning the front-end metal layer to form a front-end metal structure.
In the method of the embodiment of the invention, the patterning of the front-end metal layer is realized by adopting a photoetching definition and etching process.
And after the etching process of the front-end metal layer is finished, cleaning to remove defects generated by the etching process of the front-end metal layer.
The front end metal layer is composed of a solderable metal material to form a bonding area for packaging at a surface of the front end metal structure.
Step four, as shown in fig. 2D, patterning the topmost front metal layer 2 to form a front metal electrode of the semiconductor device; the front-end metal structure is positioned on the surface of a partial area of the front-side metal electrode, and the patterning of the front-end metal layer is positioned before the patterning of the topmost front-side metal layer 2, so that the defects generated by the patterning of the front-end metal layer are reduced.
The front metal electrode comprises a source electrode or a grid electrode. The source electrode is connected with the source region, and the grid electrode is connected with the grid electrode conducting material layer.
In the method of the embodiment of the invention, the patterning of the topmost front metal layer 2 is realized by adopting a photoetching definition and etching process.
Step five, as shown in fig. 1, forming a front passivation layer 6 and patterning the front passivation layer 6 to open the bonding region and thereby expose the surface of the front metal structure of the bonding region, wherein the front passivation layer 6 covers the outside of the bonding region.
In the method of the embodiment of the present invention, the material of the front passivation layer 6 includes: epoxy, polyimide, or oxynitride.
The bonding area is used for bonding with the copper sheet during packaging.
In fig. 1, the exposed area of the front passivation layer 6 is the bonding area, and the size of the bonding area matches the size of the copper sheet to be bonded in a top view, and the bonding area can be bonded by welding such as soldering.
The method of the embodiment of the invention realizes the manufacture of the front-end metal structure by 2 times of photoetching: the method comprises the steps of photoetching a front-end metal layer and photoetching a topmost front-side metal layer 2; the method provided by the embodiment of the invention can form a solderable front-end metal structure, so that the front-end metal structure formed by the method provided by the embodiment of the invention enables the packaging of the copper sheet PDFN, and a new research direction is developed for a new packaging form of a new generation of integrated circuits in the future.
In addition, the process of the method of the embodiment of the invention adopts the technology of firstly carrying out photoetching and etching on the front-end metal layer and then carrying out photoetching and etching on the topmost front metal layer 2, which is different from the existing common front-end metal process, so that the defects generated in the etching process of the front-end metal layer of the device are greatly reduced, and the stability and the high reliability of the device are improved. The most front end passivation of the device is the front end passivation layer 6, so that other parts of the whole device can be protected in the process of placing soldering tin, and the reliability of the whole device is improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (16)

1. A front-end metal structure of a semiconductor device, characterized in that: the semiconductor device comprises a topmost front metal layer, and a front metal electrode of the semiconductor device is formed after the topmost front metal layer is patterned;
the front-end metal structure is formed by patterning a front-end metal layer formed on the surface of the topmost front-side metal layer, and the front-end metal layer is composed of a weldable metal material so as to form a bonding area for packaging on the surface of the front-end metal structure;
the front-end metal structure is positioned on the surface of a partial area of the front-side metal electrode, and the patterning of the front-end metal layer is positioned before the patterning of the topmost front-side metal layer so as to reduce the defects generated by the patterning of the front-end metal layer;
the semiconductor device further comprises a front end passivation layer, wherein the bonding region is opened by the front end passivation layer so as to expose the surface of the front end metal structure of the bonding region, and the front end passivation layer covers the outside of the bonding region.
2. The front-end metal structure of a semiconductor device of claim 1, wherein: the semiconductor device comprises a power device, the semiconductor device is provided with a vertical channel, and the front metal electrode comprises a source electrode or a grid electrode.
3. The front-end metal structure of a semiconductor device of claim 1, wherein: the material of the topmost front metal layer comprises AlCu or Al.
4. The front-end metal structure of a semiconductor device of claim 1, wherein: the front-end metal layer is a superposed layer of a Ti layer, a Ni layer and an Ag layer or a superposed layer of a Ni layer, a Pd layer and an Au layer.
5. The front-end metal structure of a semiconductor device of claim 4, wherein: when the front-end metal layer is a superposed layer of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100nm, the thickness of the Ni layer is 200nm, and the thickness of the Ag layer is 600 nm;
when the front-end metal layer is an overlapped layer of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100nm, the thickness of the Pd layer is 200nm, and the thickness of the Au layer is 600 nm.
6. The front-end metal structure of a semiconductor device of claim 1, wherein: the material of the front passivation layer comprises: epoxy, polyimide, or oxynitride.
7. The front-end metal structure of a semiconductor device of claim 1, wherein: the bonding area is used for bonding with the copper sheet during packaging.
8. A method for manufacturing a front-end metal structure of a semiconductor device is characterized by comprising the following steps:
step one, forming a topmost front metal layer of a semiconductor device;
secondly, forming a front-end metal layer on the surface of the topmost front-side metal layer;
step three, patterning the front-end metal layer to form a front-end metal structure;
the front end metal layer is composed of a solderable metal material to form a bonding area for packaging on the surface of the front end metal structure;
fourthly, forming a front metal electrode of the semiconductor device after patterning the topmost front metal layer; the front-end metal structure is positioned on the surface of a partial area of the front-side metal electrode, and the patterning of the front-end metal layer is positioned before the patterning of the topmost front-side metal layer so as to reduce the defects generated by the patterning of the front-end metal layer;
and fifthly, forming a front end passivation layer and patterning the front end passivation layer to open the bonding region and expose the surface of the front end metal structure of the bonding region, wherein the front end passivation layer covers the outside of the bonding region.
9. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 8, characterized by: the semiconductor device includes a power device;
the semiconductor device has a vertical channel, and the front metal electrode comprises a source electrode or a grid electrode.
10. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 8, characterized by: in the third step, the patterning of the front-end metal layer is realized by adopting a photoetching definition and etching process;
and after the etching process of the front-end metal layer is finished, cleaning to remove defects generated by the etching process of the front-end metal layer.
11. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 10, characterized by: and step four, realizing the patterning of the topmost front metal layer by adopting a photoetching definition and etching process.
12. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 8, characterized by: the material of the topmost front metal layer comprises AlCu or Al.
13. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 1, characterized by: the front-end metal layer is a superposed layer of a Ti layer, a Ni layer and an Ag layer or a superposed layer of a Ni layer, a Pd layer and an Au layer.
14. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 13, wherein: when the front-end metal layer is a superposed layer of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100nm, the thickness of the Ni layer is 200nm, and the thickness of the Ag layer is 600 nm;
when the front-end metal layer is an overlapped layer of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100nm, the thickness of the Pd layer is 200nm, and the thickness of the Au layer is 600 nm.
15. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 8, characterized by: the front passivation layer comprises the following materials: epoxy, polyimide, or oxynitride.
16. A method of fabricating a front-end metal structure of a semiconductor device as claimed in claim 8, characterized by: the bonding area is used for bonding with the copper sheet during packaging.
CN202011577547.XA 2020-12-28 2020-12-28 Front-end metal structure of semiconductor device and manufacturing method thereof Pending CN114695296A (en)

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Application Number Priority Date Filing Date Title
CN202011577547.XA CN114695296A (en) 2020-12-28 2020-12-28 Front-end metal structure of semiconductor device and manufacturing method thereof

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