CN114695285A

CN114695285A - Semiconductor package and method of manufacturing the same

Info

Publication number: CN114695285A
Application number: CN202011604294.0A
Authority: CN
Inventors: 黄馨禾
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2022-07-01

Abstract

The present disclosure provides a semiconductor device, including: a semiconductor die having a first surface and a second surface opposite the first surface; a plurality of first real conductive pillars located in a first area on the first surface; and a plurality of supports located in a second region adjacent to the first region. The area density of the plurality of supports in the second region is in a range of about 50% to about 100% of the area density of the plurality of first real conductive pillars in the first region. Also disclosed in the present disclosure is a method for manufacturing a semiconductor package including the semiconductor device.

Description

Semiconductor package and method of manufacturing the same

Technical Field

The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a semiconductor die having dense connection regions and sparse connection regions.

Background

To accommodate the development of mobile communication devices, reduction in volume (e.g., thinning), reduction in manufacturing cost, flexibility in function, and speeding up of product cycle time are essential for device packaging.

Grinding is a well-known method of reducing package thickness in semiconductor packaging. Generally, for a semiconductor die having an active surface provided with a plurality of conductive pillars, a tape is attached to the active surface and covers the plurality of conductive pillars. Due to the flexible nature of the strip, the bottom of the strip may deform according to the profile of the underlying conductive posts, while the top of the strip is substantially flat.

Disclosure of Invention

In some embodiments, the present disclosure provides a semiconductor device comprising: a semiconductor die having a first surface and a second surface opposite the first surface; a plurality of first real conductive pillars located in a first area on the first surface; and a plurality of supports in a second region adjacent to the first region. The area density of the plurality of supports in the second region is in a range of about 50% to about 100% of the area density of the plurality of first real conductive pillars in the first region.

In some embodiments, the present disclosure provides a semiconductor package comprising: a first semiconductor die having a first surface and a second surface opposite the first surface; a plurality of first real conductive pillars located in a first dense area on the first surface; a plurality of second real conductive pillars located in a second dense area on the first surface; a plurality of supports located in a sparse region between the first dense region and the second dense region; a second semiconductor die located over the first semiconductor die; and a third semiconductor die located over the first semiconductor die.

In some embodiments, the present disclosure provides a method for manufacturing a semiconductor package, the method comprising: forming a plurality of first real conductive pillars in a first region of a first surface of a semiconductor die; introducing a deformation prevention member at a second region of the first surface, the second region being adjacent to the first region; securing the semiconductor die by providing suction at the first surface; and thinning the semiconductor die at a second surface opposite the first surface.

Drawings

Aspects of the present disclosure may be readily understood by the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates a top view of a semiconductor die in a semiconductor package according to some comparative embodiments.

Fig. 2 illustrates a top view of a semiconductor die in a semiconductor package according to some embodiments of the present disclosure.

Fig. 3 illustrates a top view of a semiconductor die in a semiconductor package according to some embodiments of the present disclosure.

Fig. 4 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

Fig. 5A, 5B, and 5C illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure.

Fig. 5A ', 5B ', and 5C ' illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure.

Fig. 5A ", 5B", and 5C "illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure.

Fig. 5D and 5E illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure.

Fig. 5D 'and 5E' illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure.

Fig. 6A shows a cross-sectional view of a semiconductor die according to some embodiments of the present disclosure.

Fig. 6B shows a cross-sectional view of a semiconductor package including the semiconductor die of fig. 6A.

Fig. 7A shows a cross-sectional view of a semiconductor die according to some embodiments of the present disclosure.

Fig. 7B shows a cross-sectional view of a semiconductor package containing the semiconductor die of fig. 7A.

Detailed Description

The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions, such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "above," "below," and the like, are specified with respect to a particular component or group of components, or a particular plane of a component or group of components, or with respect to an orientation of a component, as shown in the associated figures. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual embodiments of the structures described herein may be spatially arranged in any orientation or manner without departing from the advantages of the embodiments of the present disclosure.

With reference to a semiconductor die having an active surface attached to a flexible tape, when dense regions (having a greater volumetric density of conductive pillars per unit volume) and sparse regions (having a lesser or even zero volumetric density of conductive pillars per unit volume) are present on the active surface of the semiconductor die, the top surface of the tape (tape) may not continue to maintain a flat topography over the dense and sparse regions. In fact, a step height difference at the top surface of the belt may be generated at the boundary of the dense area and the sparse area. From a macroscopic perspective, a recess is formed over the sparse region because a large number of straps are used to fill the gaps in the sparse region, and a small number of straps are used to fill the gaps between the conductive pillars in the dense region.

In a subsequent backgrinding operation, the tape is brought into contact with a chuck table to apply vacuum suction to the semiconductor die at the side of the tape. During the thinning process, when the semiconductor die is greater than 100 μm thick, the vacuum suction may not create a mechanical impact sufficient to deform the semiconductor die at the regions adjacent to the recesses of the tape. However, when the thickness of the semiconductor die is less than 100 μm, the vacuum suction may create a mechanical impact sufficient to deform the semiconductor die at the region adjacent to the recess of the tape.

When the semiconductor die at the area adjacent to the recessed portion of the tape (that is, at the sparse area) exhibits deformation, then exposing the conductive pillars in the dense area and, if any, the conductive pillars in the sparse area by a molding compound planarization operation may cause the Total Thickness Variation (TTV) of all the conductive pillars to be greater than 7 μm. The aforementioned TTV may exceed the process error window of the molding compound planarization operation and may result in some conductive pillars, if any, in the sparse region being nearly removed.

The present disclosure provides a semiconductor package structure implementing a plurality of supports in sparse regions. The additional support may prevent the formation of recesses on the tape in sparse areas and may reduce the impact of deformation of the semiconductor die that results in high TTV.

The present disclosure provides a method for fabricating such a semiconductor package structure implementing multiple supports in sparse regions.

The present disclosure provides a method for fabricating a semiconductor structure that is immune to high TTV problems due to semiconductor die deformation at the back side grinding stage. For example, mechanical supports designed at the chuck table providing vacuum suction may be implemented to prevent deformation. For another example, a protrusion designed at the chuck table to eliminate a recess on the tape above the sparse region may be implemented to prevent deformation.

Referring to fig. 1, fig. 1 illustrates a top view of a semiconductor die 100 in a semiconductor package according to some comparative embodiments. Fig. 1 shows an active surface of a semiconductor die 100, wherein the active surface includes a dense region 100H, a dense region 100H ', and a sparse region 100L between the dense region 100H and the dense region 100H'. A plurality of conductive pillars 100HR are provided in the dense region 100H, and a plurality of conductive pillars 100HR 'are provided in the dense region 100H'. In some comparative embodiments, conductive pillars 100HR and 100HR' are electrically coupled at one end to a conductive trace near the active surface of semiconductor die 100 and/or at the other end to another conductive routing layer, such as a redistribution layer (RDL). In other words, the conductive pillars 100HR and 100HR' are real conductive pillars used for the purpose of making electrical connection in a semiconductor package incorporating the semiconductor die 100. It can be observed that the area density of conductive pillars 100HR in dense region 100H is greater than the area density of conductive pillars (if any) in sparse region 100L. In some comparative embodiments, the bulk density of conductive pillars 100HR in dense region 100H is greater than the bulk density of conductive pillars (if any) in sparse region 100L when considering the height of each of conductive pillars 100HR, 100 HR'. In some comparative embodiments, conductive pillars 100HR and 100HR' may be copper pillars, copper posts, copper bumps, and the like, regardless of the particular size, aspect ratio, and shape.

Referring to fig. 2, fig. 2 illustrates a top view of a semiconductor die 201 in a semiconductor package according to some embodiments of the present disclosure. Fig. 2 shows an active surface of a semiconductor die 201, where the active surface includes dense regions 101H (enclosed by dashed lines), dense regions 101H '(enclosed by dashed lines), and sparse regions 101L (enclosed by dashed lines) between dense regions 101H and dense regions 101H'. A plurality of conductive pillars 101HR are provided in the dense region 101H, and a plurality of conductive pillars 101HR' are provided in the dense region 101H. A plurality of supports 101LS are provided in the sparse region 101L.

In some embodiments, conductive pillars 101HR and 101HR' are electrically coupled at one end to a conductive trace near the active surface of semiconductor die 201, and/or at the other end to another conductive routing layer, e.g., a redistribution layer (RDL). In other words, the conductive pillars 101HR and 101HR' are real conductive pillars used for the purpose of making electrical connection in a semiconductor package incorporating the semiconductor die 201. At one end, support 101LS may be disposed on conductive pads, which may or may not be coupled to conductive traces near the active surface of semiconductor die 201. At the other end, support 101LS may not be electrically coupled to another conductive routing layer, e.g., a redistribution layer (RDL). In other words, the supports 101LS may contain dummy conductive pillars that are not used for the purpose of making electrical connections in a semiconductor package incorporating the semiconductor die 101A. In some embodiments, supports 101LS may include both real and dummy conductive pillars.

It can be observed that the area density of conductive pillars 101HR in dense region 100H is greater than the area density of supports 101LS in sparse region 101L. In some embodiments, the bulk density of conductive pillars 101HR in dense region 101H is greater than the bulk density of supports 101LS in sparse region 101L when considering the height of each of conductive pillars 101HR and supports 101 LD. In some embodiments, conductive pillars 101HR and supports 101LS may be copper pillars, copper posts, copper bumps, or the like, regardless of the particular size, aspect ratio, and shape. Similarly, the area density of conductive pillars 101HR 'in dense region 100H' is greater than the area density of supports 101LS in sparse region 101L. The bulk density of conductive pillars 101HR 'in the dense region 101H' is greater than the bulk density of the supports 101LS in the sparse region 101L.

As shown in fig. 2, from a top view perspective, supports 101LS in sparse region 101L of semiconductor die 201 have the same shape, e.g., circular shape, as conductive pillars 101HR and 101HR 'in

dense regions

101H, 101H'. In some embodiments, when all of the conductive pillars 101HR, 101HR' and supports 101LS are formed on the active surface of semiconductor die 101A, an optical inspection may be performed to filter semiconductor die having defective conductive pillars (e.g., tilted pillars or broken pillars). When a defective conductive pillar is identified as one of the dummy supports 101LS, the semiconductor die may not contribute to yield loss.

Fig. 3 illustrates a top view of a semiconductor die 301 in a semiconductor package according to some embodiments of the present disclosure. Fig. 3 shows an active surface of a semiconductor die 301, wherein the active surface includes a dense region 101H (enclosed by dashed lines), a dense region 101H '(enclosed by dashed lines), and a sparse region 101L (enclosed by dashed lines) between the dense region 101H and the dense region 101H'. A plurality of conductive pillars 101HR are provided in the dense region 101H. A plurality of conductive pillars 101HR 'are provided in the dense region 101H'. A plurality of supports 101LS are provided in the sparse region 101L.

In some embodiments, conductive pillars 101HR and 101HR' are electrically coupled at one end to a conductive trace near the active surface of semiconductor die 301 and/or at the other end to another conductive routing layer, e.g., a redistribution layer (RDL). In other words, the conductive pillars 101HR and 101HR' are real conductive pillars used for the purpose of making electrical connection in a semiconductor package incorporating the semiconductor die 301. At one end, support 101LS may be disposed on conductive pads that may or may not be coupled to conductive traces near the active surface of semiconductor die 301. At the other end, support 101LS may not be electrically coupled to another conductive routing layer, e.g., a redistribution layer (RDL). In other words, the supports 101LS may be dummy conductive pillars that do not serve the purpose of making electrical connections in a semiconductor package incorporating the semiconductor die 101B. In some embodiments, supports 101LS may include both real and dummy conductive pillars.

It can be observed that the area density of conductive pillars 101HR in dense region 100H is greater than the area density of supports 101LS in sparse region 101L. In some embodiments, the bulk density of conductive pillars 101HR in dense regions 101H is greater than the bulk density of supports 101LS in sparse regions 101L when considering the height of each of conductive pillars 101HR and supports 101 LS. In some embodiments, conductive pillars 101HR and supports 101LS may be copper pillars, copper posts, copper bumps, or the like, regardless of the particular size, aspect ratio, and shape. Similarly, the area density of conductive pillars 101HR 'in dense region 100H' is greater than the area density of supports 101LS in sparse region 101L. The bulk density of conductive pillars 101HR 'in dense region 101H' is greater than the bulk density of supports 101LS in sparse region 101L.

As shown in fig. 3, from a top view perspective, supports 101LS in sparse region 101L of semiconductor die 301 have a different shape (e.g., triangular shape) than the shape (e.g., circular shape) of conductive pillars 101HR in dense region 101H. In some embodiments, the shape of supports 101LS in sparse region 101L is different from the shape of conductive pillars 101HR in dense region 101H. In some embodiments, when all conductive pillars 101HR, 101HR' and supports 101LS are formed on the active surface of semiconductor die 301, an optical inspection may be performed to filter semiconductor die having defective conductive pillars (e.g., tilted pillars or broken pillars). When a defective conductive pillar is identified as one of the supports 101LS, the semiconductor die may not contribute to yield loss. The support 101LS illustrated in fig. 3 may facilitate the above-described identification process, as the triangular shape shown in the inspection may indicate the support 101LS, and the circular shape may indicate the true conductive pillar 101HR or 101 HR'.

Fig. 4 illustrates a cross-sectional view of a semiconductor package 400 according to some embodiments of the present disclosure. The semiconductor package 400 includes a semiconductor die 401 having an active surface 401A and a passive surface 401B opposite the active surface 401A. Active surface 401A has at least dense region 401H, dense region 401H', and sparse region 401L, wherein the area density of the plurality of true conductive pillars 401HR in dense region 401H is greater than the area density of supports 401LS in sparse region 401L. In the sparse region 401L of the active surface 401A, a plurality of supports 401LS are disposed therein. Although not shown in fig. 4, the active surface 401A of the semiconductor die 401 may include a conductive routing layer (e.g., RDL) that is electrically connected to the active area in the semiconductor die 401 and the plurality of true conductive pillars 401HR, 401 HR'.

In view of the volume (e.g., projected area and height) of each of real conductive pillars 401HR, 401HR' and supports 401LS, supports 401LS in sparse region 401L may have a first volume density (e.g., volume of supports 401LS per unit volume in sparse region 401L). On the other hand, the true conductive pillars 401HR or 401HR 'in the

dense region

401H or 401H' may have a second volume density (e.g., the volume per unit volume of the true conductive pillars 401HR or 401HR 'in the

dense region

401H or 401H'). In some embodiments, the first bulk density may be equal to or less than the second bulk density. In some embodiments, the first bulk density is at least about 50% of the second bulk density. In some embodiments, the first bulk density is in a range from about 50% to about 100% of the second bulk density. As previously described, the presence of supports 401LS in the sparse regions 401L having the aforementioned volume density may effectively reduce the TTV of all conductive pillars 401HR, 401HR' and supports 401LS on the active surface 401A of the semiconductor die 401 in the semiconductor package 400.

In view of the area (e.g., projected area and height) of each of the real conductive pillars 401HR, 401HR' and supports 401LS, supports 401LS in sparse region 401L may have a first areal density (e.g., projected area of supports 401LS per unit area in sparse region 401L). On the other hand, the real conductive pillars 401HR or 401HR ' in the

dense region

401H or 401H ' may have a second area density (e.g., the area of the real conductive pillars 401HR or 401H ' per unit area in the dense region 401H). In some embodiments, the first areal density may be equal to or less than the second areal density. In some embodiments, the first areal density is at least about 50% of the second areal density. In some embodiments, the first areal density is in a range from about 50% to about 100% of the second areal density. As previously described, the presence of supports 401LS in the sparse regions 401L having the aforementioned area density may effectively reduce the TTV of all conductive pillars 401HR, 401HR' and supports 401LS on the active surface 401A of the semiconductor die 401 in the semiconductor package 400.

Still referring to fig. 4, the semiconductor package 400 further includes an encapsulant 105 surrounding the plurality of real conductive pillars 401HR or 401HR 'in the

dense regions

401H or 401H', and the plurality of supports 401LS in the sparse regions 401L. As shown in fig. 4, all conductive pillars 401HR, 401HR' and supports 401LS on the active surface 401A may have the same height. The top of support 401LS may be in contact (e.g., RDL) with conductive routing layer 403 adjacent to active surface 401A of semiconductor die 401, but not electrically connected with conductive traces or pads of conductive routing layer 403. In addition to conductive routing layer 403, semiconductor package 400 further includes a conductive routing layer 402 (e.g., RDL) adjacent to passive surface 401B of semiconductor die 401. Conductive routing layer 402 may be electrically connected to active surface 401A of semiconductor die 401 via vias 103 in encapsulant 105 and any of the true conductive pillars 401HR, 401HR of

dense regions

401H, 401H', and supports 401LS of sparse region 401L, respectively.

Still referring to fig. 4, the semiconductor package 400 further includes a semiconductor die 200 located above the conductive routing layer 403 and partially overlapping a portion of the semiconductor die 401. The semiconductor die 200 has an active surface 200A and a passive surface 200B opposite the active surface 200A. In some embodiments, the semiconductor die 200 has a plurality of conductive terminals 203 on the active surface 200A that are electrically connected with the semiconductor die 401. In some embodiments, the plurality of conductive terminals 203 of the semiconductor die 200 overlap and are electrically connected with the plurality of real conductive pillars 401HR in the dense region 401H of the semiconductor die 401. In other words, the plurality of supports 401LS in the sparse region 401L of the semiconductor die 401 may or may not be electrically connected with the semiconductor die 200, but the supports 401LS in the sparse region 401L may partially overlap with the semiconductor die 200.

Still referring to fig. 4, the semiconductor package 400 further includes a semiconductor die 300 located above the conductive routing layer 403 and partially overlapping a portion of the semiconductor die 401. The semiconductor die 300 has an active surface 300A and a passive surface 300B opposite the active surface 300A. In some embodiments, the semiconductor die 300 has a plurality of conductive terminals 303 on the active surface 300A that are electrically connected with the semiconductor die 401. In some embodiments, the plurality of conductive terminals 303 of the semiconductor die 300 overlap and are electrically connected with the plurality of real conductive pillars 401HR 'in the dense region 401H' of the semiconductor die 401. In other words, the plurality of supports 401LS in sparse region 401L of semiconductor die 401 may or may not be electrically connected with semiconductor die 300, but supports 401LS in sparse region 401L may partially overlap with semiconductor die 300.

Still referring to fig. 4, semiconductor package 400 further includes a substrate 404 that carries semiconductor die 401, semiconductor die 200, and semiconductor die 300. The conductive terminals 405' on the top surface of the substrate 404 are smaller in size than the conductive terminals 405 on the bottom surface of the substrate 404. In some embodiments, the conductive terminals 203 on the active surface 200A of the semiconductor die 200 are smaller in size than the conductive terminals 405' on the top surface of the substrate 404. In some embodiments, thickness T1 of semiconductor die 401 is thinner than thickness T2 of semiconductor die 200 or thickness T3 of semiconductor die 300. In some embodiments, the thickness T1 is less than about 100 μm, for example, about 50 μm. The thickness T2 and the thickness T2' are greater than about 100 μm, for example, about 250 μm. As previously discussed, when the thickness of the semiconductor die is below 100 μm, the vacuum suction applied on the surface of the semiconductor die may create a mechanical shock sufficient to deform the semiconductor die at areas lacking mechanical support. In the present disclosure, when the support 401LS is implemented in the sparse region 401L, since a conformal interface (conformal interface) is formed between the tape covering the support 401LS and the chuck table providing vacuum suction, the deformation resistance at the sparse region 401L can be effectively increased.

Fig. 5A, 5B, and 5C illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure. In fig. 5A, a semiconductor wafer having a plurality of semiconductor die regions is provided. Fig. 5A shows a cross-sectional view of only the die area of the wafer. The semiconductor die 101 'includes a sparse region 101L at the active surface and more than one

dense regions

101H, 101H' adjacent to the sparse region 101L. The active surface of the semiconductor die 101 'includes a conductive routing layer 503 (e.g., RDL) disposed between the active area in the semiconductor die 101' and the plurality of real conductive pillars 101HR, 101HR 'in the

dense areas

101H, 101H'. In some embodiments, the plurality of real conductive pillars 101HR, 101HR' are formed by a suitable plating operation. In some embodiments, the plurality of real conductive pillars 101HR, 101HR 'are formed in a single plating operation, each of the plurality of real conductive pillars 101HR, 101HR' having approximately the same height.

A deformable layer (e.g., tape 501) is applied over the active surface of the semiconductor die 101' and covers the plurality of true conductive pillars 101HR, 101HR ' in the

dense regions

101H, 101H ' and the sparse region 101L. In some embodiments, the thickness of the tape 501 is determined to cover the top of each of the real

conductive pillars

101H, 101H'. As described previously, since a large number of strips are used to fill the gaps in the sparse region 101L and a small number of strips are used to fill the gaps between the real conductive pillars 101HR or 101HR 'in the

dense region

101H or 101H', the recessed portions 505 are formed above the sparse region 101L.

In fig. 5B, the semiconductor die 101 'is brought into contact with a chuck table 502A, which provides vacuum suction to secure the semiconductor die 101' while performing the thinning operation shown in fig. 5C. In some embodiments, the chuck table 502A includes a deformation prevention member 5020 that provides mechanical support to the sparse region 101L of the semiconductor die 101 'such that the sparse region 101L of the semiconductor die 101' does not deform in response to vacuum suction when thinned beyond a critical thickness, for example, less than 100 μm. In some embodiments, the deformation prevention member 5020 is a protrusion on the chuck table 502A, and the protrusion is designed to have a surface that conforms to the recess 505 of the band 501. In fig. 5C, a thinning operation is performed from the passive surface toward the active surface of the semiconductor die 101' to obtain a desired die thickness. In some embodiments, a Chemical Mechanical Polishing (CMP) operation is performed by grinding wheel 507 to remove a majority of the thickness of semiconductor die 101' until the remaining thickness is less than about 100 μm.

Fig. 5A ', 5B ', and 5C ' illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure. The description of fig. 5A 'and 5C' may refer to the paragraphs explained for fig. 5A and 5C and will not be repeated here for the sake of brevity. In fig. 5B ', the semiconductor die 101' is brought into contact with a chuck table 502B, which provides vacuum suction to secure the semiconductor die 101 'while performing the thinning operation shown in fig. 5C'. In some embodiments, the chuck table 502B includes a deformation prevention member 5021 that eliminates the recesses 505 of the tape 501 at the sparse regions 101L of the semiconductor die 101 'so that the sparse regions 101L of the semiconductor die 101' do not deform in response to vacuum suction when thinned beyond a critical thickness, e.g., less than 100 μm. In some embodiments, the deformation preventing member 5021 is at least one protrusion on the chuck table 502B and designed to be inserted into the band 501 to occupy a volume near the sparse region 101L. The recess 501 of the band 505 may be eliminated when the calculated volume is occupied by at least one protrusion. Therefore, as shown in fig. 5C ', when the deformation preventing member 5021 is engaged with the tape over the sparse region 101L of the semiconductor die 101', there is no gap between the tape and the chuck table 502B.

Fig. 5A ", 5B", and 5C "illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure. Fig. 5A ″ is similar to fig. 5A except that a plurality of supports 101LS are formed as deformation preventing members in the sparse region 101L. As previously described, it can be observed that the area density of the real conductive pillars 101HR in the dense region 100H is greater than the area density of the supports 101LS in the sparse region 101L. In some embodiments, the bulk density of real conductive pillars 101HR in

dense regions

101H or 101H 'is greater than the bulk density of supports 101LS in sparse regions 101L, when considering the height of each of conductive pillars 101HR, 101HR' and supports 101 LS. For example, the bulk density of supports 101LS in sparse region 101L is in a range of about 50% to about 100% of the bulk density of real conductive pillars 101HR or 101HR 'in

dense region

101H or 101H'. When the foregoing bulk density is implemented, the TTV of all the conductive pillars can be effectively reduced.

In some embodiments, the plurality of real conductive pillars 101HR, 101HR' and the support 101LS are formed by a suitable plating operation. In some embodiments, a plurality of real conductive pillars 101HR, 101HR 'and supports 101LS are formed in a single plating operation, each of the plurality of real conductive pillars 101HR, 101HR' and supports 101LS having approximately the same height, as shown in fig. 6A. In some embodiments, the plurality of real conductive pillars 101HR, 101HR 'and supports 101LS are formed in different plating operations, and thus, each of the plurality of real conductive pillars 101HR, 101HR' and supports 101LS may have a different height, as shown in fig. 7A. When tape 501 is applied over the active surface of semiconductor die 101', no recess is observed in contrast to the counterparts discussed in fig. 5A and 5A', due to the presence of support 101LS in sparse region 101L. Thus, as shown in fig. 5B "and 5C", when the semiconductor die 101' is brought into contact with the chuck table 502C, which provides vacuum suction, there is no gap between the tape 501 and the chuck table 502C. The description of fig. 5C "may refer to the paragraphs explained for fig. 5C and are not repeated here for the sake of brevity.

Fig. 5D and 5E show cross-sectional views of an intermediate product during various manufacturing operations of the semiconductor package subsequent to previously described fig. 5A, 5B, 5C and 5A ', 5B ', 5C '. After the chuck tables 502A, 502B and the

deformation prevention members

5020, 5021 are disengaged from the thinned semiconductor die 101, the recesses 505 of the tape 501 are restored as shown in fig. 5D. At the completion of the thinning operation, the thinned semiconductor die 101 has a thickness T1 of less than about 100 μm and no distortion is formed on the thinned semiconductor die 101. In fig. 5E, the tape 501 is peeled off to expose the plurality of real conductive pillars 101HR and 101 HR'.

Fig. 5D 'and 5E' show cross-sectional views of an intermediate product during various manufacturing operations of the semiconductor package subsequent to the previously described fig. 5A ", 5B", 5C ". After the chuck table 502C is disengaged from the thinned semiconductor die 101, the tape 501 has a flat surface, as shown in fig. 5D'. At the completion of the thinning operation, the thinned semiconductor die 101 has a thickness T1 of less than about 100 μm and no distortion is formed on the thinned semiconductor die 101. In fig. 5E ', tape 501 is peeled away to expose the plurality of real conductive pillars 101HR, 101HR' and the plurality of supports 101 LS. As previously discussed, supports 101LS may include dummy conductive pillars and/or real conductive pillars.

Fig. 6A shows a cross-sectional view of a semiconductor die according to some embodiments of the present disclosure. As shown in fig. 6A, the supports 101LS in the sparse region 101L have the same height. Fig. 6B shows a cross-sectional view of a semiconductor package including the semiconductor die of fig. 6A. Semiconductor die 101 is electrically connected to semiconductor die 200 and semiconductor die 300 by a plurality of real conductive pillars 101HR, 101HR' and conductive routing layer 503, e.g., RDL. In some embodiments, the semiconductor die 101 is a bridge die connecting at least two semiconductor dies 200, 300. More than one

dense region

101H, 101H' overlap with semiconductor die 200 and semiconductor die 300, respectively.

Fig. 7A shows a cross-sectional view of a semiconductor die according to some embodiments of the present disclosure. As shown in fig. 7A, the real conductive pillars 101HR, 101HR' and the supports 101LS in the sparse region 101L have different heights. The height difference 701 can be observed from a cross-sectional view. Fig. 7B shows a cross-sectional view of a semiconductor package containing the semiconductor die of fig. 7A. Semiconductor die 101 is electrically connected to semiconductor die 200 and semiconductor die 300 through a plurality of real conductive pillars 101HR, 101HR' and conductive routing layer 503 (e.g., RDL). In some embodiments, the semiconductor die 101 is a bridge die connecting at least two semiconductor dies 200, 300. More than one

dense region

As used herein, and without further definition, the terms "substantially", "largely", "approximately" and "about" are used to describe and explain minor variations. When used in conjunction with an event or condition, these terms can encompass the precise occurrence of the event or condition as well as the extreme approximation of the occurrence of the event or condition. For example, when used in conjunction with numerical values, these terms can range less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. The term "substantially coplanar" may refer to two surfaces within a micron scale positioned along the same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm positioned along the same plane.

As used herein, the singular terms "a", "an" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, providing a component "on" or "over" another component may encompass: the former component is directly on the latter component, for example, in physical contact therewith, and one or more intervening components are positioned therebetween.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not to be construed in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The drawings are not necessarily to scale. There may be a distinction between artistic renditions in this disclosure and actual devices due to manufacturing processes and tolerances. Other embodiments of the present disclosure may exist that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation.

Claims

1. A semiconductor device, comprising:

a semiconductor die having a first surface and a second surface opposite the first surface;

a plurality of first real conductive pillars located in a first area on the first surface; and

a plurality of supports located in a second region adjacent to the first region,

wherein an area density of the plurality of supports in the second region is in a range of about 50% to about 100% of an area density of the plurality of first true conductive pillars in the first region.

2. The semiconductor device of claim 1, wherein the plurality of supports comprise dummy pillars.

3. The semiconductor device of claim 1, wherein a bulk density of the plurality of supports in the second region is in a range of about 50% to about 100% of a bulk density of the plurality of first real conductive pillars in the first region.

4. The semiconductor device of claim 1, wherein from a top view perspective, a shape of each of the supports of the second region is different from a shape of each of the plurality of first real conductive pillars of the first region.

5. The semiconductor device of claim 1, wherein a height of each of the plurality of supports of the second region is lower than a height of each of the plurality of first real conductive pillars of the first region.

6. The semiconductor device of claim 1, wherein the semiconductor die is less than about 100 μm thick.

7. A semiconductor package, comprising:

a first semiconductor die having a first surface and a second surface opposite the first surface;

a plurality of first real conductive pillars located in a first dense area on the first surface;

a plurality of second real conductive pillars located in a second dense area on the first surface;

a plurality of supports located in a sparse region between the first dense region and the second dense region;

a second semiconductor die located over the first semiconductor die; and

a third semiconductor die located above the first semiconductor die.

8. The semiconductor package of claim 7, wherein the second semiconductor die overlaps the first real conductive pillars and the third semiconductor die overlaps the second real conductive pillars.

9. The semiconductor package of claim 7, wherein an area density of the plurality of supports in the sparse region is in a range of about 50% to about 100% of an area density of the plurality of first real conductive pillars in the dense region.

10. The semiconductor package of claim 7, wherein from a top view perspective, a shape of each of the plurality of supports of the sparse region is different from a shape of each of the plurality of first real conductive pillars of the dense region.

11. The semiconductor package of claim 7, wherein the first semiconductor die is a bridge die.

12. A method for manufacturing a semiconductor package, comprising:

forming a plurality of first real conductive pillars in a first area of a first surface of a semiconductor die;

introducing a deformation prevention member at a second region of the first surface, the second region being adjacent to the first region;

securing the semiconductor die by providing suction at the first surface; and

thinning the semiconductor die at a second surface opposite the first surface.

13. The method of claim 12, wherein introducing the deformation prevention member comprises: forming a plurality of supports in the second region of the first surface prior to securing the semiconductor die.

14. The method of claim 13, wherein an area density of the plurality of supports in the second region is in a range of about 50% to about 100% of an area density of the plurality of first real conductive pillars in the first region.

15. The method of claim 12, further comprising:

applying a tape at the first surface to cover the plurality of first real conductive pillars, and forming a recess on the tape over the second area before fixing the semiconductor die.

16. The method of claim 12, wherein introducing the deformation prevention member comprises: eliminating the recess by inserting at least one protrusion into the band above the second region.

17. The method of claim 12, wherein introducing the deformation prevention member comprises: mechanical support is provided by engaging projections that conform to the recesses.

18. The method according to claim 13, wherein forming the plurality of first real conductive pillars and the plurality of supports is performed in the same operation.

19. The method of claim 12, wherein thinning the semiconductor die at the second surface comprises: grinding the semiconductor die to a thickness of 100 μm or less.

20. The method of claim 12, wherein securing the semiconductor die comprises: providing vacuum suction at the first surface.