CN114695282A - Chip packaging structure and manufacturing method thereof - Google Patents

Chip packaging structure and manufacturing method thereof Download PDF

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Publication number
CN114695282A
CN114695282A CN202011584196.5A CN202011584196A CN114695282A CN 114695282 A CN114695282 A CN 114695282A CN 202011584196 A CN202011584196 A CN 202011584196A CN 114695282 A CN114695282 A CN 114695282A
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China
Prior art keywords
chip
layer
stress buffer
buffer layer
encapsulant
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CN202011584196.5A
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Chinese (zh)
Inventor
杨凯铭
彭家瑜
陈姵圻
林溥如
柯正达
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Unimicron Technology Corp
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Unimicron Technology Corp
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Priority to CN202011584196.5A priority Critical patent/CN114695282A/en
Publication of CN114695282A publication Critical patent/CN114695282A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a chip, a reconfiguration circuit layer, a welding ball, a packaging colloid and a stress buffer layer. The chip has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface. The redistribution layer is configured on the active surface of the chip. The solder balls are arranged on the reconfiguration circuit layer, and the chip is electrically connected with the solder balls through the reconfiguration circuit layer. The packaging colloid covers the active surface and the back surface of the chip, the reconfiguration circuit layer and part of the welding balls. The stress buffer layer covers at least the peripheral surface of the chip. The outer surface of the stress buffer layer is aligned with the side surface of the packaging colloid. The chip packaging structure can effectively protect the edge of the chip and increase the overall structural strength and structural reliability.

Description

Chip packaging structure and manufacturing method thereof
Technical Field
The present disclosure relates to chip packaging structures and, particularly, to a chip packaging structure and a method for fabricating the same.
Background
In the prior art, an overhang structure under an elastic material, a packaging material or a bare die can be used as an anchor to protect the edge of a chip or enhance the mechanical strength of a packaging colloid. At present, in products, the elastic material or the packaging material only protects the wafer back and the spherical surface, but cannot effectively protect the chip edge. Or, in another product, the package material is used to protect the chip edge, and although the chip failure caused by chip crack (crack) can be avoided in the reliability experiment, the reliability times and the product use time are shortened due to the difference of the thermal expansion coefficients between the package colloid and the chip.
Disclosure of Invention
The invention is directed to a chip packaging structure, which can effectively protect the edge of a chip and increase the overall structural strength and structural reliability.
The invention also relates to a manufacturing method of the chip packaging structure, which is used for manufacturing the chip packaging structure.
According to an embodiment of the invention, the chip packaging structure comprises a chip, a redistribution layer, a solder ball, a packaging colloid and a stress buffer layer. The chip has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface. The redistribution layer is configured on the active surface of the chip. The solder balls are arranged on the reconfiguration circuit layer, and the chip is electrically connected with the solder balls through the reconfiguration circuit layer. The packaging colloid covers the active surface and the back surface of the chip, the reconfiguration circuit layer and part of the solder balls. The stress buffer layer covers at least the peripheral surface of the chip. The outer surface of the stress buffer layer is aligned with the side surface of the packaging colloid.
In the chip package structure according to the embodiment of the invention, the redistribution layer includes a circuit layer and at least one conductive via. The conductive through hole is positioned between the circuit layer and the active surface of the chip. The chip is electrically connected with the circuit layer through the conductive through hole.
In the chip package structure according to the embodiment of the invention, the chip package structure further includes a surface treatment layer disposed on the redistribution layer and located between the solder balls and the redistribution layer.
In the chip package structure according to the embodiment of the invention, the encapsulant has an upper surface and a lower surface opposite to each other. The side surface is connected with the upper surface and the lower surface and comprises a first side surface and a second side surface. The stress buffer layer also extends to cover the first side surface and the upper surface, and the outer surface of the stress buffer layer is aligned with the second side surface.
In the chip package structure according to the embodiment of the invention, a first vertical distance is provided between the upper surface of the encapsulant and the active surface of the chip. A second vertical distance is formed between the lower surface of the packaging colloid and the back surface of the chip. The first vertical spacing is greater than the second vertical spacing.
In the chip package structure according to the embodiment of the invention, the height of the stress buffer layer is equal to or slightly greater than the thickness of the chip.
In the chip package structure according to the embodiment of the invention, the material of the stress buffer layer is different from the material of the encapsulant, and the material of the stress buffer layer includes Silane coupling agent polymer (Silane adhesion promoter), silicone rubber (silicone rubber), Epoxy resin (Epoxy), or photosensitive dielectric material (for example, PI, PBO, BCB, or PID).
According to an embodiment of the invention, a method for manufacturing a chip packaging structure comprises the following steps. And providing a packaging semi-finished product. The semi-finished product of the package comprises a wafer, a redistribution layer, a plurality of solder balls and a package colloid. The redistribution layer is located between the solder balls and the wafer. The encapsulant encapsulates the wafer, the redistribution layer and a portion of the solder balls. A plurality of grooves are formed in the packaging colloid. The grooves are criss-cross and extend from the upper surface of the packaging colloid and penetrate through the wafer, so that the wafer is divided into a plurality of chips. Each chip has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface. The redistribution layer is configured on the active surface of the chip. Each chip is electrically connected with each corresponding solder ball through the reconfiguration circuit layer. The packaging colloid covers the active surface and the back surface of each chip, the reconfiguration line layer and the corresponding part of the solder balls. And forming a stress buffer layer on the upper surface of the packaging colloid and extending and configuring the stress buffer layer in the groove. The stress buffer layer exposes a part of the solder balls. And performing a monomer process to cut the stress buffer layer and the packaging colloid to form a plurality of chip packaging structures separated from each other. The encapsulant has an upper surface and a lower surface opposite to each other and a side surface connecting the upper surface and the lower surface. The side surface comprises a first side surface and a second side surface. The stress buffer layer covers the first side surface and the upper surface, and the outer surface of the stress buffer layer is aligned with the second side surface.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes providing a carrier before providing the package semi-finished product, and the package semi-finished product is disposed on the carrier. Before the singulation process, the carrier is removed to expose the lower surface of the encapsulant.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the redistribution layer includes a circuit layer and at least one conductive via. The conductive through hole is positioned between the circuit layer and the active surface of the chip. The chip is electrically connected with the circuit layer through the conductive through hole.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the package semi-finished product further includes a surface treatment layer disposed on the redistribution layer and located between the solder ball and the redistribution layer.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the step of forming the stress buffer layer includes forming a stress buffer material layer on an upper surface of the encapsulant and extending into the trench, wherein the stress buffer material layer covers the solder balls. And performing a plasma etching procedure to remove part of the stress buffer material layer, thereby exposing part of the solder balls and forming the stress buffer layer.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, a first vertical distance is provided between the upper surface of the encapsulant and the active surface of the chip, a second vertical distance is provided between the lower surface of the encapsulant and the back surface of the chip, and the first vertical distance is greater than the second vertical distance.
In the method for fabricating a chip package structure according to an embodiment of the present invention, the material of the stress buffer layer is different from the material of the encapsulant, and the material of the stress buffer layer includes Silane coupling agent polymer (Silane adhesion promoter), silicone rubber (silicone rubber), Epoxy resin (Epoxy), or photosensitive dielectric material (for example, PI, PBO, BCB, or PID).
According to an embodiment of the invention, a method for manufacturing a chip packaging structure comprises the following steps. And providing a packaging semi-finished product. The semi-finished package comprises a plurality of chips, a reconfiguration circuit layer, a plurality of solder balls, a package colloid and a stress buffer layer. The chips are separated from each other, and each chip has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface. The redistributing layer is configured on the active surface of the chip. Each chip is electrically connected with each corresponding solder ball through the reconfiguration circuit layer. The packaging colloid covers the active surface and the back surface of each chip, the reconfiguration line layer, the corresponding partial solder balls and the stress buffer layer. The stress buffer layer covers the peripheral surface of each chip and the height of the stress buffer layer is equal to or slightly larger than the thickness of each chip. And performing a monomer process to cut the stress buffer layer and the packaging colloid to form a plurality of chip packaging structures separated from each other. The side surface of the packaging colloid is aligned with the outer surface of the stress buffer layer.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes providing a carrier before providing the package semi-finished product, and the package semi-finished product is disposed on the carrier. After the singulation process, the carrier is removed to expose the lower surface of the encapsulant.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the redistribution layer includes a circuit layer and at least one conductive via. The conductive through hole is positioned between the circuit layer and the active surface of the chip, and the chip is electrically connected with the circuit layer through the conductive through hole.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the package semi-finished product further includes a surface treatment layer disposed on the redistribution layer and located between the solder ball and the redistribution layer.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the encapsulant has an upper surface and a lower surface opposite to each other and a side surface connecting the upper surface and the lower surface. A first vertical interval is arranged between the upper surface of the packaging colloid and the active surface of the chip, a second vertical interval is arranged between the lower surface of the packaging colloid and the back surface of the chip, and the first vertical interval is larger than the second vertical interval.
In the method for fabricating a chip package structure according to an embodiment of the present invention, the material of the stress buffer layer is different from the material of the encapsulant, and the material of the stress buffer layer includes Silane coupling agent polymer (Silane adhesion promoter), silicone rubber (silicone rubber), Epoxy resin (Epoxy), or photosensitive dielectric material (for example, PI, PBO, BCB, or PID).
Based on the above, in the chip package structure of the present invention, the encapsulant covers the active surface and the back surface of the chip, the redistribution layer, and a portion of the solder balls, and the stress buffer layer at least covers the peripheral surface of the chip. That is, the active surface and the back surface of the chip are protected by the encapsulant, and the peripheral surface of the chip is protected by the stress buffer layer. That is, the edge of the chip is effectively protected by the arrangement of the stress buffer layer, and the structural strength of the chip packaging structure is increased by the arrangement of the packaging colloid, so that the chip packaging structure has better structural reliability.
Drawings
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention;
fig. 1G is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention;
fig. 2A to fig. 2C are schematic cross-sectional views illustrating partial steps of a method for fabricating a chip package structure according to another embodiment of the invention;
fig. 2D is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention.
Description of the reference numerals
10, a carrier plate;
100a, 100b, a chip package structure;
110, a chip;
112, an active surface;
114, a back side;
116, a peripheral surface;
120, a reconfiguration line layer;
122, a circuit layer;
124, conductive through holes;
130, solder balls;
132 a top surface;
140. 142, packaging colloid;
141, an upper surface;
143 lower surface;
145 first side surface;
147 a second side surface;
148 side surfaces;
150, surface treatment layer;
162a stress buffer material layer;
160a and 164: stress buffer layer;
167. 168, an outer surface;
b, a groove;
FA. FB, packaging the semi-finished product;
w is a wafer;
g1, first vertical spacing;
g2 second vertical spacing.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention. Fig. 1G is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention.
Regarding the manufacturing method of the chip package structure of the present embodiment, first, a carrier 10 and a package semi-finished product FA are provided, wherein the package semi-finished product FA is disposed on the carrier 10. In detail, the semi-finished package FA includes a wafer W, a redistribution layer 120, a plurality of solder balls 130, and a molding compound 142. The redistribution layer 120 is located between the solder balls 130 and the wafer W, and the encapsulant 142 encapsulates the wafer W, the redistribution layer 120, and a portion of the solder balls 130. That is, the encapsulant 142 exposes portions of the solder balls 130 to serve as contact points for external electrical connection.
Furthermore, the redistribution layer 120 of the present embodiment includes a circuit layer 122 and at least one conductive via (a plurality of conductive vias 124 are schematically illustrated), wherein the conductive via 124 is located between the circuit layer 122 and the wafer W, and the circuit layer 122 is embodied as a patterned circuit layer. Furthermore, the semi-finished package FA of the present embodiment further includes a surface treatment layer 150 disposed on the redistribution layer 120 and located between the solder balls 130 and the redistribution layer 120. The surface treatment layer 150 may be, for example, Nickel palladium Immersion Gold (ENEPIG), Organic Solderability Preservations (OSP), or Electroless Nickel Immersion Gold (ENIG), but is not limited thereto. That is, the package semi-finished product FA of the present embodiment is substantially a wafer level package, and the circuit and ball mounting process is completed.
Next, referring to fig. 1A and fig. 1B, a plurality of grooves B are formed in the molding compound 142, wherein the grooves B extend from the upper surface 141 of the molding compound 142 and penetrate through the wafer W, so that the wafer W is divided into a plurality of chips 110. That is, the wafer W is diced to form the chips 110 separated from each other. It should be noted that, when the trench B is viewed from the top view, it is criss-cross.
Here, each chip 110 has an active surface 112 and a back surface 114 opposite to each other and a peripheral surface 116 connecting the active surface 112 and the back surface 114. The redistribution layer 120 is disposed on the active surface 112 of the chip 110, and each chip 110 is electrically connected to the corresponding solder ball 130 through the redistribution layer 120. The encapsulant 142 covers the active surface 112 and the back surface 114 of each chip 110, the redistribution layer 120, and the corresponding solder balls 130.
Next, referring to fig. 1C, a stress buffer material layer 162a is formed on the upper surface 141 of the encapsulant 142 and extends into the trench B to fill the trench B. At this time, the stress buffering material layer 162a covers the top surfaces 132 of the solder balls 130 and is spaced apart from the top surfaces 132 of the solder balls 130.
Next, referring to fig. 1D, a plasma etching process is performed to remove a portion of the stress buffer material layer 162a and expose the top surface 132 of the solder ball 130 to form a stress buffer layer 164. In particular, the material of the stress buffer layer 164 of the present embodiment is different from the material of the encapsulant 142, wherein the material of the stress buffer layer 164 is, for example, a Silane coupling agent polymer (Silane coupling agent), a silicone rubber (silicone rubber), an Epoxy resin (Epoxy), or a photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but not limited thereto. At this point, the stress buffer layer 164 is formed on the upper surface 141 of the encapsulant 142 and extends into the trench B to expose a portion of the solder ball 130.
Then, referring to fig. 1D and fig. 1E, the carrier 10 is removed to expose the lower surface 143 of the encapsulant 142.
Finally, referring to fig. 1E and fig. 1F, a singulation process is performed to cut the stress buffer layer 164 and the encapsulant 142 to form a plurality of chip package structures (schematically illustrated as four chip package structures 100a) separated from each other. At this time, the cut stress buffer layer 160a covers the first side surface 145 and the upper surface 141 of the cut encapsulant 140, and the outer surface 167 of the cut stress buffer layer 160a is aligned with the second side surface 147 of the cut encapsulant 140. Thus, the chip package structure 100a is completed.
Structurally, referring to fig. 1G, a chip package structure 100a of the present embodiment includes a chip 110, a redistribution layer 120, solder balls 130, a molding compound 140, and a stress buffer layer 160 a. The chip 110 has an active surface 112 and a back surface 114 opposite to each other and a peripheral surface 116 connecting the active surface 112 and the back surface 114. The redistribution layer 120 is disposed on the active surface 112 of the chip 110, wherein the redistribution layer 120 includes a circuit layer 122 and a conductive via 124. The conductive via 124 is located between the circuit layer 122 and the active surface 112 of the chip 110, wherein the chip 110 is electrically connected to the circuit layer 122 through the conductive via 124. The solder balls 130 are disposed on the redistribution layer 120, and the chip 110 is electrically connected to the solder balls 130 through the redistribution layer 120.
Furthermore, the encapsulant 140 of the present embodiment covers the active surface 112 and the back surface 114 of the chip 110, the redistribution layer 120, and a portion of the solder balls 130. More specifically, the encapsulant 140 has an upper surface 141 and a lower surface 143 opposite to each other. The side surface connects the upper surface 141 and the lower surface 143, and includes a first side surface 145 and a second side surface 147. A first vertical distance G1 exists between the upper surface 141 of the encapsulant 140 and the active surface 112 of the chip 110, a second vertical distance G2 exists between the lower surface 143 of the encapsulant 140 and the back surface 114 of the chip 110, and the first vertical distance G1 is greater than the second vertical distance G2.
In particular, the stress buffer layer 160a covers the peripheral surface 116 of the chip 110 and extends to cover the first side surface 145 and the upper surface 141 of the encapsulant 140, wherein the outer surface 167 of the stress buffer layer 160a is aligned with the second side surface 147. Here, the material of the stress buffer layer 160a is different from that of the encapsulant 140, wherein the material of the stress buffer layer 160a is, for example, Silane coupling agent polymer (Silane coupling agent), silicone rubber (silicone rubber), Epoxy resin (Epoxy), or photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but not limited thereto.
In addition, the chip package structure 100a of the present embodiment further includes a surface treatment layer 150 disposed on the redistribution layer 120 and located between the solder balls 130 and the redistribution layer 120. The surface treatment layer 150 may be, for example, Nickel palladium Immersion Gold (ENEPIG), Organic Solderability Preservations (OSP), or Electroless Nickel Immersion Gold (ENIG), but is not limited thereto.
In the embodiment, the encapsulant 140 covers the active surface 112 and the back surface 114 of the chip 110, the redistribution layer 120 and the solder balls 130, and the stress buffer layer 160a covers at least the peripheral surface 116 of the chip 110 (the stress buffer layer 160a may protrude downward or be flush with the chip 110). That is, the active surface 112 and the back surface 114 of the chip 110 are protected by the encapsulant 140, and the peripheral surface 116 of the chip 110 is protected by the stress buffer layer 160 a. That is, the edge of the chip 110 is effectively protected by the stress buffer layer 160a, and the structural strength of the chip package structure 100a is increased by the encapsulant 140, so that the chip package structure 100a of the present embodiment has better structural reliability.
It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Fig. 2A to fig. 2C are schematic cross-sectional views illustrating partial steps of a method for manufacturing a chip package structure according to another embodiment of the invention. Fig. 2D is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention.
The manufacturing method of the chip package structure 100b of the present embodiment is similar to the manufacturing method of the chip package structure 100a, and the difference between the two methods is: referring to fig. 2A, a carrier 10 and a package semi-finished product FB are provided, wherein the package semi-finished product FB is disposed on the carrier 10. In detail, the package semi-finished product FB includes a plurality of chips 110, a redistribution layer 120, a plurality of solder balls 130, an encapsulant 142, and a stress buffer layer 162 b. The chips 110 are separated from each other, and each chip 110 has an active surface 112 and a back surface 114 opposite to each other and a peripheral surface 116 connecting the active surface 112 and the back surface 114. The redistribution layer 120 is disposed on the active surface 112 of the chip 110, wherein the redistribution layer 120 includes a circuit layer 122 and a conductive via 124. The conductive via 124 is located between the circuit layer 122 and the active surface 112 of the chip 110, and the chip 110 is electrically connected to the circuit layer 122 through the conductive via 124. Each chip 110 is electrically connected to each corresponding solder ball 130 through the redistribution layer 120.
Furthermore, the encapsulant 142 of the present embodiment covers the active surface 112 and the back surface 114 of each chip 110, the redistribution layer 120, the corresponding portion of the solder ball 130, and the stress buffer layer 162 b. In particular, in the present embodiment, the stress buffer layer 162b covers the peripheral surface 116 of each chip 110, and the height H of the stress buffer layer 162b is equal to or slightly greater than the thickness T of each chip 110. Here, the material of the stress buffering layer 162b is different from that of the encapsulant 142, wherein the material of the stress buffering layer 162b is, for example, Silane coupling agent polymer (Silane coupling agent), silicone rubber (silicone rubber), Epoxy resin (Epoxy), or photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but not limited thereto. In addition, the package semi-finished product FB of the present embodiment further includes a surface treatment layer 150 disposed on the redistribution layer 120 and located between the solder balls 130 and the redistribution layer 120. The surface treatment layer 150 is, for example, Nickel palladium Immersion Gold (ENEPIG), Organic Solderability Preservations (OSP), or Electroless Nickel Immersion Gold (ENIG), but is not limited thereto.
In brief, the Package semi-finished product FB of the present embodiment is embodied as a Fan-out Wafer Level Chip Package (Fan out WLCSP) structure, which reassembles the Chip 110 on the carrier 10, and completes the circuit and ball-mounting process after the stress buffer layer 162b is used to protect the peripheral surface 116 of the Chip 110.
Next, referring to fig. 2A and fig. 2B, a singulation process is performed to cut the stress buffer layer 162B and the encapsulant 142, so as to form a plurality of chip package structures 100B separated from each other. At this time, the side surface 148 of the encapsulant 140 is cut to be flush with the outer surface 168 of the stress buffer layer 160 b. Finally, referring to fig. 2B and fig. 2C, the carrier 10 is removed to expose the lower surface 143 of the encapsulant 140, thereby completing the fabrication of the chip package structure 100B.
Referring to fig. 1G and fig. 2D, the chip package structure 100b of the present embodiment is similar to the chip package structure 100a, and the difference between the two structures is: the stress buffer layer 160b of the present embodiment only covers the peripheral surface 116 of the chip 110, and the height H of the stress buffer layer 160b may be equal to or slightly greater than the thickness T of the chip 110. Here, the material of the stress buffer layer 160b is different from that of the encapsulant 140, wherein the material of the stress buffer layer 160b is, for example, Silane coupling agent polymer (Silane coupling agent), silicone rubber (silicone rubber), Epoxy resin (Epoxy), or photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but not limited thereto.
In the embodiment, the encapsulant 140 covers the active surface 112 and the back surface 114 of the chip 110, and the stress buffer layer 160b covers the peripheral surface 116 of the chip 110. That is, the active surface 112 and the back surface 114 of the chip 110 are protected by the encapsulant 140, and the peripheral surface 116 of the chip 110 is protected by the stress buffer layer 160 b. The edge of the chip 110 is effectively protected by the stress buffer layer 160b, and the structural strength of the chip package structure 100b is increased by the encapsulant 140, so that the chip package structure 100b of the present embodiment has better structural reliability.
In summary, in the chip package structure of the present invention, the active surface and the back surface of the chip are protected by the encapsulant, and the peripheral surface of the chip is protected by the stress buffer layer. Therefore, the edge of the chip is effectively protected by the arrangement of the stress buffer layer, and the structural strength of the chip packaging structure is increased by the arrangement of the packaging colloid, so that the chip packaging structure has better structural reliability.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (20)

1. A chip package structure, comprising:
a chip having an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface;
the reconfiguration circuit layer is configured on the active surface of the chip;
the solder balls are configured on the reconfiguration circuit layer, and the chip is electrically connected with the solder balls through the reconfiguration circuit layer;
the packaging colloid covers the active surface and the back surface of the chip, the reconfiguration line layer and part of the solder balls; and
and the stress buffer layer at least covers the peripheral surface of the chip, wherein the outer surface of the stress buffer layer is aligned with the side surface of the packaging colloid.
2. The chip package structure according to claim 1, wherein the redistribution layer comprises a circuit layer and at least one conductive via, the at least one conductive via is located between the circuit layer and the active surface of the chip, and the chip is electrically connected to the circuit layer through the at least one conductive via.
3. The chip package structure according to claim 1, further comprising:
and the surface treatment layer is configured on the reconfiguration circuit layer and is positioned between the solder balls and the reconfiguration circuit layer.
4. The chip package structure according to claim 1, wherein the encapsulant has an upper surface and a lower surface opposite to each other, the side surface connects the upper surface and the lower surface, the side surface includes a first side surface and a second side surface, the stress buffer layer further extends to cover the first side surface and the upper surface, and the outer surface of the stress buffer layer is aligned with the second side surface.
5. The chip package structure according to claim 4, wherein a first vertical distance is provided between the upper surface of the encapsulant and the active surface of the chip, and a second vertical distance is provided between the lower surface of the encapsulant and the back surface of the chip, and the first vertical distance is greater than the second vertical distance.
6. The chip package structure according to claim 1, wherein the stress buffer layer has a height equal to or slightly greater than a thickness of the chip.
7. The chip package structure according to claim 1, wherein the stress buffer layer is made of a material different from that of the encapsulant, and the stress buffer layer comprises a silane coupling agent polymer, silicone rubber, epoxy resin, or a photosensitive dielectric material.
8. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
providing a semi-finished package product, wherein the semi-finished package product comprises a wafer, a reconfiguration circuit layer, a plurality of solder balls and a package colloid, the reconfiguration circuit layer is positioned between the solder balls and the wafer, and the package colloid coats the wafer, the reconfiguration circuit layer and part of the solder balls;
forming a plurality of grooves in the encapsulant, wherein the grooves are criss-cross and extend from an upper surface of the encapsulant and penetrate through the wafer, so that the wafer is divided into a plurality of chips, each of the chips has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface, the redistribution layer is disposed on the active surface of the chip, each of the chips is electrically connected with each of the corresponding solder balls through the redistribution layer, and the encapsulant covers the active surface and the back surface of each of the chips, the redistribution layer and the corresponding part of the solder balls;
forming a stress buffer layer on the upper surface of the encapsulant and extending into the plurality of trenches, wherein the stress buffer layer exposes a portion of the solder balls; and
and performing a singulation process to cut the stress buffer layer and the encapsulant to form a plurality of chip package structures separated from each other, wherein the encapsulant has an upper surface and a lower surface opposite to each other and side surfaces connecting the upper surface and the lower surface, the side surfaces include a first side surface and a second side surface, the stress buffer layer covers the first side surface and the upper surface, and an outer surface of the stress buffer layer is aligned with the second side surface.
9. The method for manufacturing the chip package structure according to claim 8, further comprising:
before providing the semi-finished package, providing a carrier plate, wherein the semi-finished package is configured on the carrier plate; and
before the singulation process, the carrier is removed to expose the lower surface of the encapsulant.
10. The method of claim 8, wherein the redistribution layer comprises a trace layer and at least one conductive via, the at least one conductive via is located between the trace layer and the active surface of the chip, and the chip is electrically connected to the trace layer through the at least one conductive via.
11. The method for manufacturing a chip package structure according to claim 8, wherein the semi-finished package further comprises:
and the surface treatment layer is configured on the reconfiguration circuit layer and is positioned between the plurality of solder balls and the reconfiguration circuit layer.
12. The method for manufacturing the chip package structure according to claim 8, wherein the step of forming the stress buffer layer comprises:
forming a stress buffer material layer on the upper surface of the packaging colloid and extending and configured in the grooves, wherein the stress buffer material layer covers the solder balls; and
and performing a plasma etching procedure to remove a part of the stress buffer material layer to expose a part of the solder balls and form the stress buffer layer.
13. The method of claim 8, wherein a first vertical distance is provided between the upper surface of the encapsulant and the active surface of the chip, and a second vertical distance is provided between the lower surface of the encapsulant and the back surface of the chip, and the first vertical distance is greater than the second vertical distance.
14. The method of claim 8, wherein the stress buffer layer is made of a material different from that of the encapsulant, and the stress buffer layer comprises a silane coupling agent polymer, silicone rubber, epoxy resin, or photosensitive dielectric material.
15. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
providing a semi-finished package product, wherein the semi-finished package product comprises a plurality of chips, a reconfiguration circuit layer, a plurality of solder balls, a package colloid and a stress buffer layer, the chips are separated from each other, and each of the plurality of chips has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface, the redistribution layer is configured on the active surface of the chip, each of the plurality of chips is electrically connected with each of the plurality of corresponding solder balls through the redistribution layer, the packaging colloid covers the active surface and the back surface of each of the plurality of chips, the reconfiguration line layer, the corresponding part of the solder balls and the stress buffer layer, the stress buffer layer covers the peripheral surface of each of the plurality of chips, and the height of the stress buffer layer is equal to or slightly larger than the thickness of each of the plurality of chips; and
and carrying out a monomer procedure to cut the stress buffer layer and the packaging colloid to form a plurality of chip packaging structures separated from each other, wherein the side surface of the packaging colloid is aligned with the outer surface of the stress buffer layer.
16. The method for manufacturing the chip package structure according to claim 15, further comprising:
before providing the semi-finished package product, providing a carrier plate, wherein the semi-finished package product is configured on the carrier plate; and
after the singulation process is performed, the carrier is removed to expose the lower surface of the encapsulant.
17. The method of claim 15, wherein the redistribution layer comprises a trace layer and at least one conductive via, the at least one conductive via is located between the trace layer and the active surface of the chip, and the chip is electrically connected to the trace layer through the at least one conductive via.
18. The method for manufacturing a chip package structure according to claim 15, wherein the semi-finished package further comprises:
and the surface treatment layer is configured on the reconfiguration circuit layer and is positioned between the plurality of solder balls and the reconfiguration circuit layer.
19. The method of claim 15, wherein the encapsulant has an upper surface and a lower surface opposite to each other and the side surfaces connecting the upper surface and the lower surface, the upper surface of the encapsulant has a first vertical distance from the active surface of the chip, the lower surface of the encapsulant has a second vertical distance from the back surface of the chip, and the first vertical distance is greater than the second vertical distance.
20. The method of claim 15, wherein the stress buffer layer is made of a material different from that of the encapsulant, and the stress buffer layer comprises a silane coupling agent polymer, silicone rubber, epoxy resin, or photosensitive dielectric material.
CN202011584196.5A 2020-12-28 2020-12-28 Chip packaging structure and manufacturing method thereof Pending CN114695282A (en)

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